|Publication number||US5877043 A|
|Application number||US 09/028,014|
|Publication date||Mar 2, 1999|
|Filing date||Feb 23, 1998|
|Priority date||Feb 1, 1996|
|Also published as||EP0788158A2, EP0788158A3, US5760465|
|Publication number||028014, 09028014, US 5877043 A, US 5877043A, US-A-5877043, US5877043 A, US5877043A|
|Inventors||David James Alcoe, Steven Wayne Anderson, Yifan Guo, Eric Arthur Johnson|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Referenced by (167), Classifications (34), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of U.S. Ser. No. 08/595,108, filed Feb. 1, 1996, now U.S. Pat. No. 5,760,465.
This invention relates to electronic packages and particularly those which utilize flexible circuitry and semiconductor devices (chips). Such packages may be used in such products as information handling systems (computers).
Electronic packages of the variety described above are known in the art. Examples are defined in detail in U.S. Pat. Nos. 5,435,732 (Angulas et al), 5,397,921 (Karnezos), 5,386,341 (Olson et al), 5,278,724 (Angulas et al), 4,873,123 (Canestaro et al) and 5,383,787 (Switky et al).
As defined therein, such packages typically include a semiconductor device (chip) electrically coupled to one side of a circuitized substrate such as a flexible circuit member, which typically comprises a dielectric, e.g., polyimide, having at least one layer of circuitry, e.g., copper thereon. Such a chip may be coupled, electrically, to the flexible circuit member's circuitry using solder. See, e.g., U.S. Pat. No. 5,435,732 at FIG. 10. A well-known technique for accomplishing such a solder coupling includes what is known in the industry as a controlled collapse chip connection (C4) procedure. Another known process is a thermal compression bonding (TCB) procedure. Because both processes are known, further description is not believed necessary. The flexible circuitry (often called a tape) may then be coupled electrically to respective circuitry, e.g. copper pads or lines, formed on the surfaces of a circuitized substrate, such as another flex circuit, a more rigid printed circuit board, a ceramic substrate, or the like. Circuit boards, usually comprised of several layers of dielectric material, e.g., fiberglass-reinforced epoxy resin, interspersed with various conductor levels, e.g., power, signal and/or ground planes, and often including plated through-holes and/or internal conductive vias, are known in the art and further definition is not believed necessary.
The above packages also typically utilize a heat sink member which is thermally coupled to the package's chip, the heat sink being located slightly above the chip and provided with a good thermal path to the chip to enhance heat removal from the completed package (most particularly the chip) during package operation. Such heat sinks usually comprise a metallic element located on the package in such a position as to facilitate thermal removal by interaction with a cooling airflow or, simply, relatively non-moving ambient air. The heat sink may be attached to the chip with an appropriate thermal adhesive, several of which are known in the art. To further promote heat removal, the heat sink typically includes appropriate fins, pins, or the like at various locations. The heat sink may also be of a multilayer (or multilevel) design, where each level of the heat sink is optimized for a particular function. The first level of the heat sink may be designed to optimize the thermal contact with the chip and the removal and spreading of heat from the chip, along with the function of protecting the chip and attached circuitry from chemical or other contact from various manufacturing processes. The heat sink's second level may be optimized for thermal interaction with cooling fluid flow (gas or liquid) to provide additional thermal efficiency if demanded by a particular application. This second level of the heat sink may be a separate element, attached to the first level structure by thermal adhesive. It is possible that the first heat sink level may comprise a low-profile, platelike member with the second level including a plurality of fins so that in combination, very high rates of heat removal may be realized. However, if very high thermal performance is not needed, the second level of heat sink may be omitted.
In U.S. Pat. No. 5,397,921, an example is shown of a chip electrically connected to a tape by at least two methods. A one-level heat sink design is used, with the heat sink material chosen to be a specifically designed metallic compound so as to match the coefficient of thermal expansion (CTE) of the heat sink to that of the chip. However, such a choice will not adequately match the CTE of the tape to the chip. Since the chip is bonded to the tape, there exists a mismatch in expansion coefficients, and thus thermally-induced stresses will occur on the circuitry of the tape. Such stresses, typically the result of temperature changes during package operation, can adversely affect the package, including possibly rendering it inoperative.
To utilize various thermal epoxies for heat sink attachment, the temperature of the entire package must be elevated during production in order to cure the epoxy into a useful material state. Because of the mismatch of thermal expansion coefficients between the tape and chip, high tensile stresses are thus created between the chip and the bulk of the tape. These stresses have occasionally resulted in wrinkling of the tape, which in turn results in substantial, unpredictable, and uncontrollable non-planarity of portions of the tape. Such non-planarity can interfere with subsequent electrical connection procedures involving the package's circuitry. Such interference can be great enough to render the package unusable or can contribute to unreliable subsequent electrical connections. This mechanism of failure is further aggravated by the use of larger size chips which are considered necessary in many of today's electronic package assemblies in order to assure enhanced operational capabilities demanded of such structures.
It is also known that some procedures of electrically connecting the chip to the circuitry of the tape (a/k/a chip bonding) require the use of substantially elevated chip temperatures. A primary example is the aforementioned TCB procedure, which requires relatively high temperatures and pressures to satisfactorily effect chip and tape connections. As the connection is formed, the temperature of the chip is significantly greater than that of the bulk of the tape. Subsequent cooling of the bonded chip and tape results in high tensile stresses between both elements. As mentioned, such stresses have been found of sufficient magnitude to induce wrinkles in the tape.
In accordance with the teachings of the present invention, it has been found that it is possible to avoid the condition of high tensile stresses, which cause the condition of tape wrinkling, by the use of strain relief means between the chip and the tape. Significantly, use of this invention permits the highly advantageous utilization of larger and more complex chips in such electronic packages, thereby advancing the art of electronics and electronic packaging in general. Further, such use of strain relief in turn permits the use of a wide variety of high-temperature cured thermal adhesives with such larger chips, while preventing tape wrinkling.
For a chip package to accommodate numerous sizes, designs and types of chips, it is not always possible to precisely know what the effective CTE of a chip will be. Therefore, it is not possible to choose the heat sink material CTE to match that of the chip, as there is known to be a range of chip material CTE values depending on the exact chip material composition (e.g., silicon or gallium arsenide), processing and coating of the chip material, and the extent of circuitry on the chip. Even if the CTE of the heat sink material was perfectly matched to that of the chip, temperature gradients or differences between the heat sink and the chip may cause an unacceptable expansion mismatch. Thus, for a variety of practical reasons, there will in general exist a mismatch of expansion between the chip and the heat sink, giving rise to thermally induced stresses in any thermal epoxy used to bond the two members. As understood, these stresses can be substantial, causing fracture, debonding, and loss of thermal contact between heat sink and chip. Such conditions may also lead to chip overheating and disconnection from the tape. In order to avoid these failures, the present invention also details a means of reducing these stresses and improving the adhesion between the adhesive and heat sink, if such adhesive is utilized. Further, a simple means of providing additional support and bracing to promote contact between the chip and heat sink is described. This additional support can be necessary if a relatively large, massive heat sink is required, and the strength of the thermal adhesive (e.g., epoxy) alone is not sufficient. As understood from the following, implementation of this invention will enable the successful use of relatively large, heavy heat sinks, made of a heat sink material which is not necessarily chosen to be a particular match to any of a wide variety of large, complex, and varied chips.
Because the chip is bonded to the tape, and there exists a relatively significant mismatch in expansion coefficients, small thermally-induced stresses can occur during use of the tape's circuitry. These stresses are not necessarily of the high tensile nature described above (which can cause wrinkling), but instead are relatively small and may occur at the location of the circuitry on the tape that is directly coupled to the chip. The action of heating an electronic package and subsequently cooling thereof is known as thermal cycling. It is known that even very small stresses can induce fatigue fracture in the circuitry after a relatively large number of such cycles, such fatigue fracture possibly resulting in a loss of electrical conductivity of a circuit line (and thus failure of the entire package). To reduce these stresses, it has been found that providing a fillet of a particular configuration can also be effective as stress relief means. These stresses can also be redirected away from circuit lines near the chip (which are relatively fine and narrow) to more robust electrical lines farther away from the chip, using the teachings of the invention.
It is believed that an electronic package assembly possessing the above and other advantageous features which is thus capable of overcoming the several aforementioned problems, and a method of making such a package assembly, would constitute significant advancements in the art.
It is, therefore, a primary object of the present invention to enhance the art of electronic packages and particularly those packages for use in the computer industry.
It is another object of the invention to provide an electronic package which overcomes the aforementioned disadvantages of various known packages.
It is a still further object of the invention to provide an electronic package which can be produced in a relatively inexpensive manner, and which is adaptable to mass production techniques for such packages.
In accordance with one aspect of the invention, there is defined an electronic package which includes a stiffener member, a flexible circuitized substrate secured to the stiffener member, and a semiconductor device. The flexible circuitized substrate includes at least one dielectric layer and at least one conductive layer with a plurality of signal lines, with selected lines having a projecting lead portion. The semiconductor device is electrically connected to selected ones of the projecting lead portions and selected ones of the plurality of signal lines on the flexible circuitized substrate are each adapted for being electrically connected to an external conductive element. The improvement to the electronic package comprises the inclusion of strain relief means in the projecting lead portions at a location adjacent the connection between the lead portions and the semiconductor device.
In accordance with another aspect of the invention, there is provided a method of making an electronic package which comprises the steps of providing a stiffener member, securing a flexible circuitized substrate to the stiffener member, the substrate including at least one dielectric layer and at least one conductive layer located on the dielectric layer and including a plurality of signal lines each having a projecting lead portion adapted for being electrically coupled to an external conductive element when the element is positioned on the flexible circuitized substrate, spacedly positioning a semiconductor device relative to the stiffener member and electrically coupling the semiconductor device to the projecting lead portions of the flexible circuitized substrate. Significantly, the method as taught herein further includes the step of providing strain relief means in the flexible circuitized substrate at a location relative to the location of the electrical coupling between the semiconductor device and the projecting lead portions of the signal lines.
In accordance with yet another aspect of the invention, there is provided an information handling system comprising an electronic package including a stiffener member, a flexible circuitized substrate secured to the stiffener member and including at least a first dielectric layer, at least one conductive layer located on the first dielectric layer and including a plurality of signal lines each having a projecting lead portion as part thereof, which project a predetermined distance from the first dielectric layer, selected ones of the signal lines adapted for being electrically connected to respective ones of external conductive elements when the external conductive elements are positioned on the flexible circuitized substrate, and a semiconductor device including a plurality of contact sites thereon. Selected ones of the contact sites are electrically coupled to respective ones of the projecting lead portions of the signal lines and spacedly positioned from the stiffener, the projecting lead portions of the signal lines of the flexible circuitized substrate including strain relief means therein at a location adjacent the connection between the projecting lead portions and the contact sites of the semiconductor device.
FIG. 1 is a partial, side sectional view, in elevation and on a much enlarged scale, of an electronic package of known construction. (It is understood herein that the center line CL--CL in all of the drawing Figures indicates a mirror image of the illustrated section exists to the left of said line. The partial views provided herein, all on an enlarged scale, are shown herein in such a manner for ease of illustration purposes);
FIG. 2 is a partial side, sectional view of an electronic package in accordance with one embodiment of the invention. Strain relief means are included on projecting signal lead portions, and a bonding apparatus which can form the strain relief means and electrically connect the semiconductor device to the selected lead portions is depicted;
FIG. 2B is a partial plan, sectional view of a part of an electronic package in accordance with one embodiment of the invention. A feathered edge portion formed within a second layer of dielectric used to cover portions of the flexible circuit's signal lines is depicted;
FIG. 3 is a partial side, sectional view of another electronic package of known construction, a protective coating on the semiconductor device being depicted;
FIG. 4 is a partial side, sectional view of an electronic package in accordance with another embodiment of the invention. Strain relief means is depicted on the invention's projecting lead portions, while also shown is a tapered protective encapsulant coating to provide even further strain relief;
FIG. 5 is a partial side, sectional view of an electronic package in accordance with an embodiment of the invention, wherein a forming means is shown which is capable of forming the protective coating on the semiconductor device in a predetermined shape;
FIG. 6 is a partial side, sectional view of an electronic package as shown in FIG. 5, including a tapered protective coating on the semiconductor device and parts of the invention's flexible substrate;
FIG. 7 is a partial side, sectional view of an electronic package in accordance with another embodiment of the invention, including a tapered protective coating on the semiconductor device such as shown above, and additional strain relief means for the invention's projecting lead portions. Also illustrated is another stress-reducing feature (this in the heat sink) near the semiconductor device's perimeter.
For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings. It is understood that like numerals may be used to indicate like elements from Figure to Figure.
In FIG. 1, there is shown an electronic package 11 of known configuration. Package 11 includes a stiffener member 13, a flexible circuitized substrate 15 secured to stiffener 13 (e.g., with adhesive 17), a semiconductor device 19 (e.g., a chip) electrically connected at contact sites 21 to selected signal lines 23 of conductive layer 24 of substrate 15, and external conductive elements 25 (e.g., solder balls).
It is understood that, although only one of each is shown, more than one contact site 21 and projecting lead portion 31 of signal lines 23 are preferably utilized in the invention. In one example, a total of 647 contact sites and lead portions were successfully used. Further, it is understood that chip 19 may include conductive sites around its entire periphery (typically of rectangular configuration) and that flexible circuitized substrate 15 may define an opening (e.g., below chip 19) of similar configuration as the chip but slightly wider, with projecting lead portions 23 extending from each of the circuit's dielectric layer's internal edges which define such an opening. Rectangular openings in flexible circuitry designed to accommodate rectangularly configured semiconductor chips are known in the art, and further description is not necessary.
Typical materials used in flexible circuitized substrate 15 include copper (or copper alloy) for the signal lines 23 and any associated ground plane 27 (if used), and polyimide for the flexible substrate's dielectric layer 29. Stiffener member 13 is typically copper or aluminum. Conductive elements 25 can be either high-melt (e.g., 90:10 which is 90 percent lead and 10 percent tin) solder or lower melting point (e.g., 37:63) solder. Adhesive 17 is typically a soft elastomeric film, and may be selected from several known adhesives in the field.
Chip 19 is electrically connected to the flexible substrate's signal lines 23 at the illustrated, respective contact sites 21. Such connection is to a small projecting portion of the signal line 23 which projects from beyond the internal edge 28 of the dielectric layer 29. Each projecting portion of lines 23 thus forms a projecting lead portion 31. In FIG. 1, no strain relief exists between chip 19 and the flexible substrate 15, due to the direct physical bond (connection) at contact site 21. The bond at site 21 is typically rapidly formed using a known thermal compression process with a known hot bonding apparatus 33 (e.g., as depicted in FIG. 2). Such a procedure normally only takes about one second, including connection of all sites simultaneously in this manner. In one example, a total of 647 sites have been bonded. During this procedure, the bulk (larger, remaining portion) of the substrate and the metal stiffener remain at or near room temperature. Subsequent heating of the entire package 11 may thus bring about high tensile stresses in the portion of the substrate 15 located immediately below the gap between the stiffener member 13 and chip 19, due primarily to the higher CTE of both the stiffener 13 and substrate 15 compared to that of the chip 19 (typically by a magnitude of about 5:1 to 7:1). Because of the lack of acceptable strain relief between chip 19 and substrate 15, a detrimental condition known as "wrinkling" may occur to the flexible circuitized substrate 15 due to these high tensile stresses. This wrinkled condition can even delaminate substrate 15 from adhesive 17, and also prevent successful utilization of external conductive elements 25 to form an electrical connection to external conductive elements, e.g., conductive pads, on a circuit board. (The pads (26) are only shown in FIG. 7 of the drawings, and are understood to lie on a circuitized substrate such as a printed circuit board 26' located below the embodiments in the drawings such that elements 25 each physically engage a respective pad to form a connection thereto. None of the other parts shown in the drawings physically engage the board in the final version of the invention.)
In FIG. 2, there is shown an electronic package 12 in accordance with one embodiment of this invention. Package 12 overcomes the aforementioned problem associated with wrinkling through the provision of strain relief means 37. Strain relief means 37 comprises a substantial bend of the projecting lead portion 31 relative to the regular plane of the substrate's circuitry 23 (and dielectric layer 29). Such a bend, or offset, can be rapidly and conveniently formed by modifying the alignment of known bonding apparatus 33. As the thermal compression bonding apparatus 33 moves to press the projecting lead portion 31 against the chip's contact site 21 (bonding apparatus 33 is shown in its withdrawn position in solid in FIG. 2, and in its advanced engagement position in phantom), the relatively weaker and more flexible projecting lead portion 31 is substantially bent upward toward the chip and, significantly, slightly moved back in the direction indicated by arrow 39. This simultaneous movement continues until the physical bond is formed at site 21, after which the bonding apparatus 33 is withdrawn, leaving the projecting lead portion 31 bent from its normally planar configuration and formed to include strain relief means 37. During this process, the flexible circuitized substrate 15 may similarly be formed to include an indentation 38, which further enhances strain relief at this location. Significantly, projecting lead portion 31 is also electrically connected at site 21 to chip 19. With strain relief means 37, relative movement between the chip and the stiffener resulting from subsequent heating of completed package 12 (e.g., as shown in FIG. 7) is substantially absorbed (accommodated) without high tensile stress generation in the aforementioned "window area" between stiffener 13 and the chip. Thus, wrinkling of the improved substrate 15' is substantially eliminated by the simultaneous action of forming strain relief means 37 and bonding the chip at site 21. The forming of indentation 38 of substrate 15 has similar effect. It is again worth mentioning that this action results in the projecting lead portion 31 being deflected and simultaneously withdrawn (arrow 39), while still assuring formation of an effective electrical connection between portion 31 and chip contact site 21.
In FIG. 2, there is shown a second dielectric layer 41, which can be included to further protect signal lines 23 from debris, chemicals, and the like as may be encountered during various manufacturing processes and utilization of the finished electronic package 12. This second dielectric layer can also be polyimide bonded with a known suitable adhesive to the underlying signal lines 23 and first dielectric layer 29. Layer 41 may also be a conforming film of protective adhesive known as solder mask material, e.g., Vacrel, typically 2 mils thick. (Vacrel is a trademark of E. I. DuPont deNemours & Company.) The inclusion of second dielectric layer 41 also has the added beneficial effect of stiffening and strengthening the flexible circuitized substrate 15' in the area (designated as "A" in FIG. 2) between chip 19 and stiffener 13. The transition of low stiffness from the unprotected projecting signal line portion 31 to high stiffness of the flexible circuitized substrate 15' can be made more gradual by including a feathered edge portion 42 (FIG. 2B). This gradual change in stiffness gives a gradual change in strain of the signal lines 23 across the feathered portion 42, thus avoiding an undesirable stress concentration from abrupt change in stiffness.
An illustration of such a feathered edge portion is shown in FIG. 2B, which shows the second dielectric layer coverlay fashioned into a series of tapered forward edge portions 44. FIG. 2B is a partial plan view, looking down on package 12 (from a position at the top in FIG. 2). The known methods of die-cutting, punching, or photoetching may be used to form the feathered edge portions. It is preferred that the number of tapered forward edge portions coincides with the number and placement of signal lines 23, specifically, one pair of tapered edges per line. Although tapered edges are shown, there are other patterns of edges which assure graduation of stiffness to avoid serious stress concentration, e.g., linear taper, parabolic taper, series of non-tapered features (like a comb), staggered rectangular, etc. The invention is thus not limited to the V-shaped tapers depicted. The choice of a linearly tapered feature appears most suitable for economical manufacture, however.
Also in FIG. 2, a region of moderated thermal expansivity 40 is depicted as part of ground plane 27. The CTE of the material in region 40 is chosen to be at least as great as that of chip 19, but no greater than the flexible circuitized substrate 15', so that the difference in thermal strain between the chip 19 and substrate 15' is significantly reduced in this critical area. The region 40 may include the entire substrate 15' or just an area surrounding the chip 19 as depicted in FIG. 2. There are numerous known materials suitable for this purpose, such as Invar or other iron-nickel compounds, nickel, chromium, tungsten, molybdenum, etc. which can be electroplated or sputtered onto the first dielectric layer 29 (along region 40) and/or the ground plane 27, so that the thermal strain difference is reduced in this region. Beyond region 40, (that area beneath stiffener 13), however, the thermal strain differential may be relatively increased, because, in the present design, the circuit lines 23 "fanout" and are therefore wider in size and thus more fatigue resistant. Also, the flexible circuitized substrate 15' is bonded to the stiffener 13 and thus better supported to avoid wrinkling.
In FIG. 3, there is illustrated the known electronic package 11 of FIG. 1 with the addition of a protective coating of encapsulant material 43 surrounding the sides and contact surfaces of chip 19, projecting lead portions 31, and contact sites 21. Suitable compositions of the encapsulant material are known in the art, and are typically a filled epoxy dispensed in viscous form followed by temperature cure to cause solidification.
Typical encapsulant dispense processes known in the art can result in formation of a sharply ending, steep fillet 45 due to the viscosity of the uncured encapsulant material, as depicted in FIG. 3. This fillet shape, which sharply terminates about one-half the distance between chip and stiffener, has been found to be undesirable, because such sharpness (steepness) forcibly concentrates thermal expansion stress on circuit line 23 near the edge 47 of the fillet. In FIG. 4, there is depicted an improved electronic package 49 over the embodiment of FIG. 3. This package includes a chip 19, projecting lead portions 31 (only one shown), and contact sites 21 (only one shown) surrounded by encapsulant material 43, which has a substantially greater tapered fillet 51. The more gradual change of the encapsulant material thickness over circuit lines 23, thicker at the chip 19 while thinning as the distance from the chip increases, including to the point of intersection between the adhesive 17's forward edge and line 23, results in little or no thermal stress concentration on circuit lines 23.
Dispensing encapsulant material 43 into a sharp fillet 45 (FIG. 3) is caused when using today's dispensing processes/apparatus and typical low viscosity uncured encapsulant materials. To obtain the desired tapered fillet 51 with said material, forming means 53 (FIG. 5) is used. Forming means 53 (depicted in FIG. 5 without encapsulant material 43 having been dispensed) comprises a woven mesh collar form member 54 frictionally pressed in place around chip 19. Typical material suitable for form member 53 include open-woven stranded nylon (0.5 to 1 mil thick), pressed into the depicted shape, to which the uncured encapsulant material 43 (FIG. 6) will wet. As the viscous, uncured encapsulant material is dispensed, capillary action of the mesh pulls material 43 into the desirable shape of a tapered fillet 51. Leaving the form member 53 in place, the encapsulant material 43 is then thermally cured into solid form, as depicted in FIG. 6. The open weave of the collar used as forming means 53 allows gases to escape from the encapsulant during thermal cure. The rectangular form member 53 includes a central rectangular opening designed to precisely conform to the rectangular chip's perimeter 55, and an outer, rectangular edge designed to conform to adhesive 17's inner edge 57. Contact with the stiffener's adhesive 17 holds the form member 53 in place during encapsulant dispense and curing.
In FIG. 7, an improved electronic package 59 is depicted, utilizing strain relief means 37, second dielectric layer 41, and a gradually tapered fillet 51 (including mesh 54 which remains as part of package 59). Additionally, a heat sinking member 61 is attached. Typical known materials for member 61 include copper and aluminum, or alloys thereof Copper materials are typically plated with nickel for corrosion resistance and aluminum materials are typically anodized. It is known, however, that poor adhesion often occurs between many known thermal epoxies and nickel-plated material. To enhance adhesion, the heatsink of the invention preferably includes a plurality of channels 63 which serve to increase heatsink surface area while increasing the effective adhesion strength. Channels 63 may be used to increase adhesion strength of adhesive used over the chip 19 (thermal adhesive 65), over the stiffener 13 (stiffener adhesive 67), or both. Channels 63 may be cut, stamped, or etched into the heatsink, depending on the most economical method available. Obtaining a channel depth of 1 to 2 mils with a channel width of 2 to 3 mils has resulted in a significant increase in the effective adhesion strength. Several patterns of the channels 63 on the face of heatsink 61 have been evaluated and found to be acceptable, including parallel, crisscross, radial, circular, curved, herringbone, and overlapped crossings at angles to form small pillars, posts, or raised areas. Thus, the pattern of the channels is not particularly important for increasing strength, but the use of a radially oriented pattern originating at the approximate center of the corresponding chip 19 may help to promote complete filling of the channels with adhesive as the heatsink 61 is pressed onto the uncured adhesives 65 and 67 (toward chip 19).
To significantly reduce shear strain in the thermal adhesive located between the chip and heatsink, a general increase in thickness of the adhesive may prove to be effective. However, a general increase in thickness decreases thermal transfer efficiency. It has been found that strain relief means 69 can be built into heatsink 61 by thinning a portion of the heatsink in regions adjacent the chip's perimeter 55. Thus, a thin layer of adhesive 65 is used over most of the chip 19 (promoting beneficial thermal transfer between the chip and heatsink), with a thicker layer of adhesive near the chip perimeter 55 to relieve thermal strain (such strain is highest near the chip perimeter 55). Typical thickness for known thermal adhesives are 1-8 mils, and it has been found that significant strain reduction is obtained by at least doubling the nominal adhesive thickness near the chip perimeter using strain relief means 69. In one example, a nominal adhesive thickness of 3 mils over chip 19 which gradually increased to 6-8 mils in regions near the chip perimeter proved successful. This outer thickness may be as high as 5 to 10 times the nominal internal thickness, and may extend about 15 to 30 mils from the chip's perimeter (to the right in FIG. 7). The fabrication operations used to form channels 63 may be used to form strain relief means 69, with stamping being particularly convenient as the channels 63 and strain relief means 69 may be simultaneously stamped into the heatsink.
In FIG. 7, the improved electronic package is further enhanced by including a tab portion 71 along the outer peripheral portion of stiffener 13'. This tab is shown interlocking with a corresponding slot 73 formed in heatsink 61. The improvement of stiffener 13' over stiffener 13 (as depicted in previous figures) by including tab portion 71 provides added positive retention of the heatsink to the rest of the electronic package, providing further stress relief to the thermal adhesives 65 and 67 (useful prior to curing of the adhesives), which can be particularly important if a relatively heavy heatsink 61 is utilized. Tab portion 71 can be of two types: permanently deformable or spring-locking; the choice primarily being economic. It has been found that using an extension of the stiffener, formed by stamping it approximately 10 mils thick at several locations about the outer edge of the stiffener, provides sufficient material to bend around onto corresponding slot features 73 of the retained heatsink.
Thus there has been shown and described an improved electronic package in which strain relief means are provided to substantially prevent adverse conditions such as tape "wrinkling" should excessive CTE differentials exist. The modifications are readily possible using many known processes and thus do not significantly increase the final cost of the finished product.
While there have been shown and described what are at present considered the preferred embodiments of the invention, it is understood that various modifications and changes may be made thereto without departing from the scope of the invention as defined by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4873123 *||Sep 29, 1987||Oct 10, 1989||International Business Machines Corporation||Flexible electrical connection and method of making same|
|US5016084 *||Apr 2, 1990||May 14, 1991||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device|
|US5168430 *||Apr 21, 1989||Dec 1, 1992||Robert Bosch Gmbh||Flexible printed circuit connecting means for at least one hybrid circuit structure and a printed circuit board|
|US5278724 *||Jul 6, 1992||Jan 11, 1994||International Business Machines Corporation||Electronic package and method of making same|
|US5340771 *||Mar 18, 1993||Aug 23, 1994||Lsi Logic Corporation||Techniques for providing high I/O count connections to semiconductor dies|
|US5352632 *||May 17, 1993||Oct 4, 1994||Kabushiki Kaisha Toshiba||Multichip packaged semiconductor device and method for manufacturing the same|
|US5383787 *||Apr 27, 1993||Jan 24, 1995||Aptix Corporation||Integrated circuit package with direct access to internal signals|
|US5383788 *||May 20, 1993||Jan 24, 1995||W. L. Gore & Associates, Inc.||Electrical interconnect assembly|
|US5386341 *||Nov 1, 1993||Jan 31, 1995||Motorola, Inc.||Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape|
|US5397921 *||Sep 3, 1993||Mar 14, 1995||Advanced Semiconductor Assembly Technology||Tab grid array|
|US5435732 *||Aug 11, 1994||Jul 25, 1995||International Business Machines Corporation||Flexible circuit member|
|US5474957 *||Apr 28, 1995||Dec 12, 1995||Nec Corporation||Process of mounting tape automated bonded semiconductor chip on printed circuit board through bumps|
|US5756380 *||Nov 2, 1995||May 26, 1998||Motorola, Inc.||Method for making a moisture resistant semiconductor device having an organic substrate|
|EP0613336A1 *||Feb 7, 1994||Aug 31, 1994||International Business Machines Corporation||Printed circuit card latching and stiffening assembly|
|GB2116370A *||Title not available|
|JPS6457588A *||Title not available|
|JPS63314884A *||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6143981 *||Jun 24, 1998||Nov 7, 2000||Amkor Technology, Inc.||Plastic integrated circuit package and method and leadframe for making the package|
|US6274927||Jun 3, 1999||Aug 14, 2001||Amkor Technology, Inc.||Plastic package for an optical integrated circuit device and method of making|
|US6281568||Oct 21, 1998||Aug 28, 2001||Amkor Technology, Inc.||Plastic integrated circuit device package and leadframe having partially undercut leads and die pad|
|US6320251||Jan 18, 2000||Nov 20, 2001||Amkor Technology, Inc.||Stackable package for an integrated circuit|
|US6404046||Feb 3, 2000||Jun 11, 2002||Amkor Technology, Inc.||Module of stacked integrated circuit packages including an interposer|
|US6420204||Apr 20, 2001||Jul 16, 2002||Amkor Technology, Inc.||Method of making a plastic package for an optical integrated circuit device|
|US6424031||May 8, 2000||Jul 23, 2002||Amkor Technology, Inc.||Stackable package with heat sink|
|US6433277||Jul 13, 2000||Aug 13, 2002||Amkor Technology, Inc.||Plastic integrated circuit package and method and leadframe for making the package|
|US6448633||Nov 19, 1999||Sep 10, 2002||Amkor Technology, Inc.||Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant|
|US6455356||Sep 14, 1999||Sep 24, 2002||Amkor Technology||Methods for moding a leadframe in plastic integrated circuit devices|
|US6476478||Nov 12, 1999||Nov 5, 2002||Amkor Technology, Inc.||Cavity semiconductor package with exposed leads and die pad|
|US6484708 *||Jan 9, 2002||Nov 26, 2002||Hitachi, Ltd.||Resin sealed electronic device|
|US6501171||Jan 30, 2001||Dec 31, 2002||International Business Machines Corporation||Flip chip package with improved cap design and process for making thereof|
|US6518659||May 8, 2000||Feb 11, 2003||Amkor Technology, Inc.||Stackable package having a cavity and a lid for an electronic device|
|US6521987||Oct 31, 2000||Feb 18, 2003||Amkor Technology, Inc.||Plastic integrated circuit device package and method for making the package|
|US6528179||Oct 19, 2000||Mar 4, 2003||International Business Machines Corporation||Reduction of chip carrier flexing during thermal cycling|
|US6566164||Dec 7, 2000||May 20, 2003||Amkor Technology, Inc.||Exposed copper strap in a semiconductor package|
|US6570250 *||Feb 24, 2000||May 27, 2003||Honeywell International Inc.||Power conditioning substrate stiffener|
|US6605865||Oct 19, 2001||Aug 12, 2003||Amkor Technology, Inc.||Semiconductor package with optimized leadframe bonding strength|
|US6608366||Apr 15, 2002||Aug 19, 2003||Harry J. Fogelson||Lead frame with plated end leads|
|US6611047||Oct 12, 2001||Aug 26, 2003||Amkor Technology, Inc.||Semiconductor package with singulation crease|
|US6627977||May 9, 2002||Sep 30, 2003||Amkor Technology, Inc.||Semiconductor package including isolated ring structure|
|US6630728||Jun 14, 2002||Oct 7, 2003||Amkor Technology, Inc.||Plastic integrated circuit package and leadframe for making the package|
|US6667544||Jun 30, 2000||Dec 23, 2003||Amkor Technology, Inc.||Stackable package having clips for fastening package and tool for opening clips|
|US6684496||Oct 22, 2001||Feb 3, 2004||Amkor Technology, Inc.||Method of making an integrated circuit package|
|US6696318 *||Apr 29, 2002||Feb 24, 2004||Medtronic, Inc.||Methods for forming a die package|
|US6700187||Mar 21, 2002||Mar 2, 2004||Amkor Technology, Inc.||Semiconductor package and method for manufacturing the same|
|US6713322||Dec 10, 2001||Mar 30, 2004||Amkor Technology, Inc.||Lead frame for semiconductor package|
|US6723582||Jan 31, 2003||Apr 20, 2004||Amkor Technology, Inc.||Method of making a semiconductor package having exposed metal strap|
|US6750545||Feb 28, 2003||Jun 15, 2004||Amkor Technology, Inc.||Semiconductor package capable of die stacking|
|US6756658||Apr 6, 2001||Jun 29, 2004||Amkor Technology, Inc.||Making two lead surface mounting high power microleadframe semiconductor packages|
|US6759737||Mar 23, 2001||Jul 6, 2004||Amkor Technology, Inc.||Semiconductor package including stacked chips with aligned input/output pads|
|US6777789||Jan 10, 2003||Aug 17, 2004||Amkor Technology, Inc.||Mounting for a package containing a chip|
|US6784534||Feb 6, 2002||Aug 31, 2004||Amkor Technology, Inc.||Thin integrated circuit package having an optically transparent window|
|US6790710||Jan 31, 2002||Sep 14, 2004||Asat Limited||Method of manufacturing an integrated circuit package|
|US6794740||Mar 13, 2003||Sep 21, 2004||Amkor Technology, Inc.||Leadframe package for semiconductor devices|
|US6798046||Jan 22, 2002||Sep 28, 2004||Amkor Technology, Inc.||Semiconductor package including ring structure connected to leads with vertically downset inner ends|
|US6798047||Dec 26, 2002||Sep 28, 2004||Amkor Technology, Inc.||Pre-molded leadframe|
|US6803645||Dec 26, 2001||Oct 12, 2004||Amkor Technology, Inc.||Semiconductor package including flip chip|
|US6818972 *||Sep 30, 2002||Nov 16, 2004||International Business Machines Corporation||Reduction of chip carrier flexing during thermal cycling|
|US6818973||Sep 9, 2002||Nov 16, 2004||Amkor Technology, Inc.||Exposed lead QFP package fabricated through the use of a partial saw process|
|US6825062||May 22, 2002||Nov 30, 2004||Amkor Technology, Inc.||Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant|
|US6841414||Jun 19, 2002||Jan 11, 2005||Amkor Technology, Inc.||Saw and etch singulation method for a chip package|
|US6847103||Nov 9, 1999||Jan 25, 2005||Amkor Technology, Inc.||Semiconductor package with exposed die pad and body-locking leadframe|
|US6858919||Mar 23, 2001||Feb 22, 2005||Amkor Technology, Inc.||Semiconductor package|
|US6861720||Aug 29, 2001||Mar 1, 2005||Amkor Technology, Inc.||Placement template and method for placing optical dies|
|US6867071||Jul 12, 2002||Mar 15, 2005||Amkor Technology, Inc.||Leadframe including corner leads and semiconductor package using same|
|US6879034||May 1, 2003||Apr 12, 2005||Amkor Technology, Inc.||Semiconductor package including low temperature co-fired ceramic substrate|
|US6885086||Mar 5, 2002||Apr 26, 2005||Amkor Technology, Inc.||Reduced copper lead frame for saw-singulated chip package|
|US6921967||Sep 24, 2003||Jul 26, 2005||Amkor Technology, Inc.||Reinforced die pad support structure|
|US6927478||Jan 11, 2002||Aug 9, 2005||Amkor Technology, Inc.||Reduced size semiconductor package with stacked dies|
|US6977431||Nov 5, 2003||Dec 20, 2005||Amkor Technology, Inc.||Stackable semiconductor package and manufacturing method thereof|
|US7042068||Apr 27, 2001||May 9, 2006||Amkor Technology, Inc.||Leadframe and semiconductor package made using the leadframe|
|US7183630||Jun 11, 2003||Feb 27, 2007||Amkor Technology, Inc.||Lead frame with plated end leads|
|US7226821 *||Jun 24, 2005||Jun 5, 2007||Cardiac Pacemakers, Inc.||Flip chip die assembly using thin flexible substrates|
|US7497911||Aug 15, 2006||Mar 3, 2009||Cardiac Pacemakers, Inc.||Flip chip die assembly using thin flexible substrates|
|US7687893||Dec 27, 2006||Mar 30, 2010||Amkor Technology, Inc.||Semiconductor package having leadframe with exposed anchor pads|
|US7687899||Aug 7, 2007||Mar 30, 2010||Amkor Technology, Inc.||Dual laminate package structure with embedded elements|
|US7692286||Aug 5, 2008||Apr 6, 2010||Amkor Technology, Inc.||Two-sided fan-out wafer escape package|
|US7696621 *||Jul 5, 2007||Apr 13, 2010||Microstrain, Inc.||RFID tag packaging system|
|US7714431||Nov 28, 2006||May 11, 2010||Amkor Technology, Inc.||Electronic component package comprising fan-out and fan-in traces|
|US7723210||Jun 6, 2007||May 25, 2010||Amkor Technology, Inc.||Direct-write wafer level chip scale package|
|US7723852||Jan 21, 2008||May 25, 2010||Amkor Technology, Inc.||Stacked semiconductor package and method of making same|
|US7732899||Feb 4, 2009||Jun 8, 2010||Amkor Technology, Inc.||Etch singulated semiconductor package|
|US7768135||Apr 17, 2008||Aug 3, 2010||Amkor Technology, Inc.||Semiconductor package with fast power-up cycle and method of making same|
|US7777351||Oct 1, 2007||Aug 17, 2010||Amkor Technology, Inc.||Thin stacked interposer package|
|US7808084||May 6, 2008||Oct 5, 2010||Amkor Technology, Inc.||Semiconductor package with half-etched locking features|
|US7829990||Jan 18, 2007||Nov 9, 2010||Amkor Technology, Inc.||Stackable semiconductor package including laminate interposer|
|US7847386||Nov 5, 2007||Dec 7, 2010||Amkor Technology, Inc.||Reduced size stacked semiconductor package and method of making the same|
|US7847392||Sep 30, 2008||Dec 7, 2010||Amkor Technology, Inc.||Semiconductor device including leadframe with increased I/O|
|US7875963||Nov 21, 2008||Jan 25, 2011||Amkor Technology, Inc.||Semiconductor device including leadframe having power bars and increased I/O|
|US7902660||May 24, 2006||Mar 8, 2011||Amkor Technology, Inc.||Substrate for semiconductor device and manufacturing method thereof|
|US7906855||Apr 12, 2010||Mar 15, 2011||Amkor Technology, Inc.||Stacked semiconductor package and method of making same|
|US7928542||Mar 6, 2009||Apr 19, 2011||Amkor Technology, Inc.||Lead frame for semiconductor package|
|US7932595||Mar 19, 2010||Apr 26, 2011||Amkor Technology, Inc.||Electronic component package comprising fan-out traces|
|US7956453||Jan 16, 2008||Jun 7, 2011||Amkor Technology, Inc.||Semiconductor package with patterning layer and method of making same|
|US7960818||Mar 4, 2009||Jun 14, 2011||Amkor Technology, Inc.||Conformal shield on punch QFN semiconductor package|
|US7968998||Jun 21, 2006||Jun 28, 2011||Amkor Technology, Inc.||Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package|
|US7977163||Jul 2, 2009||Jul 12, 2011||Amkor Technology, Inc.||Embedded electronic component package fabrication method|
|US7977774||Jul 10, 2007||Jul 12, 2011||Amkor Technology, Inc.||Fusion quad flat semiconductor package|
|US7982297||Mar 6, 2007||Jul 19, 2011||Amkor Technology, Inc.||Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same|
|US7982298||Dec 3, 2008||Jul 19, 2011||Amkor Technology, Inc.||Package in package semiconductor device|
|US7989933||Oct 6, 2008||Aug 2, 2011||Amkor Technology, Inc.||Increased I/O leadframe and semiconductor device including same|
|US8008758||Oct 27, 2008||Aug 30, 2011||Amkor Technology, Inc.||Semiconductor device with increased I/O leadframe|
|US8026589||Feb 23, 2009||Sep 27, 2011||Amkor Technology, Inc.||Reduced profile stackable semiconductor package|
|US8058715||Jan 9, 2009||Nov 15, 2011||Amkor Technology, Inc.||Package in package device for RF transceiver module|
|US8067821||Apr 10, 2008||Nov 29, 2011||Amkor Technology, Inc.||Flat semiconductor package with half package molding|
|US8072050||Nov 18, 2008||Dec 6, 2011||Amkor Technology, Inc.||Semiconductor device with increased I/O leadframe including passive device|
|US8084868||Jun 18, 2010||Dec 27, 2011||Amkor Technology, Inc.||Semiconductor package with fast power-up cycle and method of making same|
|US8089141||Jan 25, 2010||Jan 3, 2012||Amkor Technology, Inc.||Semiconductor package having leadframe with exposed anchor pads|
|US8089145||Nov 17, 2008||Jan 3, 2012||Amkor Technology, Inc.||Semiconductor device including increased capacity leadframe|
|US8089159||Oct 3, 2007||Jan 3, 2012||Amkor Technology, Inc.||Semiconductor package with increased I/O density and method of making the same|
|US8102037||Feb 28, 2011||Jan 24, 2012||Amkor Technology, Inc.||Leadframe for semiconductor package|
|US8119455||Mar 18, 2011||Feb 21, 2012||Amkor Technology, Inc.||Wafer level package fabrication method|
|US8125064||Jul 28, 2008||Feb 28, 2012||Amkor Technology, Inc.||Increased I/O semiconductor package and method of making same|
|US8184453||Jul 31, 2008||May 22, 2012||Amkor Technology, Inc.||Increased capacity semiconductor package|
|US8188579||Dec 10, 2010||May 29, 2012||Amkor Technology, Inc.||Semiconductor device including leadframe having power bars and increased I/O|
|US8188584||Mar 19, 2010||May 29, 2012||Amkor Technology, Inc.||Direct-write wafer level chip scale package|
|US8227921||Nov 7, 2011||Jul 24, 2012||Amkor Technology, Inc.||Semiconductor package with increased I/O density and method of making same|
|US8294276||May 27, 2010||Oct 23, 2012||Amkor Technology, Inc.||Semiconductor device and fabricating method thereof|
|US8298866||Jan 26, 2012||Oct 30, 2012||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US8299602||Oct 26, 2010||Oct 30, 2012||Amkor Technology, Inc.||Semiconductor device including leadframe with increased I/O|
|US8304866||Jun 2, 2011||Nov 6, 2012||Amkor Technology, Inc.||Fusion quad flat semiconductor package|
|US8318287||Jan 19, 2011||Nov 27, 2012||Amkor Technology, Inc.||Integrated circuit package and method of making the same|
|US8319338||Jul 8, 2010||Nov 27, 2012||Amkor Technology, Inc.||Thin stacked interposer package|
|US8324511||Apr 6, 2010||Dec 4, 2012||Amkor Technology, Inc.||Through via nub reveal method and structure|
|US8390130||Jan 6, 2011||Mar 5, 2013||Amkor Technology, Inc.||Through via recessed reveal structure and method|
|US8410585||Mar 10, 2006||Apr 2, 2013||Amkor Technology, Inc.||Leadframe and semiconductor package made using the leadframe|
|US8432023||Jun 15, 2011||Apr 30, 2013||Amkor Technology, Inc.||Increased I/O leadframe and semiconductor device including same|
|US8440554||Aug 2, 2010||May 14, 2013||Amkor Technology, Inc.||Through via connected backside embedded circuit features structure and method|
|US8441110||May 17, 2011||May 14, 2013||Amkor Technology, Inc.||Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package|
|US8486764||Sep 26, 2012||Jul 16, 2013||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US8487420||Dec 8, 2008||Jul 16, 2013||Amkor Technology, Inc.||Package in package semiconductor device with film over wire|
|US8487445||Oct 5, 2010||Jul 16, 2013||Amkor Technology, Inc.||Semiconductor device having through electrodes protruding from dielectric layer|
|US8501543||May 16, 2012||Aug 6, 2013||Amkor Technology, Inc.||Direct-write wafer level chip scale package|
|US8552548||Nov 29, 2011||Oct 8, 2013||Amkor Technology, Inc.||Conductive pad on protruding through electrode semiconductor device|
|US8558365||Sep 27, 2011||Oct 15, 2013||Amkor Technology, Inc.||Package in package device for RF transceiver module|
|US8575742||Apr 6, 2009||Nov 5, 2013||Amkor Technology, Inc.||Semiconductor device with increased I/O leadframe including power bars|
|US8633575 *||May 24, 2012||Jan 21, 2014||Amkor Technology, Inc.||IC package with integrated electrostatic discharge protection|
|US8648450||Jan 27, 2011||Feb 11, 2014||Amkor Technology, Inc.||Semiconductor device including leadframe with a combination of leads and lands|
|US8680656||Jan 5, 2009||Mar 25, 2014||Amkor Technology, Inc.||Leadframe structure for concentrated photovoltaic receiver package|
|US8691632||Jun 14, 2013||Apr 8, 2014||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US8710649||Sep 5, 2013||Apr 29, 2014||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US8729682||May 3, 2011||May 20, 2014||Amkor Technology, Inc.||Conformal shield on punch QFN semiconductor package|
|US8729710||Apr 26, 2011||May 20, 2014||Amkor Technology, Inc.||Semiconductor package with patterning layer and method of making same|
|US8791501||Dec 3, 2010||Jul 29, 2014||Amkor Technology, Inc.||Integrated passive device structure and method|
|US8796561||Oct 5, 2009||Aug 5, 2014||Amkor Technology, Inc.||Fan out build up substrate stackable package and method|
|US8823152||Jul 12, 2011||Sep 2, 2014||Amkor Technology, Inc.||Semiconductor device with increased I/O leadframe|
|US8853547 *||Oct 9, 2009||Oct 7, 2014||Conti Temic Microelectronic Gmbh||Flexible printed board|
|US8853836||Oct 29, 2012||Oct 7, 2014||Amkor Technology, Inc.||Integrated circuit package and method of making the same|
|US8900995||Jun 26, 2013||Dec 2, 2014||Amkor Technology, Inc.||Semiconductor device and manufacturing method thereof|
|US8937381||Dec 3, 2009||Jan 20, 2015||Amkor Technology, Inc.||Thin stackable package and method|
|US8952522||Apr 29, 2014||Feb 10, 2015||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US8963301||Dec 27, 2013||Feb 24, 2015||Amkor Technology, Inc.||Integrated circuit package and method of making the same|
|US8981572||Sep 4, 2013||Mar 17, 2015||Amkor Technology, Inc.||Conductive pad on protruding through electrode semiconductor device|
|US9048298||Mar 29, 2012||Jun 2, 2015||Amkor Technology, Inc.||Backside warpage control structure and fabrication method|
|US9054117||Dec 30, 2014||Jun 9, 2015||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US9082833||Jan 31, 2013||Jul 14, 2015||Amkor Technology, Inc.||Through via recessed reveal structure and method|
|US9129943||Mar 29, 2012||Sep 8, 2015||Amkor Technology, Inc.||Embedded component package and fabrication method|
|US9159672||Apr 12, 2013||Oct 13, 2015||Amkor Technology, Inc.||Through via connected backside embedded circuit features structure and method|
|US9184118||May 2, 2014||Nov 10, 2015||Amkor Technology Inc.||Micro lead frame structure having reinforcing portions and method|
|US9184148||Oct 22, 2014||Nov 10, 2015||Amkor Technology, Inc.||Semiconductor package and method therefor|
|US9224676||Jan 8, 2015||Dec 29, 2015||Amkor Technology, Inc.||Integrated circuit package and method of making the same|
|US9275939||Dec 13, 2013||Mar 1, 2016||Amkor Technology, Inc.||Semiconductor device including leadframe with a combination of leads and lands and method|
|US9324614||Oct 29, 2012||Apr 26, 2016||Amkor Technology, Inc.||Through via nub reveal method and structure|
|US9362210||Feb 10, 2013||Jun 7, 2016||Amkor Technology, Inc.||Leadframe and semiconductor package made using the leadframe|
|US9406645||Jun 9, 2015||Aug 2, 2016||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US9431323||Feb 5, 2015||Aug 30, 2016||Amkor Technology, Inc.||Conductive pad on protruding through electrode|
|US9508631||Dec 30, 2015||Nov 29, 2016||Amkor Technology, Inc.||Semiconductor device including leadframe with a combination of leads and lands and method|
|US20020020907 *||Mar 23, 2001||Feb 21, 2002||Amkor Technology, Inc.||Semiconductor package|
|US20020093087 *||Jan 11, 2002||Jul 18, 2002||Paek Jong Sik||Semiconductor package with stacked dies|
|US20020093093 *||Jan 11, 2002||Jul 18, 2002||Jong Sik Paek||Semiconductor package with stacked dies|
|US20020127837 *||Apr 29, 2002||Sep 12, 2002||Medtronic, Inc.||Methods for forming a die package|
|US20030020146 *||May 22, 2002||Jan 30, 2003||Yee Jae Hak||Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant|
|US20030034566 *||Sep 30, 2002||Feb 20, 2003||Jimarez Lisa J.||Reduction of chip carrier flexing during thermal cycling|
|US20030178719 *||Mar 22, 2002||Sep 25, 2003||Combs Edward G.||Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package|
|US20030197290 *||May 16, 2003||Oct 23, 2003||Crowley Sean Timothy||Stackable semiconductor package and method for manufacturing same|
|US20040046241 *||Aug 11, 2003||Mar 11, 2004||Combs Edward G.||Method of manufacturing enhanced thermal dissipation integrated circuit package|
|US20040065905 *||Oct 7, 2003||Apr 8, 2004||Jong Sik Paek||Semiconductor package and method for manufacturing the same|
|US20050077613 *||Aug 6, 2003||Apr 14, 2005||Mclellan Neil Robert||Integrated circuit package|
|US20060290007 *||Aug 15, 2006||Dec 28, 2006||Cardiac Pacemakers, Inc.||Flip Chip Die Assembly Using Thin Flexible Substrates|
|US20060292756 *||Jun 24, 2005||Dec 28, 2006||Cardiac Pacemakers, Inc.||Flip chip die assembly using thin flexible substrates|
|US20080009149 *||Jul 5, 2007||Jan 10, 2008||Arms Steven W||RFID tag packaging system|
|US20090166842 *||Mar 6, 2009||Jul 2, 2009||Hyung Ju Lee||Leadframe for semiconductor package|
|US20100213586 *||Feb 17, 2010||Aug 26, 2010||Yamaha Corporation||Semiconductor package and manufacturing method thereof|
|US20110232946 *||Oct 9, 2009||Sep 29, 2011||Andreas Voegerl||Flexible Printed Board|
|CN101814463A *||Feb 11, 2010||Aug 25, 2010||雅马哈株式会社||Semiconductor package and manufacturing method thereof|
|U.S. Classification||438/123, 438/125|
|International Classification||H01L23/498, H01L23/13, H01L21/60, H01L23/495, H01L23/373, H01L23/12, H01L23/16|
|Cooperative Classification||H01L2924/15787, H01L2924/351, H01L2224/2929, H01L2224/293, H01L2224/83851, H01L2924/01074, H01L2924/01033, H01L2924/01023, H01L23/49816, H01L2924/01082, H01L2924/01019, H01L2924/01004, H01L23/13, H01L23/16, H01L2924/01013, H01L2924/01024, H01L24/50, H01L23/49572, H01L2924/01042, H01L2924/01029|
|European Classification||H01L24/50, H01L23/498C4, H01L23/16, H01L23/495J, H01L23/13|
|Feb 23, 1998||AS||Assignment|
Owner name: IBM CORPORATION, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JOHNSON, ERIC A.;REEL/FRAME:009033/0195
Effective date: 19960229
|Jul 16, 2002||FPAY||Fee payment|
Year of fee payment: 4
|Sep 20, 2006||REMI||Maintenance fee reminder mailed|
|Mar 2, 2007||LAPS||Lapse for failure to pay maintenance fees|
|May 1, 2007||FP||Expired due to failure to pay maintenance fee|
Effective date: 20070302
|Sep 3, 2015||AS||Assignment|
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001
Effective date: 20150629
|Oct 5, 2015||AS||Assignment|
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001
Effective date: 20150910