|Publication number||US5880015 A|
|Application number||US 08/323,262|
|Publication date||Mar 9, 1999|
|Filing date||Oct 14, 1994|
|Priority date||Apr 30, 1991|
|Also published as||DE69220615D1, DE69220615T2, EP0511837A2, EP0511837A3, EP0511837B1|
|Publication number||08323262, 323262, US 5880015 A, US 5880015A, US-A-5880015, US5880015 A, US5880015A|
|Inventors||William Y. Hata|
|Original Assignee||Sgs-Thomson Microelectronics, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (19), Referenced by (87), Classifications (20), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of U.S. application Ser. No. 08/104,500, filed Aug. 10, 1993 now abandoned, which was a continuation of U.S. application Ser. No. 07/693,671, filed Apr. 30, 1991 now abandoned, which has been assigned to the assignee hereof and incorporated by reference herein.
The present invention relates generally to semiconductor integrated circuit processing, and more specifically to producing stepped sidewall interconnects and gates.
With the trend to continue to miniaturize semiconductor integrated circuits to achieve submicron feature sizes, photolithography has become one of the most critical steps in semiconductor manufacturing. The goal of photolithography in establishing the horizontal dimensions of the various devices and circuits is to create a pattern which meets design requirements as well as to correctly align the circuit pattern on the surface of the wafer.
As line widths shrink smaller and smaller in submicron photolithography, the process to print lines in photoresist becomes increasingly more difficult. Photoresists have been developed to keep pace with the industry's need to print narrower lines with fewer defects. The selection of the photoresist must be made on whether the photoresist has the capability of producing the design dimensions. The resist must also be able to function as an etchant barrier during the etching step and be free of pinholes. Furthermore, the selection of photoresist must provide for process latitude and step coverage capabilities.
Exposure light sources are chosen in photolithography based upon the characteristics of the photoresist. Standard production exposure tools used to print lines may limit how small the devices can be made. One problem with standard exposure tools is in the auto focus mechanism used to pattern a wafer. The exposure tools, when used in conjunction with thick photoresists have a small depth of focus so that light focused on the top of the photoresist will be out of focus near the bottom of the photoresist.
Production tools with light sources having longer wavelengths also create negative optical effects such as diffraction. Diffraction reduces the resolution of an image in the photoresist causing poor image definition.
Smaller features can be imaged clearly by using thinner photoresist layers for a given photoresist chemistry and optical tool. Thinner photoresists, however, are not suitable for all masking requirements because of the reduced ability to protect masked areas.
A concern in printing submicron devices is the resultant angle of the step from the top of the photoresist to the bottom of the layer in which the device is being made. If the angle is too steep, subsequently deposited layers may be too thin over the step and not fill in the spaces between adjacent devices. Thus, step coverage problems result.
Step coverage problems have been of prime importance throughout the history of integrated circuit manufacture. Poor step coverage can be found at the sharp vertical step metal to substrate contacts, metal to metal vias, and metal crossovers. On the other hand, there is a concern in printing submicron devices in close proximity to adjacent devices. Design criteria requires controlling the cross sectional lengths of the devices. Control of the cross sectional lengths of devices is best achieved when the sidewall slopes of the devices are 90 degrees. The critical dimension, or cross sectional length, is then a function of the critical dimension of the photoresist. If the sidewall slope is not 90 degrees, other factors must be considered in determining the critical dimension of the device, such as the angle of the sidewall slope, photoresist selectivity and the photoresist critical dimension.
As stated above, however, step coverage problems arise when the angle of the slope forms a steep sidewall. For example, as the height of a vertical or 90 degree sidewall increases, the percent of step coverage decreases. The ratio of the sidewall height to the space between adjacent structures is the aspect ratio. Device structures with high aspect ratios only increase step coverage problems. The spaces between the devices become harder to fill. On the other hand, sloped sidewall structures have an advantage over structures with sidewalls having a 90 degree angle because of a lower aspect ratio.
In order to increase step coverage while maintaining a lower aspect ratio, a two-tiered stepped sidewall is proposed by this invention. The step heights of each tier of the stepped sidewall are kept at a minimum, thus lowering the equivalent aspect ratio while increasing step coverage.
It would be desirable to provide a method for printing interconnects and gates having stepped sidewalls to enhance step coverage using thin photoresists. It would be further desirable for such fabrication technique to provide stepped sidewall profiles for use with small device geometries by lowering aspect ratios. It would be further desirable for such method to be compatible with current process technologies.
Therefore, according to the present invention, a method is provided for making submicron interconnects and transistor gates by forming an insulating layer over a substrate and a conductive layer over the insulating layer. The conductive layer is etched to form two-tiered stepped sidewalls.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIGS. 1-9 illustrate one method for forming integrated circuit structures according to the present invention.
FIGS. 10-12 illustrate an alternate method for forming integrated circuit structures according to the present invention.
The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.
Referring to FIG. 1, an integrated circuit device is to be formed in a silicon substrate 10. Selected regions of the substrate 10 are oxidized to form an oxide insulating layer 12. A conductive layer 14 is deposited over the insulating layer 12 by methods known in the art. The conductive layer 14 may a metal or a polysilicon. A first layer of photoresist 16 is formed on the conductive layer. Photoresist layer 16 is then patterned and developed.
Referring to FIG. 2, conductive layer 14 is then etched by methods known in the art, using photoresist layer 16 as a mask. Among the various devices manufactured, conductive layer 14 may be used as an interconnect or as the gate of a field effect transistor. Photoresist layer 16 is then stripped away.
Referring to FIG. 3, second photoresist layer 18 is spun onto the wafer again by known methods covering the remaining regions of conductive layer 14 and the exposed regions of insulating layer 12. Photoresist layers 16 and 18 typically have a thickness of less than 1.2 microns and preferably between approximately 0.1 and 0.5 microns. In order to adequately protect masked areas, one photoresist layer may need to be thicker than the other photoresist layer.
Referring to FIG. 4, photoresist layer 18 is patterned and developed by methods known in the art. The pattern of the second photoresist layer 18 is smaller than the pattern of the first photoresist layer 16. The remaining conductive layer 14 regions are then partially etched using photoresist layer 18 as a mask to form the two-tiered stepped sidewalls as shown in FIG. 5.
Referring to FIG. 6, photoresist layer 18 is stripped away leaving the interconnect or gate device structure shown. The height of each vertical section of the two-tiered stepped sidewalls will be smaller than the total height of the device. Thus, step coverage will improve over the device and the aspect ratio will be lowered.
If a gate of a field effect transistor is to be manufactured, the additional steps necessary to manufacture source and drain regions of the transistor need to be implemented during or after the manufacture of the gate. Referring to FIG. 7, the process steps are the same as above as shown in FIGS. 1-2. An insulating layer 22 is grown on substrate 20. A conductive layer 24 is deposited on insulating layer 22. A first photoresist layer 26 is spun onto the conductive layer 24, patterned and developed. Conductive layer 24 is then etched using photoresist layer 26 as a mask. The source and drain regions are created using two different implantation steps as known in the art. The first implantation step occurs after removing the first photoresist layer 26. Source and drain regions 28 are formed by heavily doping insulating layer 22. The dopant used during these implantation steps may be either N-type or P-type.
Referring to FIG. 8, a second photoresist layer 30 is then spun onto the remaining regions of conductive layer 24 and the exposed regions of insulating layer 22. Photoresist layer 30 is patterned and developed. Conductive layer 24, which forms the gate of a field effect transistor, is then etched to form the two-tiered stepped sidewalls using photoresist layer 30 as a mask. Insulating layer 22 and substrate 20 are lightly doped after the second photoresist layer 30 is removed to form a second source/drain region 32 underneath the step of the conductive layer 24. Again, either N-type or P-type dopants may be used to minimize resistance of these regions. An alternative to implanting dopants at two different stages of the process to form the source/drain regions is to form both source/drain regions 28 and 32 after conductive layer 24 is partially etched to form the two-tiered stepped sidewalls. No sidewall oxide spacers are required in using either alternative in this process to create the source/drain regions. Referring to FIG. 9, the gate device shown as conductive layer 24 is formed with first and second source/drain regions 28 and 32.
Referring to FIG. 10, an alternative method of producing a structure with stepped sidewalls is shown. As above, insulating layer 22 is formed on substrate 20 and conductive layer 24 is formed on insulating layer 22. Photoresist layer 26 is formed on conductive layer 24, patterned and developed. Conductive layer 24 is then etched partway through using photoresist layer 26 as a mask. Photoresist layer 26 is then removed. Sidewall oxide spacers 34 are then formed by methods known in the art at the step of conductive layer 24. Conductive layer 24 is then further etched using sidewall oxide spacers 34 as a mask. If the structure to be manufactured is an interconnect, the sidewall oxide spacers 34 are removed to form the structure shown in FIG. 6.
Referring to FIG. 11, where a gate of a field effect transistor is to be made, two implantation steps are necessary to form source/drain regions 36 and 38. Source/drain regions 36 are first formed by lightly doping the substrate 20 after photoresist layer 26 is removed. Source/drain regions 38 are then formed by heavily doping the substrate 20 after the final etching step of conductive layer 24 and before the sidewall oxide spacers 34 are removed. The sidewall oxide spacers 34 are then removed to form the structure shown in FIG. 12.
This alternative allows a single thin layer of photoresist to clearly image the device, providing for self-alignment. Moreover, by forming sidewall oxide spacers, the source/drain regions of a gate can be easily formed.
Submicron devices, such as interconnects and gates, can be produced with sufficient control to allow for short distances between adjacent devices, if the sidewalls have a 90 degree angle. By forming a two-tiered stepped sidewall using thin photoresists to clearly image the devices, the equivalent aspect ratio is minimized and step coverage maximized allowing the distances between devices to be minimized.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4472237 *||Dec 13, 1982||Sep 18, 1984||At&T Bell Laboratories||Reactive ion etching of tantalum and silicon|
|US4617193 *||Jun 16, 1983||Oct 14, 1986||Digital Equipment Corporation||Planar interconnect for integrated circuits|
|US4764480 *||Oct 23, 1987||Aug 16, 1988||National Semiconductor Corporation||Process for making high performance CMOS and bipolar integrated devices on one substrate with reduced cell size|
|US4818715 *||Jul 9, 1987||Apr 4, 1989||Industrial Technology Research Institute||Method of fabricating a LDDFET with self-aligned silicide|
|US4905068 *||Jan 13, 1988||Feb 27, 1990||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device having interconnection layers of T-shape cross section|
|US4907048 *||Nov 23, 1987||Mar 6, 1990||Xerox Corporation||Double implanted LDD transistor self-aligned with gate|
|US4917759 *||Apr 17, 1989||Apr 17, 1990||Motorola, Inc.||Method for forming self-aligned vias in multi-level metal integrated circuits|
|US4994873 *||Dec 26, 1989||Feb 19, 1991||Motorola, Inc.||Local interconnect for stacked polysilicon device|
|US4996584 *||Oct 13, 1988||Feb 26, 1991||Gould, Inc.||Thin-film electrical connections for integrated circuits|
|US5043294 *||Aug 29, 1990||Aug 27, 1991||Siemens Aktiengesellschaft||Method for manufacturing an FET with asymmetrical gate region|
|US5053841 *||Oct 18, 1989||Oct 1, 1991||Kabushiki Kaisha Toshiba||Nonvolatile semiconductor memory|
|US5061975 *||Feb 20, 1991||Oct 29, 1991||Mitsubishi Denki Kabushiki Kaisha||MOS type field effect transistor having LDD structure|
|US5089863 *||Sep 8, 1988||Feb 18, 1992||Mitsubishi Denki Kabushiki Kaisha||Field effect transistor with T-shaped gate electrode|
|US5100820 *||Jun 6, 1991||Mar 31, 1992||Oki Electric Industry Co., Ltd.||MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode|
|US5113238 *||Jan 6, 1989||May 12, 1992||Wang Chen Chin||Contactless non-volatile memory array cells|
|US5204285 *||Mar 19, 1992||Apr 20, 1993||Matsushita Electronics Corporation||Method for patterning a metal layer|
|US5266508 *||Aug 24, 1992||Nov 30, 1993||Sharp Kabushiki Kaisha||Process for manufacturing semiconductor device|
|US5384479 *||Oct 9, 1992||Jan 24, 1995||Mitsubishi Denki Kabushiki Kaisha||Field effect transistor with T-shaped gate electrode|
|US5578166 *||May 24, 1995||Nov 26, 1996||Fujitsu Limited||Method of reactive ion etching of a thin copper film|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5937326 *||May 30, 1996||Aug 10, 1999||Hyundai Electronics Industries Co., Ltd.||Method for making semiconductor device having via hole|
|US6040220 *||Oct 14, 1997||Mar 21, 2000||Advanced Micro Devices, Inc.||Asymmetrical transistor formed from a gate conductor of unequal thickness|
|US6083816 *||Oct 9, 1998||Jul 4, 2000||Oki Electric Industry Co. Ltd.||Semiconductor device and method of manufacturing the same|
|US6090676 *||Sep 8, 1998||Jul 18, 2000||Advanced Micro Devices, Inc.||Process for making high performance MOSFET with scaled gate electrode thickness|
|US6624473 *||Mar 9, 2000||Sep 23, 2003||Matsushita Electric Industrial Co., Ltd.||Thin-film transistor, panel, and methods for producing them|
|US6800528 *||Feb 20, 2003||Oct 5, 2004||Oki Electric Industry Co., Ltd.||Method of fabricating LDMOS semiconductor devices|
|US6812490||Jun 30, 2003||Nov 2, 2004||Matsushita Electric Industrial Co., Ltd.||Thin-film transistor, panel, and methods for producing them|
|US6815337||Feb 17, 2004||Nov 9, 2004||Episil Technologies, Inc.||Method to improve borderless metal line process window for sub-micron designs|
|US6960517 *||Jun 30, 2003||Nov 1, 2005||Intel Corporation||N-gate transistor|
|US7456476||Jun 27, 2003||Nov 25, 2008||Intel Corporation||Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication|
|US7479421||Sep 28, 2005||Jan 20, 2009||Intel Corporation||Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby|
|US7518196||Feb 23, 2005||Apr 14, 2009||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US7528025||Nov 21, 2007||May 5, 2009||Intel Corporation||Nonplanar transistors with metal gate electrodes|
|US7547637||Jun 21, 2005||Jun 16, 2009||Intel Corporation||Methods for patterning a semiconductor film|
|US7550333||May 23, 2006||Jun 23, 2009||Intel Corporation||Nonplanar device with thinned lower body portion and method of fabrication|
|US7579280||Jun 1, 2004||Aug 25, 2009||Intel Corporation||Method of patterning a film|
|US7714397||Jul 25, 2006||May 11, 2010||Intel Corporation||Tri-gate transistor device with stress incorporation layer and method of fabrication|
|US7736956||Mar 26, 2008||Jun 15, 2010||Intel Corporation||Lateral undercut of metal gate in SOI device|
|US7781771||Aug 24, 2010||Intel Corporation||Bulk non-planar transistor having strained enhanced mobility and methods of fabrication|
|US7820513||Oct 28, 2008||Oct 26, 2010||Intel Corporation||Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication|
|US7825481||Dec 23, 2008||Nov 2, 2010||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US7859053||Jan 18, 2006||Dec 28, 2010||Intel Corporation||Independently accessed double-gate and tri-gate transistors in same process flow|
|US7879675||Feb 1, 2011||Intel Corporation||Field effect transistor with metal source/drain regions|
|US7893506||Feb 22, 2011||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US7898041||Sep 14, 2007||Mar 1, 2011||Intel Corporation||Block contact architectures for nanoscale channel transistors|
|US7902014||Jan 3, 2007||Mar 8, 2011||Intel Corporation||CMOS devices with a single work function gate electrode and method of fabrication|
|US7915167||Mar 29, 2011||Intel Corporation||Fabrication of channel wraparound gate structure for field-effect transistor|
|US7960794||Jun 14, 2011||Intel Corporation||Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow|
|US7989280||Dec 18, 2008||Aug 2, 2011||Intel Corporation||Dielectric interface for group III-V semiconductor device|
|US8067818||Nov 24, 2010||Nov 29, 2011||Intel Corporation||Nonplanar device with thinned lower body portion and method of fabrication|
|US8071983||May 8, 2009||Dec 6, 2011||Intel Corporation||Semiconductor device structures and methods of forming semiconductor structures|
|US8084818||Jan 12, 2006||Dec 27, 2011||Intel Corporation||High mobility tri-gate devices and methods of fabrication|
|US8183646||May 22, 2012||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US8193567||Dec 11, 2008||Jun 5, 2012||Intel Corporation||Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby|
|US8268709||Sep 18, 2012||Intel Corporation||Independently accessed double-gate and tri-gate transistors in same process flow|
|US8273626||Sep 29, 2010||Sep 25, 2012||Intel Corporationn||Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication|
|US8294180||Mar 1, 2011||Oct 23, 2012||Intel Corporation||CMOS devices with a single work function gate electrode and method of fabrication|
|US8362566||Jun 23, 2008||Jan 29, 2013||Intel Corporation||Stress in trigate devices using complimentary gate fill materials|
|US8368135||Apr 23, 2012||Feb 5, 2013||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US8399922||Mar 19, 2013||Intel Corporation||Independently accessed double-gate and tri-gate transistors|
|US8405164||Apr 26, 2010||Mar 26, 2013||Intel Corporation||Tri-gate transistor device with stress incorporation layer and method of fabrication|
|US8502351||Sep 23, 2011||Aug 6, 2013||Intel Corporation||Nonplanar device with thinned lower body portion and method of fabrication|
|US8581258||Oct 20, 2011||Nov 12, 2013||Intel Corporation||Semiconductor device structures and methods of forming semiconductor structures|
|US8617945||Feb 3, 2012||Dec 31, 2013||Intel Corporation||Stacking fault and twin blocking barrier for integrating III-V on Si|
|US8664694||Jan 28, 2013||Mar 4, 2014||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US8741733||Jan 25, 2013||Jun 3, 2014||Intel Corporation||Stress in trigate devices using complimentary gate fill materials|
|US8749026||Jun 3, 2013||Jun 10, 2014||Intel Corporation||Nonplanar device with thinned lower body portion and method of fabrication|
|US8816394||Dec 20, 2013||Aug 26, 2014||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US8933458||Oct 8, 2013||Jan 13, 2015||Intel Corporation||Semiconductor device structures and methods of forming semiconductor structures|
|US9048314||Aug 21, 2014||Jun 2, 2015||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US9190518||May 8, 2014||Nov 17, 2015||Intel Corporation||Nonplanar device with thinned lower body portion and method of fabrication|
|US9224754||May 8, 2014||Dec 29, 2015||Intel Corporation||Stress in trigate devices using complimentary gate fill materials|
|US9337307||Nov 18, 2010||May 10, 2016||Intel Corporation||Method for fabricating transistor with thinned channel|
|US9368583||May 1, 2015||Jun 14, 2016||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US9385180||Dec 18, 2014||Jul 5, 2016||Intel Corporation||Semiconductor device structures and methods of forming semiconductor structures|
|US20030232475 *||Feb 20, 2003||Dec 18, 2003||Katsuhito Sasaki||Method of fabricating LDMOS semiconductor devices|
|US20040089878 *||Jun 30, 2003||May 13, 2004||Matsushita Electric Industrial Co., Ltd.||Thin-film transistor, panel, and methods for producing them|
|US20040262699 *||Jun 30, 2003||Dec 30, 2004||Rafael Rios||N-gate transistor|
|US20050266692 *||Jun 1, 2004||Dec 1, 2005||Brask Justin K||Method of patterning a film|
|US20060046452 *||Aug 19, 2005||Mar 2, 2006||Rafael Rios||N-gate transistor|
|US20060068591 *||Sep 29, 2005||Mar 30, 2006||Marko Radosavljevic||Fabrication of channel wraparound gate structure for field-effect transistor|
|US20060086977 *||Oct 25, 2004||Apr 27, 2006||Uday Shah||Nonplanar device with thinned lower body portion and method of fabrication|
|US20060128131 *||Jan 18, 2006||Jun 15, 2006||Chang Peter L||Independently accessed double-gate and tri-gate transistors in same process flow|
|US20060202266 *||Mar 14, 2005||Sep 14, 2006||Marko Radosavljevic||Field effect transistor with metal source/drain regions|
|US20060261411 *||Jul 25, 2006||Nov 23, 2006||Hareland Scott A||Nonplanar device with stress incorporation layer and method of fabrication|
|US20070001173 *||Jun 21, 2005||Jan 4, 2007||Brask Justin K||Semiconductor device structures and methods of forming semiconductor structures|
|US20070090408 *||Sep 29, 2005||Apr 26, 2007||Amlan Majumdar||Narrow-body multiple-gate FET with dominant body transistor for high performance|
|US20070111419 *||Jan 3, 2007||May 17, 2007||Doyle Brian S||CMOS Devices with a single work function gate electrode and method of fabrication|
|US20070262389 *||Jul 25, 2007||Nov 15, 2007||Robert Chau||Tri-gate transistors and methods to fabricate same|
|US20080090397 *||Nov 21, 2007||Apr 17, 2008||Brask Justin K||Nonplanar transistors with metal gate electrodes|
|US20080142841 *||Feb 4, 2008||Jun 19, 2008||Nick Lindert||Bulk non-planar transistor having strained enhanced mobility and methods of fabrication|
|US20080157225 *||Dec 29, 2006||Jul 3, 2008||Suman Datta||SRAM and logic transistors with variable height multi-gate transistor architecture|
|US20080188041 *||Mar 26, 2008||Aug 7, 2008||Suman Datta||Lateral undercut of metal gate in SOI device|
|US20080258207 *||Sep 14, 2007||Oct 23, 2008||Marko Radosavljevic||Block Contact Architectures for Nanoscale Channel Transistors|
|US20090090976 *||Dec 11, 2008||Apr 9, 2009||Intel Corporation||Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby|
|US20090142897 *||Dec 23, 2008||Jun 4, 2009||Chau Robert S||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US20090149531 *||Dec 10, 2008||Jun 11, 2009||Apoteknos Para La Piel, S.L.||Chemical composition derived from p-hydroxyphenyl propionic acid for the treatment of psoriasis|
|US20090218603 *||May 8, 2009||Sep 3, 2009||Brask Justin K||Semiconductor device structures and methods of forming semiconductor structures|
|US20090325350 *||May 2, 2008||Dec 31, 2009||Marko Radosavljevic||Field effect transistor with metal source/drain regions|
|US20100200917 *||Aug 12, 2010||Hareland Scott A||Nonplanar device with stress incorporation layer and method of fabrication|
|US20100295129 *||Aug 4, 2010||Nov 25, 2010||Chau Robert S||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US20100297838 *||Nov 25, 2010||Chang Peter L D||Independently accessed double-gate and tri-gate transistors in same process flow|
|US20110062512 *||Nov 24, 2010||Mar 17, 2011||Uday Shah||Nonplanar device with thinned lower body portion and method of fabrication|
|US20110062520 *||Nov 18, 2010||Mar 17, 2011||Brask Justin K||Method for fabricating transistor with thinned channel|
|US20110121393 *||May 26, 2011||Chau Robert S||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US20110156145 *||Jun 30, 2011||Marko Radosavljevic||Fabrication of channel wraparound gate structure for field-effect transistor|
|US20110180851 *||Jul 28, 2011||Doyle Brian S||Cmos devices with a single work function gate electrode and method of fabrication|
|U.S. Classification||438/585, 257/E21.314, 257/E21.583, 438/666, 438/669|
|International Classification||H01L29/41, H01L29/49, H01L21/3205, H01L29/43, H01L29/423, H01L29/78, H01L21/768, H01L21/3213, H01L21/336|
|Cooperative Classification||H01L29/6659, H01L21/32139, H01L21/7684|
|European Classification||H01L29/66M6T6F11B3, H01L21/768C2, H01L21/3213D|
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