|Publication number||US5896177 A|
|Application number||US 08/805,333|
|Publication date||Apr 20, 1999|
|Filing date||Feb 24, 1997|
|Priority date||Feb 24, 1996|
|Publication number||08805333, 805333, US 5896177 A, US 5896177A, US-A-5896177, US5896177 A, US5896177A|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (26), Classifications (13), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C §119 from an application entitled Device For Controlling An Aspect Ratio In TV-Monitor Integrated Wide Screen Receiver earlier filed in the Korean Industrial Property Office on Feb. 24, 1996, and there duly assigned Ser. No. 96-4539 by that Office.
1. Field of the Invention
The present invention relates to a device for controlling an aspect ratio in a TV-monitor integrated wide screen receiver. Specifically, this invention is a device for preventing horizontal distortion of a 4×3 picture displayed on a 16×9 wide screen monitor by controlling a sampling clock speed with a phase-locked loop system.
2. Discussion of Related Art
Conventionally, a monitor is similar to a TV receiver from which an antenna unit for receiving waves from a broadcasting station and a tuner unit for processing the waves from a TV receiver are removed. Component video signals and synchronous signals are transmitted to the monitor. The video signals are red (R), green (G), and blue (B) signals. The synchronous signals are horizontal (H) and vertical (V) signals. Composite video and synchronous signals are transmitted to the TV receiver. In a component method, horizontal and vertical frequencies of a picture are flexibly selected, so high resolution can be established. In a TV receiver, a signal band and horizontal and vertical deflection frequencies are determined according to known signaling systems such as NTSC, PAL, and SECAM. A composite method is limited in video signals, horizontal frequency, vertical frequency, video band, color carriers, and horizontal/vertical deflection frequencies so that it is not possible to freely choose frequencies.
Resolution indicates an amount of resolvable detail, and is expressed according to the number of dots or pixels which can be distinguished in a horizontal line and the number of lines which can be distinguished in a vertical frame and may be expressed as "DOT×LINE". For example, a resolution of 640 DOT×480 LINE indicates that the system has a horizontal resolution where up to 640 dots or pixels can be distinguished horizontally and a vertical resolution where up to 480 lines can be distinguished vertically.
Generally, in the United States, the NTSC television standard is set to have an aspect ratio of 4×3 (4:3), the ratio of frame width to frame height. FIG. 1A illustrates a screen whose width-height ratio is 4:3. Wide screen television usually will have an aspect ratio of 16×9 (16:9), and FIG. 1B illustrates a screen whose width-height ratio is 16:9. FIGS. 1C and 1D illustrate how a picture having a 4:3 aspect ratio may be displayed on a screen with an aspect ratio of 16:9, wherein the shaded areas are nonscanned areas of the cathode ray tube.
FIG. 2A shows an image displayed on a screen whose aspect ratio is 4:3. FIG. 2B shows a distorted image of a 4:3 aspect ratio picture displayed on a screen having the 16:9 aspect ratio. FIG. 2C illustrates a picture having the 4:3 aspect ratio being displayed on a screen having a 16:9 aspect ratio and the shaded areas are nonscanned areas for preventing the displayed picture from being distorted.
Where a TV picture of the 4:3 aspect ratio as shown in FIG. 2A, is displayed on a wide screen TV of the 16:9 aspect ratio, the picture is distorted horizontally as shown in FIG. 2B. Where widths of the screens A and B are put as L1 and L2, respectively, and lengths or heights of the two screens are put as H1 and H2, respectively, if the lengths are the same (H1=H2), the ratio of two widths (L1:L2) becomes 3 to 4. To display the 4:3 picture on the 16:9 screen without an image distortion, therefore, the length of the picture must be corrected to be 3/4×L2.
U.S. Pat. No. 5,159,438 to Khosro M. Rabii entitled Aspect Ratio Conversion Of Television Display describes a conventional aspect ratio conversion (ARC) which is applied to video signals and a wide screen TV of 16:9. Video signals in the NTSC system have the 4:3 aspect ratio. The ARC patent is applied to a wide screen TV having an aspect ration of 16:9, where a TV picture of 4:3 is displayed on the wide TV screen of 16:9. In a conventional art, a filter is used for an interpolation after an analog/digital conversion of luminance and chrominance signals, and another filter is used for a compressing method utilizing a difference between memory read and write clock speeds. In the NTSC system, synchronous signals (SYNC) and frequency modulated signals are mixed and then transmitted together through space, and the video signal has a horizontal frequency of 15.75 KHz, and a vertical frequency of 60 fields or 30 frames per second. The conventional art possibly processes signals only in NTSC system so that it cannot be applied to a computer system using a wide display.
Accordingly, the present invention is directed to a device for controlling a change of an aspect ratio that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An objective of the present invention is to provide an aspect ratio control device which is capable of converting an aspect by changing a sampling clock speed with a phase-locked loop, without utilizing a filter for an interpolation, during a video data sampling.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a device for controlling an aspect ratio in a TV-monitor integrated wide screen receiver, includes a select switch for selecting a television signal double-scanned or monitor signal of a VGA mode, a gain controller for controlling a gain of the signal which is selected by the select switch, a clamp circuit for clamping the signal controlled by the gain controller, an analog/digital converter for converting the signal clamped by the clamp circuit, an aspect ratio conversion device for horizontally and vertically converting the digital signal sampled by the analog/digital converter; and a phase-locked loop connected to the analog/digital converter and the aspect ratio conversion device, for correcting an image distortion by controlling a converting clock speed. The phase-locked loop system, which is structured in a dual mode, is composed of a first phase-locked loop for generating an analog/digital converting clock and a write clock in a memory of an aspect ratio converting port; and a second phase-locked loop for generating a memory read clock.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detail description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:
FIG. 1A illustrates a screen having a 4:3 aspect ratio;
FIG. 1B illustrates a screen having a 16:9 aspect ratio;
FIGS. 1C and 1D illustrate the screens of the 16:9 aspect ratio where the pictures of the 4:3 aspect ratio are displayed;
FIG. 2A illustrates a screen having the 4:3 aspect ratio;
FIG. 2B illustrates a distorted image with 4:3 aspect ratio displayed on a screen having the 16:9 aspect ratio;
FIG. 2C illustrates a 4:3 aspect ratio image displayed on a 16:9 aspect ratio screen;
FIG. 3 is a circuit diagram of a device according to the principles of the present invention;
FIG. 4 is a circuit diagram of a phase-locked loop system according to the principles of the present invention;
FIG. 5 is a block diagram of an aspect ratio conversion device according to the principles of the present invention; and
FIGS. 6A and 6B are waveforms of signals according to the principles of the present invention.
Referring now to FIG. 3, the present invention is largely separated into a TV reception unit 10 and a monitor reception unit 20. TV reception unit 10 includes an antenna for receiving waves transmitted through space from a broadcasting station and a tuner 12 responsive to a user interface 20, such as a keyboard or remote control for enabling a viewer to perform various functions such as channel selection and device selection, for providing intermediate frequency signals to filter 14 which separating the signals into a video signal and an audio signal. Switch 16 is responsive to a first control signal CONT1 for selecting either the audio signal of the television (TV) signal or a sound signal from a personal computer for input to audio processor 18 which drives a pair of speakers. A video decoder 22 detects video signals from the tuner. A chrominance converter 24 detects chrominance signals from the video signals which were detected by the video decoder. A double scanner 26 converts a horizontal frequency of 15.73 KHz into that of 31.46 KHz by using a double scanning method or line doubling method thereby changing the input television signal from an interlaced signal to a progressive scanned signal. A matrix circuit 28 converts the video signals double-scanned by the double scanner 26 into R, G, and B data. A low pass filter 30 performs a low pass filtering operation for the signals which passed through the matrix circuit.
Monitor reception unit 20 includes a switch 42 which selects the double-scanned TV signals or VGA mode video signals from a computer in response to a second control signal CONT2, a gain controller 46 which controls the gain of the selected signal, a clamp circuit 48 for clamping the gain controlled signals and an aspect conversion control circuit 30 composed of: an analog/digital converter 52 for converting the signals clamped by clamp circuit 48 into digital signals; an aspect ratio conversion device 54 for sampling the digital signals in accordance with sampling speed clocks provided from a phase-locked loop (PLL) system 60; and a digital/analog converter 56 for converting the signals from aspect ratio conversion device 54 into analog signals. An amplifier 58 amplifies the signals output from D/A converter 56 for display on cathode ray tube 62. Switch 44 is responsive to a third control signal CONT3 for selecting either of the sync signal of the double scanned video signal and or the sync signal of the computer signal for input to phase locked loop system 60. The aspect ratio of the digitalized signal is converted, in accordance with the speed of the clock signals, output by PLL system 60, applied to aspect converter 54, and then the signal is finally displayed on a screen.
The first, second and third control signals may be generated in response to user selection of one of the television signal and the computer signal for display by activation of one or more keys on the keyboard or remote control of interface 20. Additionally, the first, second and third control signals may be one single control signal.
As shown in FIG. 4, PLL system 60 includes first and second PLLs 70 and 80, a multiplier 64 and a switch 66 for selecting either the output of switch 44 or the output of multiplier 64 for input to first PLL 70 based on whether an image is to be displayed at the full size of 16:9 aspect ratio or the 4:3 aspect ratio. PLLs 70 and 80 respectively comprise programmable dividers 78 and 88, phase detectors 72 and 82, low pass filters 74 and 84, and voltage controlled oscillators 76 and 86, wherein phase detectors 72 and 82 compare the phase of the synchronizing signal with the outputs of programmable dividers 78 and 88. Programmable dividers 78 and 88 are similarly programmed. When switch 66 selects the sync signal at input terminal 1, the same frequencies are respectively input to programmable dividers 78 and 88 of first and second PLLs 70 and 80, respectively. Accordingly, the A/D data clock, memory write clock, and memory read clock values have the same frequencies. When switch 66 selects the output of multiplier 64 at input terminal 2, a signal having a frequency equal to 3/4 of the frequency of the sync signal input to the PLL 80 is input to PLL 70. Therefore, A/D sampling clock and memory write clock have 3/4 of frequency which the memory read clock has. PLL system 40 provides timing signals to A/D converter 52 and ARC device 54 for controlling whether an image is displayed at the full size of 16:9 aspect ratio or at the 4:3 aspect ratio.
Aspect conversion control (ARC) unit 50 corrects an aspect distortion which occurs when a picture of 4:3 aspect ratio is displayed on a screen having a 16:9 aspect ratio and is further described with reference to FIG. 5. As shown in FIG. 5, ARC device 54 repeatedly writes and reads data in and from a plurality of line memories 90-100 during a horizontal sync (H-SYNC) period, using the memory write and read clocks provided by PLL system 60. The inputs to line memories 90-100 are provided from A/D converter 52 wherein a digital red R component of the image signal is input to line memories 90 and 92 via switch 102, the digital green G component of the image signal is input to line memories 94 and 96 via switch 106 and the digital blue B component of the image signal is input to line memories 98 and 100 via switch 110. The signals stored in line memories 90-100 are read out via corresponding output switches 104, 108 and 112 as shown in FIG. 5.
The size of video data written in each of line memories 90-100 is the same as that of data converted and sampled by A/D converter 52 in accordance with the A/D sampling clock from PLL 70. Where the A/D converter's sampling clock speed, memory write clock speed, and memory read clock speed have the same values, the picture having a 4:3 aspect ratio is displayed on the screen having a 16:9 aspect ratio with its width being expanded. Where the A/D sampling clock speed and memory write clock speed are 3/4 times as fast as the memory read clock, the size of data written in the memory is reduced by twenty five percent. Since there is no change in memory read clock speed, whole video data is compressed to 3/4 its original horizontal width. Accordingly, on a display screen having a 16:9 aspect ratio a picture having a 16:9 aspect ratio will occupy the whole horizontal width of the display screen when switch 66 in FIG. 4 is connected to input terminal 1, and a picture having a 4:3 aspect ratio will occupy 3/4 the horizontal width of the display screen when switch 66 is connected to input terminal 2. A picture having a 4:3 aspect ratio will occupy the whole horizontal width of the display screen when switch 66 is connected to input terminal 1, but the picture will be horizontally expanded and thus be distorted in the horizontal direction.
The following description referring to the waveform chart of FIG. 6A, is about the operation of ARC unit 50 according to the clock speeds generated by PLL system 60. When switch 66 of FIG. 4 is connected to input terminal 1 the speeds of the A/D clock, memory write clock, and memory read clock r1, r2, r3, r4 are all the same, thus the A/D sampling data a', b', c', d' read from memory has the same size as the A/D data a, b, c, d written into the memory.
The following description referring to the waveform chart of FIG. 6B, is about the operation of ARC unit 50 according to the clock speeds generated by PLL system 60. When switch 66 of FIG. 4 is connected to input terminal 2 the speeds of the A/D clock, and memory write clock are the same. The speed of the memory read clock r1', r2', r3', r4', however, is faster than the memory write clock thus the A/D sampling data a1', b1', c1', a2' read from memory 3/4 the size of the A/D data a1, b1, c1, a2 written into the memory.
One frequency is input to the TV whereas signals of different resolutions corresponding to different frequencies are input to the monitor. In case that the receiver is used as the monitor, the sampling frequency must be controlled, recognizing the resolution of an input signal, when the video data is A/D-sampled. If the sampling amount (the number of dots) is fixed, an image is possibly distorted when the video data is restored or displayed. The correlation between the frequency input to PLL system 60 and the PLL sampling amount, is shown in Table 1 below.
TABLE 1______________________________________PLL sampling amount according to frequencies input sampling ARC samplingHorizontal Vertical amount frequency (4:3)frequency frequency Resolution (16:9) (× 3/4)______________________________________31 KHz X 640 × 480 800 60035 KHz 60.72 Hz 800 × 600 1024 768 over 85 Hz 1024 × 768 1280 96038 KHz 60 Hz 800 × 600 1024 768 70-84 Hz 640 × 480 800 60048 KHz 60 Hz 1024 × 768 1280 960 72 Hz 800 × 600 1024 76856 KHz X 1024 × 768 1280 96061 KHz X 1024 × 768 1280 960over 64 KHz X 1280 × 1024 1664 1248______________________________________
As shown in Table. 1, The sampling operation in the monitor is performed in accordance with the proper input resolution, with considering a sampling amount in case of fully displaying the picture of 4:3 aspect ratio on the screen of 16:9 aspect ratio and a sampling amount in case of converting the aspect ratio.
In the present invention, the wide screen receiver receiving both the TV signal of NTSC system and the computer signal of VGA mode, obviates an image distortion occurring when a picture of 4:3 is displayed on a screen of 16:9, by changing a sampling clock speed with a phase-locked loop system when sampling video data.
It will be apparent to those skilled in the art that various modifications and variations can be made in an aspect ratio control device of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4672443 *||Aug 30, 1985||Jun 9, 1987||Rca Corporation||Compatible wide screen television system with image compressor/expander|
|US4730215 *||May 30, 1986||Mar 8, 1988||Rca Corporation||Compatible wide screen television system with variable image compression/expansion|
|US5168362 *||Apr 26, 1991||Dec 1, 1992||Sony Corporation||Apparatus for displaying standard aspect ratio television signal on wide aspect ratio display screen|
|US5243421 *||Oct 7, 1991||Sep 7, 1993||Hitachi, Ltd.||Signal processor for a wide televison receiver|
|US5576771 *||Jun 13, 1994||Nov 19, 1996||Philips Electronics North America Corporation||Horizontal picture compression in widescreen television receivers|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6118486 *||Dec 31, 1997||Sep 12, 2000||Sarnoff Corporation||Synchronized multiple format video processing method and apparatus|
|US6268887 *||Dec 29, 1997||Jul 31, 2001||Hitachi, Ltd.||Image display apparatus and personal computer for displaying personal computer signals and broadcast signals|
|US6380982 *||Mar 18, 1998||Apr 30, 2002||Fujitsu Limited||Video signal processing circuit and computer system|
|US6433832||Jun 11, 2001||Aug 13, 2002||Hitachi, Ltd.||Image display apparatus and personal computer for displaying personal computer signals and broadcast signals|
|US6501510 *||Jun 28, 1999||Dec 31, 2002||Samsung Electronics, Co., Ltd.||Digital/analog broadcast signal processing unit|
|US6621523||Feb 21, 2002||Sep 16, 2003||Fujitsu Limited||Video signal processing circuit and computer system|
|US6816131 *||Jun 13, 2001||Nov 9, 2004||Sony Corporation||Single horizontal scan range CRT monitor|
|US6943782 *||Sep 28, 2001||Sep 13, 2005||Seiko Epson Corporation||Display control method, display controller, display unit and electronic device|
|US7003053 *||Nov 30, 2001||Feb 21, 2006||Sanyo Electric Co., Ltd.||Digital broadcast receiver|
|US7023485 *||Dec 28, 1999||Apr 4, 2006||Samsung Electronics Co., Ltd.||Apparatus and method for selectively converting clock frequency in digital signal receiver|
|US7137890 *||Feb 15, 2001||Nov 21, 2006||Namco Bandai Games Inc.||Modifying game image from wide to normal screen using moving or eye direction of character|
|US7502073 *||Apr 2, 2004||Mar 10, 2009||Panasonic Corporation||Signal processor|
|US7636125 *||Mar 11, 2003||Dec 22, 2009||Broadcom Corporation||Filter module for a video decoding system|
|US7724061 *||Oct 31, 2007||May 25, 2010||Raytheon Company||Active clamp circuit for electronic components|
|US8085346 *||Dec 27, 2011||Broadcom Corporation||Filter module for a video decoding system|
|US8619191 *||Dec 14, 2011||Dec 31, 2013||Broadcom Corporation||Filter module for a video decoding system|
|US20020047847 *||Sep 28, 2001||Apr 25, 2002||Tsuyoshi Tamura||Display control method, display controller, display unit and electronic device|
|US20020067776 *||Nov 30, 2001||Jun 6, 2002||Sanyo Electric Co., Ltd.||Digital broadcast receiver|
|US20030096647 *||Feb 15, 2001||May 22, 2003||Satoru Ouchi||Game machine, data storage medium, data transmission medium, and program|
|US20040075768 *||Mar 11, 2003||Apr 22, 2004||Patrick Law||Filter module for a video decoding system|
|US20040233997 *||Apr 2, 2004||Nov 25, 2004||Matsushita Electric Industrial Co., Ltd.||Signal processor|
|US20050041159 *||Jun 9, 2004||Feb 24, 2005||Nobuo Nakamura||Editing device and editing method|
|US20090110117 *||Oct 31, 2007||Apr 30, 2009||Won Chon||Active clamp circuit for electronic components|
|US20100066902 *||Mar 18, 2010||Patrick Law||Filter module for a video decoding system|
|USRE40327 *||Sep 16, 2005||May 20, 2008||Toshiro Obitsu||Video signal processing circuit and computer system|
|USRE42296 *||Apr 19, 2011||Dosa Advances Llc||Video signal processing circuit and computer system|
|U.S. Classification||348/445, 348/558, 348/556, 348/555, 348/E05.111|
|International Classification||H04N5/66, H04N5/46, H04N5/52, H04N7/01, H04N5/18, G09G5/00|
|Jul 3, 1997||AS||Assignment|
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HWANG, HO-DAE;REEL/FRAME:008624/0291
Effective date: 19970620
|Nov 6, 2002||REMI||Maintenance fee reminder mailed|
|Apr 21, 2003||LAPS||Lapse for failure to pay maintenance fees|
|Jun 17, 2003||FP||Expired due to failure to pay maintenance fee|
Effective date: 20030420