US5898815A - I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency - Google Patents
I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency Download PDFInfo
- Publication number
- US5898815A US5898815A US08/600,781 US60078196A US5898815A US 5898815 A US5898815 A US 5898815A US 60078196 A US60078196 A US 60078196A US 5898815 A US5898815 A US 5898815A
- Authority
- US
- United States
- Prior art keywords
- bus
- recovery
- cycle
- clock
- count
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
Definitions
- This invention is in the field of integrated circuits, and is more particularly directed to an I/O recovery counter and method for use thereof in a bus interface unit of a microprocessor.
- a typical X86 family of processors communicates with off-chip memory and peripheral units such as a hard disk, keyboard, etc. through memory or I/O bus cycles.
- a memory bus cycle is used to fetch instructions and data from the system's memory or to write data to the system's memory.
- the memory may be on the system board, in ROM or RAM.
- the processor executes a memory instruction in response to, inter alia, a "mov" or "str" instruction. To execute a memory cycle, the processor asserts an M/IO# pin to a "1" and generates an address on address pins A31 through A3.
- the I/O bus cycle is used to communicate with peripheral devices in the system such as a hard disk, keyboard, etc.
- An I/O cycle is initiated by the processor when it executes, inter alia, an IN instruction or an OUT instruction.
- the processor sets the M/IO# pin to a "0" and generates an address on the address pins A3-A15.
- Each peripheral which communicates with the processor via an I/O bus cycle is assigned a portion of the 64 Kbytes address space provided by the address pins.
- the peripheral devices sense the address and determine when the address corresponds to its assigned address.
- a system bus controller attached to the system bus returns a READY signal to the processor in response to the initiation of a bus cycle when the address is latched.
- the READY signal is used to create wait-states on the bus during an I/O bus cycle. For example, in the 8088 processor if the READY signal is held low until the rising edge of the next bus clock during an I/O bus cycle, a wait state is inserted. Thus, an I/O bus cycle of four clocks can be extended to five clocks. The READY signal can generate up to five wait states in any one I/O bus cycle. When the READY signal is again active, the I/O bus cycle ends.
- the bus cycle is normally four clocks in length or 1 microsecond for 4.77 MHz clock speed board designs, plus any additional wait states, for prior art systems.
- timing signals are derived from the same clock signal that the processor uses. At higher processor speeds, the clock signal is doubled or tripled to produce the processor speed. All external parameters however are defined with respect to the clock signal's rising edge
- processors are running at increasing speeds of 100 Mhz and more. At higher processor speeds, the system clock signal is doubled or tripled to produce the processor speed.
- This increasing speed of instructions by processors creates problems when executing I/O bus cycles. For example, a processor may execute an OUT instruction in a first clock and a second OUT instruction in the second clock.
- a peripheral is not able to respond to I/O write instructions in quick succession even when wait states are inserted in the bus cycle. Thus, when two OUT instructions specifying the same peripheral occur in quick succession, the peripheral may be unable to accept the data at the rate the data is transmitted. The peripheral is thus overrun because it can not accept the second I/O bus cycle.
- Peripheral overrun may result in loss of data or system slowdown because the data must be resent.
- This time from a first I/O write cycle to a second I/O write cycle for an I/O device to capture the data correctly is known as the I/O recovery time.
- a third solution suggested in the prior art has been to perform a "dummy" I/O read from an I/O location that will not be affected by the read operation.
- This dummy I/O read placed in between the back to back I/O write cycles guarantees at least two processor clock cycles of delay between the two I/O write cycles.
- This dummy I/O read however still requires an interruption in the order of processor instructions.
- all three prior art suggestions fail if the I/O recovery period required is longer than the time necessary to perform the inserted instruction. Thus, for instance, if the I/O recovery time is longer than the period to perform the "dummy" I/O read, than peripheral overrun may still occur.
- the present invention comprises an I/O recovery counter with a processor clock signal input and a count signal input indicating an initiation of an I/O bus cycle on a system bus.
- a counter counts to an I/O recovery count number corresponding to the minimum number of processor clocks needed for an adequate I/O recovery period.
- the I/O recovery counter completes the count of the I/O recovery count number, it outputs a complete signal.
- the bus interface unit of the processor waits to initiate a subsequent I/O cycle until the I/O recovery counter outputs the complete signal.
- FIG. 1 illustrates an electrical schematic, in block form, of an exemplary microprocessor incorporating the preferred embodiment of the invention.
- FIG. 2 illustrates an electrical diagram, in block form, of the system in which the microprocessor of FIG. 1 may be incorporated.
- FIG. 3 illustrates in an electrical diagram, in block form, of the bus interface unit of a microprocessor in which the present invention operates and the system bus controller.
- FIG. 4 illustrates a timing diagram of an exemplary I/O write bus cycle performed in the present invention.
- FIG. 5 illustrates a flow chart depicting the steps performed by the present invention.
- FIG. 6 illustrates an electrical circuit, in block diagram form, of the preferred embodiment of the present invention.
- FIG. 1 illustrates an exemplary superpipelined processor 10, into which the preferred embodiment of the present invention may be implemented.
- the present invention may be applicable to other processors of differing architectures, that may benefit from the increased efficiency of I/O access cycles and other advantages of the present invention.
- the processor uses a modular architecture in which an arbitrated C-bus interconnects a prefetch unit 12, an execution core 14, (L1) level one cache 16, bus controller 18, and floating point unit (FPU) 20.
- Instruction fetch is performed by a prefetch unit 12, which fetches instruction bytes into a multi-block prefetch buffer 22.
- a branch unit 24 supplies prefetch addresses to the prefetch unit 12 for branches stored in a branch target cache (BTC) 26.
- BTC 26 is accessed with the instruction pointer for the instruction prior to a branch.
- An execution core 14 includes the ID, AC1/AC2, EX, and WB pipeline stages.
- a pipe control unit 28 controls the flow of instructions through the pipe stages of the execution core 14. Floating point instructions are executed in a floating point unit (FPU) 20.
- FPU floating point unit
- a decode unit 30 decodes one x86 instruction per clock. Decoded instructions are dispatched to an AC unit 33, which is superpipelined into AC1 and AC2 pipe stages.
- the AC unit 33 generates memory reference addresses for loading operands from memory (accessing the cache) or I/O units and storing execution results to memory (posting to a load/store unit).
- the AC1 stage calculates one linear address per clock (address calculations involving three components require an additional clock).
- the AC2 stage performs limit checking and, if paging is enabled, linear-to-physical address translation through a translation lookaside buffer (TLB) 34.
- TLB translation lookaside buffer
- Integer instructions are issued to the EX unit 36 for execution.
- EX unit 36 receives source operands (a) as immediate data passed along with the instruction from the AC unit 33, (b) from the register file, and/or for memory references, and (c) from a load/store unit 38. Execution results are written back in the WB stage either to the register file or to the cache (memory) through load store reservation stations in the load store unit 38.
- the load/store unit 38 performs load/store operations for the prefetch unit 12 and the execution core 14.
- Eight reservation station buffers are used for posting stores--stores can be posted conditionally pending resolution of a branch, retiring only if the branch resolves correctly.
- Stores are queued in program order--data loads from the AC2 stage may bypass pending stores, and will source out of the reservation stations in the case of a load/store address match.
- the L1 cache 16 is a 16 K byte unified data/instruction cache, organized as 4 way set associative with 256 lines per set and 16 bytes (4 dwords) per cache line.
- the L1 cache 16 can be operated in either write-through or write-back mode--to support a write-back coherency protocol, each cache line includes 4 dirty bits (one per dword).
- a bus interface unit (BIU) 40 interfaces to external 32 bit address and data buses (such as the 486-type bus), and to an external control bus. Alternatively, the BIU 40 can be modified to interface to an external 64-bit data bus (such as the Pentium-type bus).
- the BIU 40 interfaces to two internal buses, a C-bus and an X-bus, through the bus controller 18.
- the BIU 40 includes a buffer for storing subsequent I/O bus access cycles, as described in more detail hereinbelow.
- the BIU 40 receives address and control signals over the C-bus defining the address and control information for a bus cycle from the execution core 14.
- the C-bus is an arbitrated bus that interconnects the prefetch unit 12, execution core 14, load/store unit 38, L1 cache 16, BIU 40, and the FPU 20.
- C-bus control is in the BIU 40.
- the C-bus includes a 32 bit address bus C -- ADDR, two 32-bit data buses C -- DATA and C -- DDATA, and a 128-bit (16 byte cache line) dedicated instruction bus.
- C -- DATA and C -- DDATA can be controlled to provide for 64 bit transfers to the FPU 20, and to support interfacing the L1 cache 16 to a 64-bit external data bus.
- the C -- DATA bus is used for data transfers between the BIU 40 and the L1 cache 16
- the C -- DDATA bus is used for transfers between the load/store unit and the L1 cache 16.
- instruction data is provided over the C -- DATA bus to the prefetch unit 12 at the same time it is provided to the L1 cache 16.
- the X-bus is an extension of the external bus interface that allows peripheral devices to be integrated on chip.
- the timing operation of processor 10, is under the control of clock generator system 42, which generates internal clock signals for use throughout processor 10.
- these internal clock signals include bus clock signal BCLCK which is forwarded to BIU 40, and processor clock signal PCLCK which is forwarded to execution core 14.
- the clock generator system 42 is connected to an external clock terminal CLK, from which it receives either a periodic clock signal (e.g., from a crystal oscillator) or a logic level transition.
- a clock multiplier input CLKMUL is also connected to the clock generator system 42. CLKMUL is sampled during a reset of the processor, such as at power-up, to determine the execution core 14 operating frequency. If CLKMUL is zero or is left unconnected, the execution core 14 frequency is two times the frequency of the CLK input. If CLKMUL is a logical 1, then the execution core frequency is three times the frequency of CLK.
- FIG. 2 illustrates an exemplary system 44 in which processor 10 may reside.
- the system 44 includes system bus controller 46.
- System bus controller 46 is connected to processor 10 through local processor bus 48, which comprises the external address pins, control signals, and data pins of FIG. 1.
- the system bus controller 46 provides the interface between the processor and the external memory subsystem--level two cache 50 and main memory 52.
- System bus controller 46 also provides control for the interfaces to the external system bus 54.
- External system bus 54 is preferably based on the Industry Standard Architecture (ISA), a bus architecture introduced in the International Business Machines (IBM) PC/AT personal computer.
- ISA Industry Standard Architecture
- the external system bus 54 interfaces to I/O chip 56, keyboard controller 58, basic input/output system (BIOS) 60, and ISA slots 62.
- Controller 46 may in addition provide control for a VL bus interface, not shown in FIG. 2.
- FIG. 3 illustrates a block schematic diagram of the BIU 40 and the system bus controller 46, in more detail.
- the BIU 40 is connected to the execution core 14 by a 32 bit data line C -- DATA 64, 32 bit address line C -- ADDR 66 and control lines C -- DDATA 68, also shown in FIG. 1.
- the BIU 40 comprises an I/O cycle buffer 70 and an I/O recovery counter 72, and a control register IORT 74 of the present invention.
- the BIU 40 is connected to the system bus controller 46 over local processor bus 48 which includes a 32 bit data line 76, a 32 bit address line 78, and control lines 80.
- the execution core 14 communicates bus cycle control information to BIU 40, including whether a bus cycle is an I/O cycle or memory cycle, over control lines C -- DDATA 68.
- the execution core 14 communicates the address and data for the cycle over address line C -- ADDR66 and data line C -- DATA 64, respectively.
- the BIU 40 asserts the M/IO# pin on the processor to a logical 0 and asserts address pins A3-A15.
- the system bus controller 46 returns a READY signal over control lines 80 when the address is latched by the peripheral.
- the I/O recovery counter 72 begins to count. Data is then written to or read from the I/O device depending on whether the I/O bus cycle is a read or a write cycle.
- the bus timing signals for a typical I/O write bus cycle are shown in FIG. 4.
- the clock signal BCLCK is the system or bus clock.
- the BCLCK signal is the timing reference used by the BIU 40.
- the BIU 40 defines all external timing parameters with respect to the BCLCK rising edge.
- the processor activates the bus definition signals, i.e. the M/IO# and W/R# signals, of the I/O bus cycle.
- the M/IO# is a bus definition signal indicating whether the bus cycle is an I/O cycle or a memory cycle. When high, M/IO# indicates that the current bus cycle is a memory cycle, and when low, indicates that the current bus cycle is an I/O cycle. When high, the W/R# signal indicates that the current memory or I/O bus cycle is a write cycle, or if low, indicates that the current bus cycle is a read cycle.
- the processor indicates that the current bus cycle is an I/O write cycle. Also during period T1, the processor asserts the ADS# bus interface signal indicating that a valid port address is on the address bus and asserts the I/O address on address pins A3 through A15. The system bus controller then asserts a READY signal to the processor to indicate that the bus is ready for a bus cycle.
- the processor drives the data onto data lines D31 through D0 (or if an 64 bit data bus, on data lines D63 through D0).
- the system bus controller 46 deactivates the READY signal and thereby generates wait state TW which provides an additional clock period for transmission of data.
- the system bus controller 46 activates the READY signal during period TW indicating that no more wait states are needed.
- the bus cycle ends during period T3. Though in this example only one wait state was generated, the system bus controller may insert up to four wait states in this manner by asserting the READY signal to a low.
- the present invention may perform pipelined bus cycles. Under a pipelined bus cycle, the processor allows up to two outstanding bus cycles at any given time. The address of the first bus cycle is driven on the bus and while the processor waits for the data for the first cycle, the address for a second bus cycle is issued.
- the peripheral may not be able to accept a second I/O bus cycle without loss of data or overrun, despite a number of inserted wait states.
- the BIU 40 waits until I/O recovery counter 72 completes its count prior to initiating another I/O bus cycle.
- the BIU 40 may initiate memory bus cycles during the count by the I/O recovery counter 72.
- the I/O recovery counter 72 is programmed with an I/O recovery count number.
- the I/O recovery count number depends on the ratio of the processor clock speed to the bus clock speed clock and the minimum number of processor clocks between I/O cycles without causing peripheral overrun.
- the I/O recovery count number corresponds to the I/O recovery period necessary for the system peripherals.
- the I/O recovery count number in the preferred embodiment equals the number of bus clocks BCLKs needed to access I/O peripherals without overrun times the ratio of processor clock PCLCK frequency to bus clock BCLCK frequency.
- the I/O recovery counter 72 can be programmed with the I/O recovery count number by the BIOS 60 during power-up of the system.
- the BIOS 60 samples the Clock Multiplier CLKMUL input of the processor to determine the processor's core operating frequency. If CLKMUL equals 0, the processor clock PCLCK frequency is 2 times the frequency of the bus clock BCLCK. If CLKMUL equals 1, the processor clock PCLCK is 3 times the frequency of bus clock BCLCK.
- the BIOS can then write the specified minimum number of clocks between I/O accesses to the I/O recovery counter based on the contents of a control register IORT 74 in BIU 40.
- control register IORT 74 specifies the minimum number of bus clocks BCLCKs between I/O bus accesses.
- control register IORT comprises 8 bits, with bits 0-2 specifying the minimum number of bus clocks between I/O access.
- Table 1 illustrates the content of register IORT 74 and the corresponding clock delay in the preferred embodiment.
- the register content is thus 0 in hexadecimal for a bus clock delay of 1, 1 in hexadecimal for a bus clock delay of 2, 2 in hexadecimal for a bus clock delay of 4, etc.
- the BIOS multiplies this clock delay by the ratio of processor PCLCK to bus BCLCK clock speed from sampling CLKMUL to obtain the I/O recovery count number.
- the BIU 40 After the I/O recovery counter 72 is programmed in block 82, the BIU 40 detects whether an external bus access is needed by the processor 10, as depicted in block 84. If no access is needed, the process returns and continues to wait for a bus access. If a bus access is needed, the BIU 40 determines if the bus access is a memory access or an I/O access in block 86. The execution core 14 communicates to BIU 40 when a bus access is a memory or I/O access (When IN or OUT instruction occurs, the bus access is an I/O access). If the bus access is a memory access, the BIU 40 executes the memory bus cycle, as depicted in Block 88.
- the BIU 40 determines if the I/O recovery counter 72 is zero in step 90. If the counter is zero, then the BIU 40 sets the I/O recovery counter 72 to the I/O recovery count number, as depicted in Block 92. In Block 94, the BIU 40 executes the I/O bus cycle by asserting the M/IO# pin to a logical 0 and asserting the address on address pins A3-A15. When the system bus controller 46 returns a READY signal, the I/O recovery counter 72 begins to count, as depicted in block 96.
- the I/O recovery counter 72 decrements from the I/O recovery count number at each processor clock PCLCK until the I/O recovery counter 72 reaches zero.
- the I/O recovery counter 72 may also increment from 0 to the I/O recovery count number at each processor clock PCLCK and still obtain the same advantages of the present invention.
- the process control returns to block 84 and the BIU 40 monitors for another bus access. If a bus access is needed, and in block 86 the BIU 40 determines the bus access is a memory access, the BIU 40 can execute the memory bus cycle even if the I/O recovery counter 72 has not completed its count. Thus, the memory bus cycles in the present invention can continue without interruption after an I/O bus cycle until the next I/O bus cycle is received, as described below.
- next bus cycle is an I/O cycle and the I/O recovery counter 72 has reached zero in decision block 90, the BIU 40 resets the I/O recovery counter 72 to the I/O recovery count number and executes the I/O bus cycle. No problem of overrun exists because the I/O recovery counter 72 has completed the count from the previously sent I/O access indicating that the minimum time has elapsed to safely send the next I/O bus cycle.
- the BIU 40 buffers the I/O access cycle in I/O buffer 70, as depicted in block 98. All bus access are stalled at this point, as shown in block 100, because the BIU 40 may not buffer more than one I/O bus cycle.
- the execution core 14 is signaled to execute no more access cycles until the I/O recovery counter 72 reaches zero and the buffered I/O access is executed.
- the present invention prevents possible loss of data because of peripheral overrun which may occur when I/O accesses are made to the same peripheral in too short a time.
- the BIU 40 stalls the access cycles whether or not the I/O bus cycle is to the same peripheral even though I/O access to different peripherals does not present the same problem of overrun as I/O access to the same peripheral.
- a comparator circuit which buffers the last I/O access address and compares the buffered address to the next I/O access.
- the BIU 40 could then execute the next I/O access prior to the I/O recovery counter 72 reaching zero if the I/O access is not addressed to the same peripheral.
- the preferred embodiment of the present invention does not include this step because of the increased complexity and cost of the hardware.
- the present invention stalls a subsequent I/O access if the I/O recovery counter is not a logical zero regardless as to whether the subsequent I/O access reads or writes to the peripheral, even though back to back reads to the same peripheral does not present the same problem of overrun as back to back writes to the same peripheral.
- this step may be added by buffering the control signal from the execution core 14 indicating that the I/O bus cycle is a read or write and comparing the buffered signal to subsequent I/O bus cycles.
- the BIU 40 may then execute a subsequent I/O cycle, if the subsequent I/O cycle is a read and the previous I/O cycle was a read. Again, the preferred embodiment of the present invention does not include this step because of the increased complexity and cost of the hardware.
- FIG. 6 illustrates an electrical circuit, in block diagram form, of the I/O recovery counter 72.
- the I/O recovery counter 72 includes an AND gate 102 with inputs of the processor clock PCLCK and a COUNT signal derived from the READY signal sent by the system bus controller 46.
- the AND gate 102 has an output connected to an 8 bit programmable counter 104.
- the 8 bit programmable counter 104 comprises a reset pin which resets its count.
- the programmable counter 104 also has an output 106.
- the BIOS 60 programs the programmable counter 104 with the I/O recovery count number.
- the BIU 40 resets the programmable counter 104 by asserting the RESET pin of the counter 96 at the beginning of an I/O bus cycle.
- the programmable counter 104 then increments when it receives a logical high signal from the AND gate 102.
- the COUNT signal input into the AND gate 102 is generated by the BIU 40. Once the BIU 40 receives a READY signal from the system bus controller during the I/O bus cycle, the BIU 40 asserts the COUNT signal to a logical high. The COUNT signal remains a logical high, even if the READY signal is held low later in the bus cycle (i.e. a wait state is generated).
- the AND gate 102 thus outputs a logical high at each processor clock PCLCK after the system bus controller returns a READY signal from the I/O bus cycle.
- the output 106 of the programmable counter 104 Prior to completing the count of the I/O recovery count number, the output 106 of the programmable counter 104 outputs a not complete signal equal to a logical low. When the programmable counter 104 completes the count of the I/O recovery count number, the outputs 106 outputs a complete signal equal to a logical high. This complete signal indicates to the BIU 40 that another I/O bus
- the clock input to the AND gate 102 may be the bus clock BCLCK rather than the processor clock PCLCK.
- the I/O recovery count, or I/O recovery period would just equal the minimum number of bus clocks necessary to prevent I/O overrun. The operation of the I/O recovery counter would otherwise be the same.
- Table 2 illustrates an example of the operation of the present invention for several bus cycles.
- the processor clock PCLCK frequency is twice the bus clock BCLCK frequency.
- the bus clock frequency is 50 Mhz
- the processor clock frequency is 100 Mhz.
- the minimum number of bus clocks BCLCKs between I/O access to prevent overrun equals 8 bus clocks.
- the register IORT 74 then will be defined as 3h, as seen from Table 1.
- the I/O recovery count number equals 16 counts (the minimum number of bus clocks times the multiplier of processor to bus speed ratio).
- the BIU 40 executes an I/O access.
- the I/O recovery counter 72 is reset and begins to decrement at the return of the READY signal from the system bus controller.
- the bus clock BCLCK is zero and the processor clock PCLCK is zero.
- the BIU 40 executes a memory bus cycle and again at time 2, the BIU 40 executes a second memory bus cycle.
- the processor executes an IN or OUT instruction and signals the BIU 40 to execute an I/O access.
- the I/O recovery counter 72 does not read zero and the output 106 is a non-complete signal.
- the BIU 40 then buffers the I/O access and stalls any subsequent bus cycles, memory or I/O. Thus no bus cycles are executed at time 3 or time 4.
- the I/O recovery counter reads zero and output 106 is a complete signal.
- the BIU 40 thus removes the stall of the bus cycles.
- the BIU 40 executes the buffered I/O bus cycle and resets the I/O recovery counter 72 to the I/O recovery count number equal to 16.
- the BIU 40 continues to execute bus cycles.
- the BIU 40 thus performs two memory bus cycles between successive I/O bus cycles without disturbing the order of instruction flow in the processor and without causing peripheral overrun.
Abstract
Description
TABLE 1 ______________________________________ CONTROL REGISTER IORT DEFINITION REGISTER CONTENT BUS CLOCKDELAY ______________________________________ 0h 1 1h 2 2h 43h 8 4h 16 5h 32 6h 64 7h no delay ______________________________________
TABLE 2 ______________________________________ ILLUSTRATION OF THE OPERATION OF THE I/O RECOVERY COUNTER FOR SEVERAL BUS CYCLES Processor Type of Bus I/O recovery Bus Clock Clock (2 × Bus Time Cycle counter Counts BCLCK Clock) ______________________________________ 0 I/O 0 0 0 1Memory 16 2 4 2Memory 12 4 8 3 I/O (Stall) 8 6 12 4 (Stall) 4 8 16 5 I/O 0 10 20 6Memory 16 12 24 ______________________________________
Claims (15)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/600,781 US5898815A (en) | 1996-02-13 | 1996-02-13 | I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/600,781 US5898815A (en) | 1996-02-13 | 1996-02-13 | I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency |
Publications (1)
Publication Number | Publication Date |
---|---|
US5898815A true US5898815A (en) | 1999-04-27 |
Family
ID=24405010
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/600,781 Expired - Lifetime US5898815A (en) | 1996-02-13 | 1996-02-13 | I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency |
Country Status (1)
Country | Link |
---|---|
US (1) | US5898815A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6216217B1 (en) * | 1997-02-27 | 2001-04-10 | Mitsubishi Denki Kabushiki Kaisha | Data processor |
US20050060454A1 (en) * | 2003-08-21 | 2005-03-17 | International Business Machines Corporation | I/O throughput by pre-termination arbitration |
US20070121496A1 (en) * | 2005-11-30 | 2007-05-31 | Sinykin Joshua P | System and method for amplitude optimization in high-speed serial transmissions |
US7937447B1 (en) * | 2004-07-22 | 2011-05-03 | Xsigo Systems | Communication between computer systems over an input/output (I/O) bus |
EP2555121A1 (en) * | 2011-08-05 | 2013-02-06 | Fujitsu Limited | Communication control device, information processing apparatus, and path selecting method |
US9083550B2 (en) | 2012-10-29 | 2015-07-14 | Oracle International Corporation | Network virtualization over infiniband |
US9331963B2 (en) | 2010-09-24 | 2016-05-03 | Oracle International Corporation | Wireless host I/O using virtualized I/O controllers |
US9813283B2 (en) | 2005-08-09 | 2017-11-07 | Oracle International Corporation | Efficient data transfer between servers and remote peripherals |
US9973446B2 (en) | 2009-08-20 | 2018-05-15 | Oracle International Corporation | Remote shared server peripherals over an Ethernet network for resource virtualization |
US20230040310A1 (en) * | 2021-08-03 | 2023-02-09 | Apple Inc. | Cpu cluster shared resource management |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3700821A (en) * | 1970-11-09 | 1972-10-24 | Bell Telephone Labor Inc | Digital constant-percent-break pulse correcting signal timer |
US4064395A (en) * | 1976-08-17 | 1977-12-20 | Cincinnati Milacron Inc. | Machine control system employing a programmable machine function controller |
US4694196A (en) * | 1984-12-07 | 1987-09-15 | American Telephone And Telegraph Company And At&T Information Systems | Clock recovery circuit |
US4703481A (en) * | 1985-08-16 | 1987-10-27 | Hewlett-Packard Company | Method and apparatus for fault recovery within a computing system |
US4740969A (en) * | 1986-06-27 | 1988-04-26 | Hewlett-Packard Company | Method and apparatus for recovering from hardware faults |
US5065313A (en) * | 1989-03-30 | 1991-11-12 | Dell Usa Corporation | Digital computer system having circuit for regulation of I/O command recovery time |
US5095450A (en) * | 1989-05-05 | 1992-03-10 | Oce Graphics Usa Inc. | Graphic plotting network methods and apparatus |
US5195110A (en) * | 1991-04-01 | 1993-03-16 | Nec America, Inc. | Clock recovery and decoder circuit for a CMI-encoded signal |
US5384563A (en) * | 1993-02-22 | 1995-01-24 | Honeywell Inc. | Method and apparatus for time synchronization of bus type local area networks including hierarchical networks |
US5448699A (en) * | 1990-12-21 | 1995-09-05 | Compaq Computer Corp. | Apparatus with leading edge delay circuit for selectively sending a delayed substitute version of a signal transmitted between an expansion card and a system bus |
US5473651A (en) * | 1994-12-28 | 1995-12-05 | At&T Corp. | Method and apparatus for testing large embedded counters |
US5603041A (en) * | 1994-12-13 | 1997-02-11 | International Business Machines Corporation | Method and system for reading from a m-byte memory utilizing a processor having a n-byte data bus |
US5634139A (en) * | 1994-04-26 | 1997-05-27 | Nec Corporation | Microprocessor using feedback memory address to internally generate bust mode transfer period signal for controlling burst mode data transfer to external memory |
-
1996
- 1996-02-13 US US08/600,781 patent/US5898815A/en not_active Expired - Lifetime
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3700821A (en) * | 1970-11-09 | 1972-10-24 | Bell Telephone Labor Inc | Digital constant-percent-break pulse correcting signal timer |
US4064395A (en) * | 1976-08-17 | 1977-12-20 | Cincinnati Milacron Inc. | Machine control system employing a programmable machine function controller |
US4694196A (en) * | 1984-12-07 | 1987-09-15 | American Telephone And Telegraph Company And At&T Information Systems | Clock recovery circuit |
US4703481A (en) * | 1985-08-16 | 1987-10-27 | Hewlett-Packard Company | Method and apparatus for fault recovery within a computing system |
US4740969A (en) * | 1986-06-27 | 1988-04-26 | Hewlett-Packard Company | Method and apparatus for recovering from hardware faults |
US5065313A (en) * | 1989-03-30 | 1991-11-12 | Dell Usa Corporation | Digital computer system having circuit for regulation of I/O command recovery time |
US5095450A (en) * | 1989-05-05 | 1992-03-10 | Oce Graphics Usa Inc. | Graphic plotting network methods and apparatus |
US5448699A (en) * | 1990-12-21 | 1995-09-05 | Compaq Computer Corp. | Apparatus with leading edge delay circuit for selectively sending a delayed substitute version of a signal transmitted between an expansion card and a system bus |
US5195110A (en) * | 1991-04-01 | 1993-03-16 | Nec America, Inc. | Clock recovery and decoder circuit for a CMI-encoded signal |
US5384563A (en) * | 1993-02-22 | 1995-01-24 | Honeywell Inc. | Method and apparatus for time synchronization of bus type local area networks including hierarchical networks |
US5634139A (en) * | 1994-04-26 | 1997-05-27 | Nec Corporation | Microprocessor using feedback memory address to internally generate bust mode transfer period signal for controlling burst mode data transfer to external memory |
US5603041A (en) * | 1994-12-13 | 1997-02-11 | International Business Machines Corporation | Method and system for reading from a m-byte memory utilizing a processor having a n-byte data bus |
US5473651A (en) * | 1994-12-28 | 1995-12-05 | At&T Corp. | Method and apparatus for testing large embedded counters |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6216217B1 (en) * | 1997-02-27 | 2001-04-10 | Mitsubishi Denki Kabushiki Kaisha | Data processor |
US20050060454A1 (en) * | 2003-08-21 | 2005-03-17 | International Business Machines Corporation | I/O throughput by pre-termination arbitration |
US7085865B2 (en) * | 2003-08-21 | 2006-08-01 | International Business Machines Corporation | I/O throughput by pre-termination arbitration |
US9264384B1 (en) | 2004-07-22 | 2016-02-16 | Oracle International Corporation | Resource virtualization mechanism including virtual host bus adapters |
US7937447B1 (en) * | 2004-07-22 | 2011-05-03 | Xsigo Systems | Communication between computer systems over an input/output (I/O) bus |
US8677023B2 (en) | 2004-07-22 | 2014-03-18 | Oracle International Corporation | High availability and I/O aggregation for server environments |
US9813283B2 (en) | 2005-08-09 | 2017-11-07 | Oracle International Corporation | Efficient data transfer between servers and remote peripherals |
US20070121496A1 (en) * | 2005-11-30 | 2007-05-31 | Sinykin Joshua P | System and method for amplitude optimization in high-speed serial transmissions |
US9973446B2 (en) | 2009-08-20 | 2018-05-15 | Oracle International Corporation | Remote shared server peripherals over an Ethernet network for resource virtualization |
US10880235B2 (en) | 2009-08-20 | 2020-12-29 | Oracle International Corporation | Remote shared server peripherals over an ethernet network for resource virtualization |
US9331963B2 (en) | 2010-09-24 | 2016-05-03 | Oracle International Corporation | Wireless host I/O using virtualized I/O controllers |
EP2555121A1 (en) * | 2011-08-05 | 2013-02-06 | Fujitsu Limited | Communication control device, information processing apparatus, and path selecting method |
US8914560B2 (en) | 2011-08-05 | 2014-12-16 | Fujitsu Limited | Communication control device for selecting a path under different loads—high, middle, or low loads—based on whether a prohibition period has passed |
US9083550B2 (en) | 2012-10-29 | 2015-07-14 | Oracle International Corporation | Network virtualization over infiniband |
US20230040310A1 (en) * | 2021-08-03 | 2023-02-09 | Apple Inc. | Cpu cluster shared resource management |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5027270A (en) | Processor controlled interface with instruction streaming | |
US4802085A (en) | Apparatus and method for detecting and handling memory-mapped I/O by a pipelined microprocessor | |
US5983325A (en) | Dataless touch to open a memory page | |
US6134634A (en) | Method and apparatus for preemptive cache write-back | |
US6088789A (en) | Prefetch instruction specifying destination functional unit and read/write access mode | |
US5860107A (en) | Processor and method for store gathering through merged store operations | |
US5926053A (en) | Selectable clock generation mode | |
US5815693A (en) | Processor having a frequency modulated core clock based on the criticality of program activity | |
US5293592A (en) | Decoder for pipelined system having portion indicating type of address generation and other portion controlling address generation within pipeline | |
US6009516A (en) | Pipelined microprocessor with efficient self-modifying code detection and handling | |
US5509137A (en) | Store processing method in a pipelined cache memory | |
US5446850A (en) | Cross-cache-line compounding algorithm for scism processors | |
US5469544A (en) | Central processing unit address pipelining | |
US5263153A (en) | Monitoring control flow in a microprocessor | |
KR20070001900A (en) | Transitioning from instruction cache to trace cache on label boundaries | |
US5590368A (en) | Method and apparatus for dynamically expanding the pipeline of a microprocessor | |
US6760835B1 (en) | Instruction branch mispredict streaming | |
US5740410A (en) | Static clock generator | |
US5860105A (en) | NDIRTY cache line lookahead | |
US5898815A (en) | I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency | |
KR950010825B1 (en) | Microprocessor incorporating branch target instruction buffer | |
EP0772822A1 (en) | Microprocessor with pipelined access request to external memory | |
US20040186982A9 (en) | Stalling Instructions in a pipelined microprocessor | |
US5596731A (en) | Single clock bus transfers during burst and non-burst cycles | |
US5924120A (en) | Method and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction times |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: CYRIX CORPORATION, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BLUHM, MARK W.;MARTIN, MARVIN W.;REEL/FRAME:007883/0169 Effective date: 19960212 |
|
AS | Assignment |
Owner name: NATIONAL SEMICONDUCTOR CORP, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CYRIX CORPORATION;REEL/FRAME:009089/0068 Effective date: 19980309 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: VIA-CYRIX, INC, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NATIONAL SEMICONDUCTOR CORPORATION;REEL/FRAME:010321/0448 Effective date: 19990908 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |