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Publication numberUS5903777 A
Publication typeGrant
Application numberUS 08/942,774
Publication dateMay 11, 1999
Filing dateOct 2, 1997
Priority dateOct 2, 1997
Fee statusPaid
Also published asDE19845248A1, DE19845248B4
Publication number08942774, 942774, US 5903777 A, US 5903777A, US-A-5903777, US5903777 A, US5903777A
InventorsDavid Brief
Original AssigneeNational Semiconductor Corp.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Increasing the availability of the universal serial bus interconnects
US 5903777 A
Abstract
A Universal Serial Bus hub circuit includes an upstream port and a plurality of downstream ports. The hub circuit further includes input circuitry via which data received on one of the downstream ports is to be repeated to the upstream port. Asynchronous event detection circuitry is to detect an asynchronous event in the received data for the one downstream port. Port selection circuitry to select the one downstream port. Timer circuitry is to measure a time period from a time that the asynchronous event detection circuitry detects an asynchronous event. Synchronous event detection circuitry is to detect a synchronous event in the received data for the one port. End-of-event generation circuitry generates a simulated end-of-event signal if the detected synchronous event is not before the end of the measured time period, and provides the simulated end-of-event signal to the upstream port.
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Claims(11)
What is claimed is:
1. A Universal Serial Bus hub circuit, comprising:
an upstream port and a plurality of downstream ports;
input circuitry via which data received on one of the downstream ports is to be repeated to the upstream port;
asynchronous event detection circuitry to detect an asynchronous event in the received data for the one downstream port;
port selection circuitry to select the one downstream port;
timer circuitry to measure a time period from a time that the asynchronous event detection circuitry detects an asynchronous event;
synchronous event detection circuitry to detect a synchronous event in the received data for the one port;
end-of-event generation circuitry to generate a simulated end-of-event signal if the detected synchronous event is not before the end of the measured time period, and to provide the simulated end-of-event signal to the upstream port.
2. The hub circuit of claim 1, and further comprising:
hub clearing circuitry to clear the selection, wherein the hub clearing circuitry clears the selection if the synchronous event is not detected before the predetermined time period ends.
3. The hub circuit of claim 1, wherein
the port selection circuitry indicates the selection by asserting a selection signal, and
the timer circuitry is a counter circuit, wherein a counting operation of the counting circuit is initialized by the selection signal being asserted.
4. The hub circuit of claim 3, wherein the counter circuit is reset in response to the detection of the synchronous event.
5. The hub circuit of claim 4, wherein the end-of-event generation circuitry provides the end-of-event signal to the upstream port in response to the counter circuit reaching a predetermined count value.
6. The hub circuit of claim 3, wherein
the input circuitry samples data responsive to state changes of the sampling clock; and
the counter circuit counts responsive to the state changes of the sampling clock.
7. A method of performing Universal Serial Bus transfer in a Universal Serial Bus hub that comprises:
receiving data on one of a plurality of downstream ports of the USB hub to be repeated to the upstream port;
detecting an asynchronous event in the received data for the one downstream port;
selecting the one downstream port;
measuring a time period from a time that the asynchronous event is detected;
detecting a synchronous event in the received data for the one downstream port;
generating a simulated end-of-event signal if the detected synchronous event is not before the end of the measured time period and providing the simulated end-of-event signal to the upstream port.
8. The method of claim 7, and further comprising:
clearing the selection if the synchronous event is not detected before the predetermined time period ends.
9. The method of claim 7, wherein
the selecting step indicates asserting a selection signal, and
the timing step includes a counting step, wherein a counting operation of the counting step is initialized by the selection signal being asserted.
10. The method of claim 9, wherein the counting operation is reset in response to the detection of the synchronous event.
11. The method of claim 10, wherein the end-of-event signal is provided to the upstream port in response to the counter operation reaching a predetermined count value.
Description
TECHNICAL FIELD

This application relates to Universal Serial Bus interconnects and, in particular, to such interconnect circuitry that increases the availability of the interconnect more quickly by automatically freeing up the interconnect after a noise event.

BACKGROUND

Universal Serial Bus is a standard peripheral interface for attaching personal computers to a wide variety of devices: e.g. digital telephone lines, monitors, modems, mice, printers, scanners, game controllers, keyboards and other peripherals. USB thus replaces existing interfaces such as the RS-232C serial ports, parallel ports, PS/2 interface and game/MIDI ports.

In accordance with USB, all attached devices connect to a personal computer through a single connector type using a tiered-star topology. A host controller of the USB interfaces with the host processor inside the personal computer. A USB system has only one host controller, which controls all accesses to USB resources and monitors the bus's topology. A USB hub provides USB attachment points for USB devices. A USB hub is shown in FIG. 1. The host controller includes a root hub, but a USB system can include other hubs that provide easy plug-in points for peripheral devices.

In particular, the USB hub is responsible for transferring data both upstream and downstream. All data transfers occur between the host (i.e., the personal computer) and the individual peripheral devices. The host is always at the root of the tree, and the devices are on leaves of the tree. A hub resides at each intersection. As shown in FIG. 2A, when the host transfers data to a device, data is transferred downstream through all hubs, from an upstream port (shown as Port 0 in FIG. 2A) to all non-disabled downstream ports (shown as Port 1 in FIG. 1) to all other hubs and devices. On the other hand, as shown in FIG. 2B, when data is transferred from a device to the host, the transfer occurs upstream only on the direct path to the host. A device is only allowed to transmit data only upon receipt of a special data packet, called a token. Devices may also be implemented to include hub functionality.

During a data transfer (from either the upstream port or a downstream port), the hub locks out all other data transmissions on any other port of the hub. Furthermore, conventionally, the hub has no inherent token detection capability. Thus, the hub essentially trusts that a packet received is valid, and the packet is directed upstream if detected on a downstream port, or downstream if detected on the upstream port. The detection of a packet by the hub must occur very quickly so that the hub can determine the data direction. According to the USB standard, data must be repeated by a hub from an input port to an output port in less than 40 ns. Thus, direction detection of a packet must occur as soon as possible upon detection of the first non-idle symbol of the packet. Only after the transfer direction is determined can the data packet be interrogated for validity. If the data packet is valid, the packet is transferred until an End-of-Packet symbol is detected, at which time the connection is torn down and detection of the next data packet is anticipated.

But, because the hub has no inherent token detection capabilities, a noise event occurring on one of the downstream ports cannot be distinguished from the beginning of a bona fide upstream data transfer, and any subsequent upstream data transfer from the downstream port will be blocked by the hub in response to the noise event. In addition, upstream data transfers on all upstream hubs will also be blocked. This "block" condition will persist until the end of the current (1 ms) frame period, at which time the currently selected port will be disabled, and transfers to and from any device in the downstream branch of this hub port will be disabled until management software intervenes to re-enables the entire connection.

SUMMARY

A Universal Serial Bus hub circuit includes an upstream port and a plurality of downstream ports. The hub circuit further includes input circuitry via which data received on one of the downstream ports is to be repeated to the upstream port.

Asynchronous event detection circuitry is to detect an asynchronous event in the received data for the one downstream port. Port selection circuitry to select the one downstream port.

Timer circuitry is to measure a time period from a time that the asynchronous event detection circuitry detects an asynchronous event. Synchronous event detection circuitry is to detect a synchronous event in the received data for the one port. End-of-event generation circuitry to generate a simulated end-of-event signal if the detected synchronous event is not before the end of the measured time period, and to provide the simulated end-of-event signal to the upstream port.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a USB hub.

FIG. 2A illusuates a host transferring data from a host to a device.

FIG. 2B illustrates a device transferring data to a host.

FIG. 3 illustrates an improved USB system.

FIGS. 4A to 4J illustrates the timing of a normal (non-noise) USB transfer on the FIG. 3 system.

FIGS. 5A to 5K illustrate the timing of signals within the FIG. 3 system when there is a noise event in the data signal.

DETAILED DESCRIPTION

FIG. 3 shows, in block form, an improved USB system whereby noise events will not cause significant "block" conditions. The improved system shown in FIG. 3 is now discussed in detail with reference to the timing diagrams shown in FIGS. 4 and 5. The FIG. 4 timing diagram illustrates how the FIG. 3 system reacts to a normal Universal Serial transfer. FIG. 5, by contrast, illustrates how the FIG. 3 system reacts to an asynchronous noise event.

Referring now to FIG. 4, the d0-- plus and d0-- minus traces (FIGS. 4A and 4B, respectively) represent data on the upstream port of a USB hub. A packet is sent upstream from downstream port 2--the data on downstream port 2 is represented by the d2-- plus and d2-- minus traces (FIGS. 4C and 4D, respectively). As the packet is first detected by the asynchronous detector for port 2 (denoted as "Asyn-- K-- det" in FIG. 3), the bs2-- asn-- k signal (FIG. 4E) is asserted by a decoder in the port. The ds-- tsel signal (FIG. 4F is asserted by the port state machine to indicate that a provisional direction selection has been made. Meanwhile, the glitch counter asserts the lookfor13 k signal (FIG. 4J), which is a timer signal. When the synchronous detector on the port is selected, the t-- usd signal (FIG. 4G) is asserted and the WASP signal (FIG. 4I) is deasserted, indicating that the hub repeater state machine is no longer in a state of waiting for a pulse. In addition, the provisional selection signal ds-- sel is deasserted. Meanwhile, the glitch-- det signal (FIG. 4H remains deasserted because the synchronous K signal was received (as indicated by the t-- usd signal being asserted) before the glitch counter timed out.

The operation of the glitch counter is discussed in more detail immediately below with reference to a situation where the asynchronous K signal received (FIGS. 5C and 5D) is in response to a glitch. Specifically, the FIG. 5 timing diagram (FIGS. 5C and 5D) illustrates a situation where an asynchronous event that occurs on Port 2 is a glitch, and not the start of a data packet. The glitch causes the asynchronous detector on port 2 to assert the detection signal, bs2-- asn-- k (FIG. 5E), which in turn causes the bs-- ds-- tsel signal FIG. 5F) to be asserted, indicating that the transfer direction is set to "lupstream". At this point, the counter begins to count down a predetermined time (e.g., 16 cycles of the 48 MHz sampling clock). The sh.lookfor-- k signal (FIG. 5J) is asserted while the glitch counter is counting down. That is, the sh.lookfor-- k signal being asserted indicates that it is expected to detect a synchronous K. As discussed above with reference to FIG. 4, if a synchronous-- K is detected before the predetermined time expires, then the glitch counter is reset and the data packet is processed normally. Otherwise, if the predetermined time expires before a synchronous-- K is detected, then a single-ended zero (SEO) is inserted, by the EOP inserter, on d0-- plus and dO-- minus (FIGS. 5A and 5B), followed by an "idle" (FIG. 5K), to simulate an end-of-packet (EOP). This allows any upstream hub to remove its selection of this port should the glitch have propagated upstream.

Thus, a hub controller as shown in FIG. 3 need not rely on the intervention of management software to re-enable the connection that would otherwise be tied up as the result of a noise event, thereby increasing the availability of devices in a USB interconnect.

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Reference
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6067628 *Apr 9, 1998May 23, 2000Intel CorporationMethod to monitor universal serial bus hub overcurrent
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Classifications
U.S. Classification710/60, 375/211
International ClassificationG06F11/00, H04L12/403
Cooperative ClassificationH04L12/4625, G06F11/002, G06F11/0757
European ClassificationH04L12/46B7B
Legal Events
DateCodeEventDescription
Nov 12, 2010FPAYFee payment
Year of fee payment: 12
Nov 13, 2006FPAYFee payment
Year of fee payment: 8
Sep 23, 2002FPAYFee payment
Year of fee payment: 4
Oct 2, 1997ASAssignment
Owner name: NATIONAL SEMICONDUCTOR CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BRIEF, DAVID;REEL/FRAME:008837/0410
Effective date: 19970929