|Publication number||US5904575 A|
|Application number||US 08/799,153|
|Publication date||May 18, 1999|
|Filing date||Feb 14, 1997|
|Priority date||Feb 14, 1997|
|Publication number||08799153, 799153, US 5904575 A, US 5904575A, US-A-5904575, US5904575 A, US5904575A|
|Inventors||Emi Ishida, Xiao-Yu Li, Sunil D. Mehta|
|Original Assignee||Advanced Micro Devices, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Referenced by (28), Classifications (34), Legal Events (10)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The following U.S. patent applications are assigned to the assignee of the present application, are related to the present application and its disclosure and are incorporated herein by reference:
(A) Ser. No. 08/799,230, by E. Ishida, et al. and entitled METHOD OF SELECTIVELY ANNEALING DAMAGED DOPED REGIONS.
(B) Ser. No. 08/799,236, now U.S. Pat. No. 5,795,627, by Mehta, et al. and entitled A METHOD FOR ANNEALING DAMAGED SEMICONDUCTOR REGIONS ALLOWING FOR ENHANCED OXIDE GROWTH.
(C) Ser. No. 08/799,235, now U.S. Pat. No. 5,885,904, by Mehta, et al. and entitled A METHOD TO INCORPORATE, AND A DEVICE HAVING, OXIDE ENHANCEMENT DOPANTS USING GAS IMMERSION LASER DOPING (GILD) FOR SELECTIVELY GROWING AN OXIDE LAYER.
(D) Ser. No. 08/689,523, by Barsan, et al. and entitled AN INTEGRATED CIRCUIT HAVING, AND PROCESS PROVIDING, DIFFERENT OXIDE LAYER THICKNESSES ON A SUBSTRATE.
(E) Ser. No. 08/561,306, by Barsan, et al. and entitled MULTIPLE GATE OXIDE THICKNESSES ON A WAFER SUBSTRATE.
(F) Ser. No. 08/699,401, by Mehta, entitled OXIDE FORMATION PROCESS FOR MANUFACTURING PROGRAMMABLE LOGIC DEVICE.
The following U.S. patent is assigned to the assignee of the present application, is related to the present application and its disclosure is incorporated herein by reference:
(A) U.S. Pat. No. 4,924,278 issued May 8, 1990, to Logie and entitled EEPROM USING A MERGE SOURCE AND CONTROL GATE.
1. Field of the Invention
The invention relates to the process for providing nitrogen in a semiconductor substrate, particularly for forming an oxide region using differential oxide growth.
2. Description of the Related Art
A prevalent trend in the semiconductor industry is to increase the density of semiconductor devices formed on silicon substrates.
Programmable logic devices (PLD) are circuits which can be configured by a user to perform logic functions or serve as memory arrays. Generally, PLDs include a programmable array of cells and array control circuitry which is utilized to program the array with the desired implementation. The programmable array comprises a series of low-voltage, short channel floating gate transistors which store charge to reflect whether a particular cell is programmed with a bit of data. The programmed array reflects in a particular user's individual configuration for the programmable device, allowing users to customize the programmable logic device for a number of different applications.
One type of programmable logic device which has become popular due to its performance and cost characteristics are electrically erasable (E2) CMOS programmable devices.
Erasable CMOS technology is based on the concept of a stored charge on a floating gate. Electrons are transferred to the gate through a physical mechanism known as Fowler-Nordheim tunneling. For an electrically erasable cell, a tunnel oxide is present between the source and drain regions and the floating gate that is about one-third of the thickness of a traditional transistor gate oxide. Fowler-Nordheim tunneling involves placing a potential across the tunnel oxide which distorts the electric field and allows electrons to traverse the tunnel oxide upon which they become trapped on a floating gate.
The control circuitry of the cell--the program transistors--essentially comprise high voltage transistors capable of sustaining high electric fields. So called read transistors, which operate at low voltage, include a first junction, second junction and gate (defined by the word line of the device). A program junction is separated from the floating gate by an oxide layer having a thickness of approximately 180 Å. The program transistor includes a first junction, second junction and a gate which also rests on the oxide layer. The memory cell will also include a floating gate, separated from the program junction by a tunnel oxide which may be activated by the control gate. The thickness of tunnel oxide is in a range of approximately 80-100 Å.
When programming or erasing the device, a voltage is applied between the program and control gate nodes. The direction of the voltage determines whether the cell is erased or programmed. When erasing, the control gate is given a positive voltage and the program node is grounded. When programming, the program node voltage is elevated and the control gate is grounded.
Several alternative designs of memory cells are utilized. Characteristically, in an E2 CMOS PLD, four types of transistors are required: high voltage P channel, high voltage N channel, low voltage P channel, and low voltage N channel. Techniques for saving mask steps during the formation of these cells are advantageous as each mask savings reduces the cost of the overall device.
The trend of E2 PLD devices has been toward lower and lower supply voltages. Consequently, this has required a corresponding scaling down of the gate oxide and two different oxide thicknesses for the gate and tunnel oxides. As the gate oxide thicknesses have been scaled down, they have reached and become even thinner than the tunnel oxide on lightly or undoped silicon.
Traditionally, the manufacturing process for implementing all four types of cells requires a large number of sequential process steps. The reduction in processing steps, and specifically masking steps, is an objective of nearly every process engineer. Each savings of a masking step may result in a significant saving in the cost of manufacture of the particular device.
Generally, four separate masking steps were required to complete the formation of the tunnel regions and overlying oxides for the four different types of devices.
U.S. patent application Ser. No. 08/699,401, entitled OXIDE FORMATION PROCESS FOR MANUFACTURING PROGRAMMABLE LOGIC DEVICE, discloses a scheme for reducing the number of masks required for forming the transistors from four to three. The benefit of this is the savings of a mask step, but the process contemplates that the thickness of the tunnel region mask and either the n-channel or p-channel high voltage transistor will be the same. In addition, U.S. patent applications entitled AN INTEGRATED CIRCUIT HAVING, AND PROCESS PROVIDING, DIFFERENT OXIDE LAYER THICKNESSES ON A SUBSTRATE and MULTIPLE GATE OXIDE THICKNESSES ON A WAFER SUBSTRATE referenced above disclose methods for forming different oxide thicknesses on a semiconductor substrate. In particular, these applications disclose a method for forming a write transistor with a first oxide thickness, a read transistor with a second oxide thickness and a tunnel oxide with a third oxide thickness.
Typically, in forming a the tunnel and gate oxide regions, a separate mask, etch and growth step is required for the tunnel oxide region. Each of these steps adds to the ultimate cost of the device.
In formation of oxides in general, it is generally known that the provision of nitrogen into the silicon substrate prior to forming the oxide by thermal formation in an oxygen atmosphere results in a different growth of oxide between the region overlying the nitrogen deposited region and the region of the substrate where no nitrogen has been deposited. However, where the oxide thicknesses are relatively small, care must be taken not to damage the surface of the silicon substrate, as growth of the oxide will be impaired.
Conventionally, nitrogen may be implanted at a relatively low energy into the substrate. However, implantation can cause a substrate damage which is difficult to anneal out using conventional annealing methods, and compromise the quality of the oxide for small thicknesses.
One aspect of the invention, roughly described, comprises a method for forming an oxide on the surface of a semiconductor substrate. The method includes the steps of: placing the semiconductor substrate in an atmosphere containing an atmosphere of an oxide growth inhibiting dopant; applying laser energy to at least a first portion of the substrate; and forming the oxide on the surface of the substrate by heating the substrate.
In a further aspect of the invention, the method comprises applying a directional energy beam through a patterned reflective reticle. Alternatively, prior to the step of placing, a reflective mask layer is applied to the surface of the semiconductor substrate.
In yet another aspect the ambient atmosphere is a nitrogen-containing atmosphere.
An additional embodiment of the invention includes the step of applying a second dose of laser energy to the portion of the substrate, the energy being sufficient to melt the surface of the substrate to a sufficient depth of the portion.
In addition, the invention comprises an EEPROM memory cell having a program junction region in a semiconductor substrate. The cell comprises at least a first program junction provided in the silicon substrate and a floating gate having a portion positioned over the program junction. An oxide layer is positioned between the program junction and the floating gate, with the oxide formed by a single thermal oxidation step to have at least a first oxide thickness and a second oxide thickness due to gas immersion laser doped nitrogen underlying a region of the oxide having said at least first oxide thickness. In an additional embodiment, the first thickness can be zero.
The invention will be described with respect to the particular embodiments thereof. Other objects, features, and advantages of the invention will become apparent with reference to the specification and drawings in which:
FIG. 1 is a cross-section of a conventional E2 PROM memory cell which may be formed in accordance with the present invention.
FIG. 2 is a cross-section of a semiconductor substrate during the formation of an E2 PROM memory cell showing portions of the cell being formed.
FIG. 3 is a cross-section of a semiconductor substrate of the memory cell shown in FIG. 2 showing, in general, formation of the tunnel oxide region.
FIGS. 4-9 are cross-sections of a semiconductor substrate showing a first embodiment for forming a nitrogen region employing an oxide on the surface of the substrate.
FIGS. 10-15 demonstrate a second embodiment for forming a nitrogen region below the surface of a semiconductor substrate and forming an oxide through differential oxide growth.
In the following description, numerous details, for example, specific materials, process steps, etc., are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the specific details need not be employed to practice the present invention. Moreover, specific details of particular processes or structures may not be specifically presented in order not to unduly obscure the invention where such details would be readily apparent to one of average skill in the art.
FIG. 1 is an illustrative cross-section of an exemplary E2 PROM memory cell. FIG. 1 does not show an actual cross section of a manufactured E2 PROM cell, but rather an illustrative cross-section of the various transistors and their internal connections. The process of the present invention is useful in forming an E2 PROM memory cell. However, the method of the present invention is not limited to uses with E2 PROM memory technology and one of average skill in the art will readily recognize the myriad uses of the method in any application requiring a uniform oxide layer at a relatively small thickness.
As shown in FIG. 1, the E2 PROM memory cell 100 is formed on a semiconductor substrate 102 having a surface 104. The cell comprises floating gates 106a-b, control gate 108 and program junctions 110a-b. Field oxide regions 112 separate active regions of the semiconductor devices. A sense transistor 114 is formed by junction regions 116 and 118 and floating gate 106b, while the read transistor 120 is formed by junction region 118, junction region 122 and gate 124. Various thicknesses of an oxide layer 130 cover the surface 104 of semiconductor 102. The oxide 130 has a thickness of, for example, 150 Å at region 130a, a thickness of 88 Å at region 130b, the tunnel oxide region, a thickness of 180 Å at region 130c overlying the control gate, a thickness of 150 Å over the channel of sense transistor 114 at region 130d, and a thickness of 80 Å over the channel of read transistor 120 at region 130e.
These oxide thicknesses have been provided for illustrating this particular embodiment. In other embodiments, other oxide thicknesses may be used. For example, other oxide thicknesses are described in the above-referenced patent applications entitled AN INTEGRATED CIRCUIT HAVING, AND PROCESS PROVIDING, DIFFERENT OXIDE LAYER THICKNESSES ON A SUBSTRATE. It should also be understood that for convenience, the oxide layers shown in the following figures is depicted growing only upwards from the oxidated surface. In actuality, the oxide layer grows bidirectionally above and below the initial surface.
Operation of memory cell 100 is also described in detail in the above-referenced patent application entitled AN INTEGRATED CIRCUIT HAVING, AND PROCESS PROVIDING, DIFFERENT OXIDE LAYER THICKNESSES ON A SUBSTRATE.
FIGS. 2 and 3 illustrate one conventional procedure for forming oxides of varying thickness on a semiconductor substrate, and particularly for forming the gate oxide layer and tunnel oxide regions of an E2 PROM cell. FIG. 2 shows substrate 102 upon which has been formed a well region 132, isolation oxide regions 134a-134e, a gate oxide layer 140, and the program junction region 142. It should be readily understood that numerous process steps are required to reach the cross-section representation of the substrate shown in FIG. 2.
By way of example, the substrate 102 undergoes a number of pre-growth etching, cleaning and implant steps. More specifically, cleaning steps, barrier oxidation steps, and zero level etching steps will have been performed on substrate 102. In addition, well implant regions may be provided in substrate 102 in accordance with known techniques (for example, an implant of boron at 5.6×1012 atom/cm.2 at 60 KeV). Subsequently, source/drain regions, isolated from each other by field oxide regions, will be formed by depositing, for example, a nitride layer of between 1,500 and 1,800 Å on the substrate, forming a source/drain mask over the nitride layer, and etching the nitride layer leaving portions of the layer covering the source/drain regions. It should be recognized that the wells may be formed subsequent to the source/drain pattern etch.
Subsequently, device isolation regions may be formed in the substrate. Such regions are typically formed by so-called shallow trench oxidation or local oxidation of silicon (LOCOS) processes. In a LOCOS process, for example, isolation regions 134a-134e are formed in substrate 102 by placing the substrate in an atmosphere of oxygen with 0.5% HCl at a temperature of about 1,100 to 1,150° Celsius to form oxide regions 134a-134e having a thickness of between 3,700 and 4,300 Å. As is well known, the nitride portions remaining on the substrate cover the source/drain regions and prevent field oxidation in these regions. An etch back is subsequently performed on the field oxide layer and the nitride layer removed leaving source/drain substrate regions remaining between field oxide regions 134a-134e.
Additional processing steps include: forming the program junction through the use of a program junction mask layer, implant and anneal; an n-channel field mask and implant; a cell mask and implant; high-voltage n-type implant; high-voltage p-type implants; punch-through masking and implants; and a high-voltage gate oxide cleaning step.
Gate oxidation layer 130c is also conventionally formed by placing the structure shown in FIG. 2 without the associated gate oxide layer in an oxygen-containing atmosphere 900° C. for approximately thirty minutes to create a gate oxide layer having an initial thickness of approximately 125 Å on a substrate and 150 Å on a program junction. As shown in FIG. 3, a resist mask 150 must be applied over the surface of the substrate and an oxide etch performed. A second oxidation which simultaneously forms the tunnel oxide 130b, oxide layers 130a and 130d to a thickness of approximately 150 Å and oxide layer 130c has a thickness of approximately 180 Å.
As noted previously, any consolidation of processing steps, or the elimination of masking and etching steps, is advantageous in the industry. The method of the present invention allows removal of the masking step shown in FIG. 3. It is generally known that the provision of nitrogen underlying the surface of a semiconductor substrate will inhibit the oxidation of thermal oxide formed on the substrate. This phenomenon, generally referred to as differential oxide growth, takes advantage of the differential rate of oxidation of pure silicon vs. the inhibited rate of oxidation of silicon doped with nitrogen.
Conventionally, nitrogen is implanted into the surface of the semiconductor substrate in order to achieve this effect. Ion implantation is a useful process for providing the nitrogen in the semiconductor substrate, but does have certain drawbacks. With respect to providing small transistor geometries, one critical limitation is that the silicon substrate can be damaged by the implant process. Damage caused by the implant process necessitates a subsequent annealing at high temperature to cure the damage in small geometry applications. This annealing step can itself lead to unpredictability in the migration of other dopants in the structure being processed. In addition, the implant will cause a region of damage adjacent to the substrate surface which will prohibit the growth of extremely thin oxide layers. Generally, it is difficult to cure this damage through conventional annealing while not adversely affecting other dopants and structures in a device being formed.
An alternative form of doping which has heretofore not been widely used in processing semiconductor devices is gas immersion laser doping (GILD).
Generally, with laser doping, the silicon surface is exposed to intense irradiation by an excimer laser for a period lasting only several nanoseconds (approximately 50 ns or less). During this period, the silicon surface transitions from solid to liquid, at which time dopants diffuse into the liquid silicon.
Specifically, laser doping uses an excimer laser, often as XeCl laser, as an energy source. The output of the laser is directed through optics to homogenize the beam and then passed through an illuminator to scan the beam over a dielectric reticle. The reticle is then imaged, via projection optics, onto the wafer. In the illuminated areas, the incident photon energy is absorbed in approximately the top 7 nm of the silicon and converted to thermal energy, heating the surface and activating the diffusion of the impurities into the substrate. More information with respect to laser doping is contained in Weiner & McCarthy, "Fabrication of sub-40-nm p-n junctions for 0.18 μm MOS device applications using a cluster-tool-compatible, nanosecond thermal doping technique," Microelectronic Processes, Sensors, & Controls, Vol. 2091 (Int'l Soc. for Optical Eng., September 1993).
Laser doping is advantageous for several reasons. First, dopants generally will penetrate throughout the liquid silicon, but will only minimally diffuse into the solid regions. Thus, junction depth is controlled by the melt depth of the silicon. Second, high-temperature anneal steps are not required because impurities are incorporated into electrically active sites and no damage is imparted to the substrate due to the epitaxial regrowth of the silicon. Third, control of the process is generally simple. Fourth, the process results in low sheet and contact resistances. And finally, the process eliminates considerable photoresist processing.
Despite its many advantages, laser doping has not become widespread.
A detailed analysis of laser doping techniques, see Stanford University Ph.D. Thesis by Emi Ishida entitled "New Methods of Shallow Junction Formation in Silicon Using Gas Immersion Laser Doping" (November 1994), hereby specifically incorporated by reference.
FIGS. 4-9 show a first embodiment of the present invention wherein the P-GILD process is used to provide nitrogen in a semiconductor substrate and form an oxide layer having first and second thicknesses in a single oxide growth step.
FIG. 4 shows a semiconductor substrate 160 upon which an oxide is to be formed immersed in an atmosphere containing a reaction-inhibiting agent, such as nitrogen. Substrate 160 may represent a semiconductor substrate at any of a number of various locations in a larger semiconductor manufacturing process wherein an oxide layer needs to be formed having different thicknesses. It should be recognized that the invention is not limited to a particular process or technology.
FIG. 5 shows a reflective reticle 162 comprised of, for example, a dielectric stack or diffraction mask is placed above substrate 160 in a nitrogen-containing atmosphere. The nitrogen-containing atmosphere may be comprised of N2, NH3, or any other suitable gas. Alternatively, the gas can be any chemical compound wherein use of GILD will incorporate (in a pyrolytic process) or deposit (in photolytic process) an oxide growth-inhibiting agent into the silicon through GILD. The reflective reticle may be used in the application of incorporating or depositing nitrogen using the GILD process. Hence, the process does not require a separate masking layer, although in an alternative embodiment of the present invention (described below), a reflective masking layer may be utilized. As shown in FIG. 5, laser energy represented by arrows 164 is applied through the nitrogen-containing atmosphere to form a nitrogen-containing region 170 in substrate 160 as shown in FIG. 7.
In general, there are two types of gas immersion laser doping which can be utilized to provide the nitrogen in nitrogen region 170. In conventional GILD processing, doping occurs when the laser energy incident on the surface of substrate 160 is sufficient to melt the silicon surface. Absorbed dopant gas species diffuse into the molten silicon layer, and dopants are incorporated upon epitaxial regrowth.
The energy fluence of the laser at the surface of the sample determines the duration of the melt which occurs at the surface. The melt duration is related to the maximum melt depth, which will result in the junction depth of the nitrogen incorporation since solid phase diffusion beyond the melt can be avoided for the less than one microsecond thermal cycle of the process. The relationship between melt time and maximum melt depth depends on the temporal profile of the laser beam. Precise control of junction depth is possible due to the capability of measuring the FWHM of the laser and the surface melt duration during the laser doping process. Relatively large changes in the energy fluence are required to create small changes in the maximum melt depth. The dosage is controlled by the total melt time and by dopant gas partial pressure in the nitrogen. The total melt time can be varied by varying the number and/or energy of the laser pulses.
In a melt GILD process, the silicon is molten for approximately 30-100 nanoseconds. It will cool in approximately 1 microsecond. It should be recognized that the power of the laser is relative to the junction depth of the implant. A laser having energy of approximately 750 mJ/cm2 to 1.3 J/cm2 results in junction depths ranging from 20 nanometers to 150 nanometers.
The ambient in the deposition chamber is about a 50 torr dopant ambient, in which the substrate is irradiated with pulses from a 308 nm excimer laser at a 9 Hz repetition rate.
A second form of the GILD process can be utilized under "non-melt" conditions. Non-melt GILD allows greater control of the dose and incorporates dopants into the silicon substrate by solid-phase diffusion. Conditions for "non-melt" are determined using a separate HE-NE laser in-situ to perform reflectivity measurements to monitor the melt to non-melt transition. The exact principles of this process are described in the aforementioned Ishida reference.
Non-melt doping is achieved by using sub-melt laser energy fluences, higher pulse repetition rates, and 100-times greater number of pulses than that compared with conventional GILD. The solid region occurs in a range of fluences less than 650 mJ/cm2, with the transition being in a range of about 200 mJ/cm2. Although fully melted layers are completely activated, non-melt dope layers are not and generally require an annealing step to complete activation. In addition, there is a chance that some damage to the underlying silicon substrate which would affect the growth of extremely thin oxide layers may result from solid phase diffusion of dopants under non-melt GILD.
If solid phase diffusion is used, a subsequent application of laser energy, shown in FIG. 8, of a sufficient strength to melt the dopant region to the incorporation or deposition depth, may be required to cure the damage caused by the solid phase deposition. The energy of the laser applied in this step can be controlled to an accuracy necessary to melt only the surface of the substrate to a depth (typically 7-150 nm) that the dopant has diffused into the substrate. Once melted, the silicon will reform as epitaxial silicon and any damage which is imparted to the surface of the substrate 160 during the dopant process will be removed. This allows re-crystallization of the silicon. Alternative forms of curing the damage to the substrate may be utilized, such as, for example, annealing the dopant region 170 utilizing a rapid thermal anneal.
If a melt GILD process is utilized, the reapplication of laser energy as illustrated in FIG. 8 is not necessary, as the surface of the silicon substrate will recrystallize upon cooling. However, the reapplication of laser energy may be utilized if desired.
Subsequently, as shown in FIG. 9, substrate 160 can be placed in an oxygen-containing atmosphere at a temperature of approximately 900° sufficient to thermally oxidize the surface of the substrate to grow an oxide layer 172 having a sufficient thickness on undoped regions of substrate 160, while growth in region 174 is inhibited by the nitrogen region 170. The resulting oxide region will have a first thickness of approximately 80-100 Å in region 174, and a second thickness of approximately 140-180 Å in the undoped regions of the substrate. It should be recognized that the incorporation or deposition of the growth-inhibiting impurity may be in a concentration sufficient to completely inhibit oxide formation, resulting in no growth in region 174.
In the aforementioned method of the present invention, the lithography stepper is combined with the GILD doping tool. The laser is patterned by projecting the beam through a reticle, eliminating the need for an aluminum reflectivity mask. This, in turn, eliminates the need for a photoresist and solvents associated with each masking step. However, in an alternative embodiment the GILD process may be utilized with a reflective mask on the surface of the substrate to incorporate nitrogen in a silicon substrate.
FIGS. 10-15 show an alternative method of the present invention similar to that shown in FIGS. 4-9, except that a reflective mask layer 180 is provided on the surface of silicon substrate 160. Reflective mask layer 180 can be, for example, an aluminum masking layer, or an oxide masking layer. The oxide masking layer has the advantage that metal contamination of the resulting structure is avoided. As shown in FIG. 11, the substrate including mask layer 180 is again placed in a nitrogen-containing atmosphere, laser energy is applied in FIG. 12, and the nitrogen-containing region 170 is formed as shown in FIG. 13. Again, the energy can be formed utilizing a melt or non-melt process, and if a non-melt process is used, a laser annealing step as shown in FIG. 14 may be utilized. The step shown in FIG. 14 would not be required if a melt process is utilized, as discussed above, but its use with a melt GILD process is contemplated. As shown in FIG. 15, a layer of oxide is again grown in a manner similar to that described with respect to FIG. 9.
Hence, in any of the various modes of the present invention, the necessity of an additional mask layer, etching steps and oxide growth steps is removed in forming an oxide layer having at least a first thickness and a second thickness. It should be recognized that through the use of differently patterned reticles, the control over various implants into the substrate can be varied so that certain regions of the substrate have a greater amount of nitrogen than others, thereby further controlling the differential between the growth of such regions with respect to other doped and non-doped regions, thereby yielding an oxide layer with any number of thicknesses through a single growth step.
The many features and advantages of the present invention should be apparent to one of average skill in the art. All such features and advantages are intended to be within the scope of the invention as defined by the present specification, and the following claims. It should be recognized that the method of the present invention is not limited to its uses in memory technology, but would be applicable in any semiconductor method fabrication process requiring varying levels of oxide on a semiconductor substrate. The method of the present invention possesses the advantages of eliminating the necessity of using a separate masking step to form a thinner tunnel oxide, and provides the advantage of reducing the number of steps in the process. The present invention provides a unique method for introducing nitrogen into a shallow region in the silicon substrate in order to enable differential oxide growth.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4482393 *||Dec 15, 1980||Nov 13, 1984||Sony Corporation||Method of activating implanted ions by incoherent light beam|
|US4500365 *||Feb 16, 1983||Feb 19, 1985||Fujitsu Limited||Laser treating implanted semiconductor surface through photo-resist layer|
|US4585492 *||Jul 30, 1984||Apr 29, 1986||International Business Machines Corporation||Rapid thermal annealing of silicon dioxide for reduced hole trapping|
|US4621413 *||Jun 3, 1985||Nov 11, 1986||Motorola, Inc.||Fabricating a semiconductor device with reduced gate leakage|
|US4924278 *||Nov 15, 1988||May 8, 1990||Advanced Micro Devices, Inc.||EEPROM using a merged source and control gate|
|US5227329 *||Aug 30, 1991||Jul 13, 1993||Hitachi, Ltd.||Method of manufacturing semiconductor device|
|US5279973 *||Oct 15, 1991||Jan 18, 1994||Kabushiki Kaisha Toshiba||Rapid thermal annealing for semiconductor substrate by using incoherent light|
|US5316969 *||Dec 21, 1992||May 31, 1994||Board Of Trustees Of The Leland Stanford Junior University||Method of shallow junction formation in semiconductor devices using gas immersion laser doping|
|US5352636 *||Jan 16, 1992||Oct 4, 1994||Applied Materials, Inc.||In situ method for cleaning silicon surface and forming layer thereon in same chamber|
|US5514880 *||Oct 28, 1993||May 7, 1996||Mitsubishi Denki Kabushiki Kaisha||Field effect thin-film transistor for an SRAM with reduced standby current|
|US5591681 *||Jun 3, 1994||Jan 7, 1997||Advanced Micro Devices, Inc.||Method for achieving a highly reliable oxide film|
|US5620931 *||Jun 6, 1995||Apr 15, 1997||Analog Devices, Inc.||Methods for fabricating monolithic device containing circuitry and suspended microstructure|
|US5750428 *||Sep 27, 1996||May 12, 1998||United Microelectronics Corp.||Self-aligned non-volatile process with differentially grown gate oxide thickness|
|US5756385 *||Nov 22, 1995||May 26, 1998||Sandisk Corporation||Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers|
|US5817550 *||Mar 5, 1996||Oct 6, 1998||Regents Of The University Of California||Method for formation of thin film transistors on plastic substrates|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6232244 *||May 1, 2000||May 15, 2001||Advanced Micro Devices, Inc.||Methodology for achieving dual gate oxide thicknesses|
|US6268266 *||Oct 22, 1999||Jul 31, 2001||United Microelectronics Corp.||Method for forming enhanced FOX region of low voltage device in high voltage process|
|US6303521 *||Oct 17, 2000||Oct 16, 2001||United Microelectrics Corp.||Method for forming oxide layers with different thicknesses|
|US6319759 *||Aug 10, 1998||Nov 20, 2001||International Business Machines Corporation||Method for making oxide|
|US6355531||Aug 9, 2000||Mar 12, 2002||International Business Machines Corporation||Method for fabricating semiconductor devices with different properties using maskless process|
|US6423647 *||Dec 11, 2000||Jul 23, 2002||Advanced Micro Devices, Inc.||Formation of dielectric regions of different thicknesses at selective location areas during laser thermal processes|
|US6506646 *||Sep 28, 2000||Jan 14, 2003||Oki Electric Industry Co., Ltd.||Method for manufacturing a semiconductor memory|
|US6586318 *||Dec 28, 1999||Jul 1, 2003||Xerox Corporation||Thin phosphorus nitride film as an N-type doping source used in laser doping technology|
|US6680225||Oct 24, 2002||Jan 20, 2004||Oki Electric Industry Co., Ltd.||Method for manufacturing a semiconductor memory|
|US6716705 *||Jun 3, 2002||Apr 6, 2004||Lattice Semiconductor Corporation||EEPROM device having a retrograde program junction region and process for fabricating the device|
|US6764930 *||Sep 26, 2001||Jul 20, 2004||Agere Systems Inc.||Method and structure for modular, highly linear MOS capacitors using nitrogen implantation|
|US6818535 *||Oct 28, 2002||Nov 16, 2004||Xerox Corporation||Thin phosphorus nitride film as an n-type doping source used in a laser doping technology|
|US7189624 *||Jun 16, 2004||Mar 13, 2007||Kabushiki Kaisha Toshiba||Fabrication method for a semiconductor device including a semiconductor substrate formed with a shallow impurity region|
|US7453090||Feb 1, 2007||Nov 18, 2008||Kabushiki Kaisha Toshiba||Semiconductor device including a semiconductor substrate formed with a shallow impurity region|
|US7687256||Mar 30, 2010||Spire Corporation||Surface activated biochip|
|US7804148||Feb 16, 2006||Sep 28, 2010||International Business Machines Corporation||Opto-thermal mask including aligned thermal dissipative layer, reflective layer and transparent capping layer|
|US7875560 *||Mar 29, 2006||Jan 25, 2011||Infineon Technologies Austria Ag||Semiconductor having optimized insulation structure and process for producing the semiconductor|
|US8836037 *||Aug 13, 2012||Sep 16, 2014||International Business Machines Corporation||Structure and method to form input/output devices|
|US9142447||Dec 23, 2010||Sep 22, 2015||Infineon Technologies Austria Ag||Semiconductor having optimized insulation structure and process for producing the semiconductor|
|US20030067037 *||Oct 28, 2002||Apr 10, 2003||Xerox Corporation||Thin phosphorus nitride film as an n-type doping source used in laser doping technology|
|US20050023577 *||Jun 16, 2004||Feb 3, 2005||Takayuki Ito||Semiconductor device including a semiconductor substrate formed with a shallow impurity region, and a fabrication method for the same|
|US20070138567 *||Feb 1, 2007||Jun 21, 2007||Kabushiki Kaisha Toshiba||Semiconductor device including a semiconductor substrate formed with a shallow impurity region, and a fabrication method for the same|
|US20070187670 *||Feb 16, 2006||Aug 16, 2007||International Business Machines Corporation||Opto-thermal annealing mask and method|
|US20070190739 *||Mar 29, 2006||Aug 16, 2007||Markus Zundel||Semiconductor having optimized insulation structure and process for producing the semiconductor|
|US20100004144 *||Jan 7, 2010||Spire Corporation||Surface activated biochip|
|US20110089528 *||Dec 23, 2010||Apr 21, 2011||Infineon Technologies Austria Ag||Semiconductor having optimized insulation structure and process for producing the semiconductor|
|DE10213813A1 *||Mar 27, 2002||Oct 23, 2003||Promos Technologies Inc||Molecular nitrogen implantation dosage estimation method for integrated circuit manufacture, involves building relation between molecular nitrogen implantation dosage and suppression ratio of oxide layer after thermal process|
|DE10213813B4 *||Mar 27, 2002||Mar 18, 2004||Promos Technologies, Inc.||Verfahren zum Bewerten der Stabilität eines Ionenimplantierers|
|U.S. Classification||438/770, 148/DIG.126, 257/E21.335, 257/E21.346, 438/795, 257/E21.625, 438/981, 257/E27.103, 257/E21.285|
|International Classification||H01L21/316, H01L21/265, H01L27/115, H01L21/266, H01L21/8234|
|Cooperative Classification||Y10S438/981, Y10S148/126, H01L21/02312, H01L21/266, H01L21/02255, H01L27/115, H01L21/823462, H01L21/26506, H01L21/0231, H01L21/02238, H01L21/31662|
|European Classification||H01L21/02K2E2B2B2, H01L21/02K2T2L, H01L21/02K2E2J, H01L21/02K2T2J, H01L21/316C2B2, H01L21/265A, H01L27/115, H01L21/8234J, H01L21/266|
|Feb 14, 1997||AS||Assignment|
Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ISHIDA, EMI;LI, XIAO-YU;MEHTA, SUNIL D.;REEL/FRAME:008507/0067
Effective date: 19970214
|Jan 6, 1998||AS||Assignment|
Owner name: VANTIS CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:009472/0719
Effective date: 19971219
|May 14, 1998||AS||Assignment|
Owner name: VANTIS CORPORATION, CALIFORNIA
Free format text: PATENT ASSIGNMENT AGREEMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:009178/0222
Effective date: 19971219
|Jun 6, 2002||AS||Assignment|
Owner name: LATTICE SEMICONDUCTOR CORPORATION, OREGON
Free format text: MERGER;ASSIGNOR:VANTIS CORPORATION;REEL/FRAME:012937/0738
Effective date: 20020211
|Sep 19, 2002||FPAY||Fee payment|
Year of fee payment: 4
|Oct 27, 2006||FPAY||Fee payment|
Year of fee payment: 8
|Dec 20, 2010||REMI||Maintenance fee reminder mailed|
|May 18, 2011||LAPS||Lapse for failure to pay maintenance fees|
|Jul 5, 2011||FP||Expired due to failure to pay maintenance fee|
Effective date: 20110518
|Mar 17, 2015||AS||Assignment|
Owner name: JEFFERIES FINANCE LLC, NEW YORK
Free format text: SECURITY INTEREST;ASSIGNORS:LATTICE SEMICONDUCTOR CORPORATION;SIBEAM, INC.;SILICON IMAGE, INC.;AND OTHERS;REEL/FRAME:035220/0048
Effective date: 20150310