|Publication number||US5908310 A|
|Application number||US 08/580,816|
|Publication date||Jun 1, 1999|
|Filing date||Dec 27, 1995|
|Priority date||Dec 27, 1995|
|Also published as||DE69636244D1, DE69636244T2, EP0782186A2, EP0782186A3, EP0782186B1, US6180972|
|Publication number||08580816, 580816, US 5908310 A, US 5908310A, US-A-5908310, US5908310 A, US5908310A|
|Inventors||Gary B. Bronner, Wilfried Hansch, Wendell P. Noble|
|Original Assignee||International Business Machines Corporation, Siemens Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (26), Non-Patent Citations (14), Referenced by (4), Classifications (12), Legal Events (9)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention generally relates to integrated circuit memories and, more particularly, to the formation of a plate for trench storage capacitors particularly as used in dynamic random access memories (DRAMs).
2. Description of the Prior Art
Basic and indispensable operations of digital data processing circuits involve the ability to fetch one or more sequences of digital signal bits from memory, perform an operation thereon and return the result to storage. Therefore, memory structures from which signals can be accessed and to which signals can be stored in a cycle time comparable to an operating cycle of the processing circuit have been required. To answer this requirement random access memories of both static and dynamic types have been developed and their respective designs continually refined over the years.
Recent advances in digital data processing circuits has greatly increased requirements for large capacity and improved functionality of storage which may be rapidly accessed by the processing circuitry in cycle times which have become extremely short. Dynamic random access memories have generally been used to answer the requirement of increased storage capacity since data is stored therein as charge on a capacitor which can be fabricated at extremely small size and in very large numbers on a single semiconductor chip. A well-known and widely used capacitor structure occupying an extremely small area on a chip is known as a trench capacitor which, in a basic form includes a capacitor dielectric and an electrode, as one capacitor plate, formed within a blind aperture (often oval in plan view) generally referred to as a trench, in a substrate; using a region within the substrate as the second capacitor plate common to the trench capacitors on the chip.
As is understood by those skilled in the art, storage or retrieval of signals is achieved in modern, high-capacity DRAMs by the storage of very small amounts of charge. Stored charge is also subject to leakage and must be periodically refreshed in order to avoid corruption of data and while the amount of stored charge remains sufficient to provide rapid and reliable response of sense amplifiers, generally by a "read and write back" combination of operations for each cell and which can be performed simultaneously or concurrently in parallel in different partitions of memory.
The speed with which writing can be done at a given voltage depends, to a large degree, on the parasitic series resistance of the memory cell capacitors. Therefore, it is often desirable to form a structure of enhanced conductivity to serve as a common capacitor plate for the memory cells on a chip or in a partition thereof. Such structures may also facilitate isolation of cells from mutual parasitic coupling effects. As a further refinement, as memory cells have become more densely integrated on a chip, applying a bias to such a conductive structure approximating a voltage mid-way between the logic signal levels allows reduction of electrical field and stress on the capacitor dielectric which can thus be made thinner. Reduction of the dielectric thickness, consistent with the levels of electrical stress which must be tolerated, increases capacitance of each trench capacitor and potential amount of charge storage at a given voltage and allows the "footprint" of each capacitor to be reduced. In view of the number of memory cells which can currently be fabricated on a chip, seemingly slight reductions in cell footprint can provide substantial chip space for further memory cells, so-called peripheral circuits for increased memory functionality and redundant circuits to increase manufacturing yield.
Some of the read, write and refresh operations as well as differentiation between partitions of memory can be facilitated by biasing the electrode which forms a common capacitor plate for a plurality of capacitors. Particularly as to differentiation between partitions, if partitions are provided, separate and mutually isolated common electrodes must be provided which, of course, cannot be done if the substrate forms a common electrode for all storage capacitors on the chip. Additionally, the extent of any such electrode must be readily determinable as an incident of chip design in order to avoid interference with other circuitry provided on the chip to allow access to memory cells and to store and recover data, such as address decoders, sense amplifiers and peripheral circuits.
Therefore, in recent DRAM designs, a separate, independently biasable electrode has been included by a buried doped region within the substrate, such as an n-type region within a p-type substrate and beneath a p-well provided for the capacitor array so that the electrode provided by the buried, doped region will surround the capacitor portion of each trench. (Generally an isolation or other region is formed at the bottom of the trench and some portion of the upper regions of the trench may include transistors or other circuit elements or portions thereof used for accessing a particular capacitor of a memory cell.)
Such buried electrodes have been formed in known DRAM designs, such as that disclosed in U.S. Pat. No. 5,264,716 to Donald M. Kenney and assigned to the assignee of the present invention and which is hereby fully incorporated by reference, by out-diffusion of plate dopant from a diffusion source within the trench, thereby assuring that the doped region so formed will surround the capacitor portion of the trench. However, the process steps required for forming an electrode in this manner involve deposition of the dopant source, masking the vertical dopant profile and removal of the dopant source by etching, These operations involve substantial process complexity and have been found to have a substantial adverse impact on manufacturing yield.
An alternative method involves the use of an n-type substrate into which a p-type surface implantation is made prior to etching of trenches. However, while avoiding process complexity, this approach introduces some additional problems and is subject to some severe operational limitations. Specifically, the low noise and high latch-up resistance of n-well CMOS logic circuitry are sacrificed, a new latch-up mechanism is presented by the necessary p-n-p-n vertical path, the freedom to bias the plate arbitrarily is eliminated, and costs of n-type wafers meeting particular resistivity specifications are substantially higher than for p-type wafers; substantially eliminating the cost benefit of the simpler process. Further, it is not entirely clear at the present state of the art that partitions can be successfully formed consistent with this alternative process.
It is therefore an object of the present invention to provide a low-cost, high yield process for forming a buried capacitor electrode compatible with formation of a high capacity DRAM.
It is another object of the invention to provide a method of plate formation which preserves the benefits of n-well CMOS technology formed on a low-cost p-type wafer, substrate or chip which does not require out-diffusion from an impurity source or other complex process which can compromise manufacturing yield.
It is a further object of the invention to provide a low cost, high yield process suitable for p-type wafers for forming a buried electrode which can be articulated at will during manufacture and which can be arbitrarily biased in each partition so formed.
In order to accomplish these and other objects of the invention, a method of forming a buried conductive layer in a semiconductor layer or wafer is provided including the steps of implanting impurities of a first type in a region of a semiconductor layer wafer of a second impurity type, growing an epitaxial layer of semiconductor material over a region including implanted impurities of a first type, and diffusing said impurities into said epitaxial layer.
In accordance with another aspect of the invention, a method of forming a trench capacitor in a semiconductor layer or wafer is provided including the steps of implanting impurities of a first type in a region of a semiconductor layer wafer of a second impurity type, growing an epitaxial layer of semiconductor material over a region including implanted impurities of a first type, and diffusing said impurities into said epitaxial layer, forming a trench extending at least to a region having diffused impurities in the epitaxial layer, forming a dielectric layer within the trench, and forming a storage node within the dielectric layer within the trench.
In accordance with a further aspect of the invention, a dynamic random access memory device is provided comprising a body of semiconductor material, a buried plate within the body of semiconductor material having a dopant concentration which varies with depth within the body of semiconductor material, an isolation region between the buried plate and a surface of the body of semiconductor material, a trench extending at least through the isolation region and into the buried plate, a capacitor dielectric formed within the trench, and a storage node formed within the dielectric layer within the trench.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
FIG. 1 is a cross-sectional view of a p-type wafer at an initial stage of a preferred implementation of a method in accordance with the invention,
FIGS. 2, 3 and 4 are cross sectional views of the wafer at intermediate stages of a preferred form of the method in accordance with the invention,
FIG. 5 is a cross-sectional view of a completed capacitor structure formed in accordance with the method of the invention, and
FIG. 6 is a graphical representation of as-found dopant profiles formed in accordance with the invention, as schematically represented in FIG. 4.
Referring now to the drawings, and more particularly to FIG. 1, there is shown, in cross-section, a p-type wafer 10 at an initial stage of the process in accordance with the invention. The wafer is masked, as depicted by dashed line 12 and patterned to open areas 16 between remaining mask areas 14. Then, an n-type impurity implantation, preferably of phosphorus to a concentration between 1014 cm-2 and 5×1016 cm-2 or greater at about 900 KeV, is performed in accordance with the mask to form n-type regions 20 as shown in FIG. 2. Some variation in implantation energy may be useful to develop an adequate thickness of the initial impurity concentration distribution in the implantation region 20. In theory, other n-type impurities may be used for implantation to concentration which develop comparable conductivities in the implanted region. However, phosphorous is preferred, particularly in view of diffusion rates of phosphorus in semiconductor wafer materials.
Any known mask and patterning suitable for implantation can be used. The particular masking process used is not important to the practice of the invention and the mask is preferably removed following the implantation. The lower impurity concentration is adequate, after diffusion, to support bias conditions resulting in accumulation of the plate. Concentrations approaching or even exceeding the higher concentration would be necessary to additionally support depletion of the plate so that an arbitrary bias can be applied. It should also be recognized that a mask is not necessary except for the purpose of division or articulation of the buried electrode into partitions or limiting the extent of the buried conductor in the vicinity of other circuits of the chip, as may be desired in the memory design, and can be omitted if only a single electrode is to be formed across the entire chip or wafer, common to all capacitors which are later formed.
While not of importance to the practice of the invention, it has been found preferable at this point in the process to again mask the structure with a blocking mask and to pattern openings for etching of alignment marks, if required.
As shown in FIG. 3, an epitaxial p-type layer 30 is then grown over the surface of the wafer; effectively burying the n-type implanted region within the p-type material. The thickness of this layer is not particularly critical to the practice of the invention but the thickness should accommodate the formation of transistors above the final n-type region developed by annealing, as will be described below with reference to FIGS. 4 and 6 while being sufficiently thin to allow connections to be made to the final n-type regions by desired processes, such as a further masked implantation. A thickness of approximately 4 μm is presently preferred as a balance between these considerations in view of preferred forms of trench capacitors to be later formed.
As shown in FIG. 4, the buried electrode is then expanded by annealing to spread the n-type implanted impurity downward into the wafer and upward into the epitaxial region by diffusion as well as to repair damage to the crystallographic structure of the wafer resulting from implantation. Quantitatively, as shown in FIG. 6, an initial implant of 1014 /cm2 at the preferred 900 KeV provides a sharply defined distribution peak at a depth of slightly less than 2 μm within the original wafer which, after epitaxial growth of 4 μm as shown in FIG. 3, would be depicted at a depth of slightly less than 6 μm, the approximate center of the dopant concentration peak resulting from a four minute anneal at 1200° C. shown by a solid line. As annealing proceeds with time, the center of the dopant concentration profile will remain centered at this location.
It should also be noted in consideration of FIG. 6 that the range of dopant concentrations noted above is set out as an area measure, as is the practice in the art. The dopant concentrations depicted in FIG. 6 are in volumetric measure and, since the thickness and, hence, volume of material over which the dopant is diffused is very small, the concentrations will appear several orders of magnitude larger. It should be borne in mind that the dopant concentration per unit volume will determine conductivity and whether or not a bias establishing depletion of the region (in addition to accumulation) can be supported and at what depths within the structure.
Accordingly, as diffusion proceeds over time, as shown by the dashed plot corresponding to 60 minutes and the dotted plot corresponding to 120 minutes, the peak concentration is reduced and the peak is widened. It should also be noted that the valleys such as 62 on either side of the peak which result from counter-doping also widen and deepen somewhat. These valleys are useful in providing isolation and it is therefore preferred that annealing be terminated prior to valley 62' being brought to the surface since it serves to isolate the buried conductor from circuits or devices which are formed at or on the surface of the wafer or substrate. However, if the overall doping concentrations are adequately low, such as 1016 /cm3 as shown near the surface in the 120 minute trace, isolation at a depth below the surface can be achieved by counter-doping; allowing increased flexibility in developing the final location and depth of valley 64, 64', 64" by continued annealing, if that feature is significant to the design. Whether isolation is provided by valley 62' or counter-doping, connections to the buried electrode can be made by patterned doping, an etched opening or in any other suitable manner, as generally depicted at 42 of FIG. 4, since the bulk of the buried electrode, at any desired dopant concentration possible following the initial implantation, can be brought arbitrarily near the surface as various designs may require.
It should also be understood that the actual dopant concentration varies with depth at respective points along the traces shown in FIG. 6 as well as the width (e.g. thickness) of the electrode for a given (e.g. accumulation and/or depletion) mode at a given bias. This can be regulated over a wide range by initial implantation concentration as well as annealing temperature and time; the traces of FIG. 6 corresponding to the lower extremity of the concentration range disclosed to be preferred, above. Thus, the dopant concentration, which varies with depth in accordance with the invention, provides a relatively well-defined boundary for the buried electrode for any particular bias or conduction mode. Therefore, the invention provides a very flexible methodology for developing electrodes of different dimensions and conduction qualities, as may be required in various designs of DRAMs and other semiconductor integrated circuits since initial dopant concentrations, thickness of epitaxial layer as well as the potential for developing asymmetry of the dopant concentration profile by counter-doping are all variable, at will, to meet the requirements of various designs.
Following annealing, as shown in FIG. 4, the wafer or substrate is again masked and patterned (e.g. 44) and trench 46 formed by anisotropic etching; many suitable techniques for which are well-known in the art. In this regard, outline 48 of the buried electrode represents any arbitrary dopant concentration level which will support a desired conductance at that location and bias (which may vary the location of the illustrated boundary somewhat) or the locations of valleys 62', 64' which provide isolation. In any event, the buried conductor formed in accordance with the invention has been found, in practice, to present relatively well-defined boundaries to or through which trench 46 may readily be formed and will thus define an area within the trench which will function as a capacitor upon formation of a dielectric and a further electrode (which would serve as a memory cell storage node of a DRAM).
Once trench 46 is formed, fabrication of the remainder of the capacitor structure can proceed in any known manner and in accordance with any design since the remainder of the process is not considered to be critical to the practice of the invention. An exemplary trench capacitor structure is shown in FIG. 5, including depiction of the original boundary of the implantation region 20 and the final boundary 48 of the buried electrode achieved by diffusion. Trenches 46 terminate within the buried electrode and isolation from the substrate is provided by lower electrode boundaries corresponding to dopant profile valleys 62', 64', respectively.
Within the trenches 46, a capacitor dielectric 52 is formed, preferably as an oxide-nitride-oxide (ONO) sandwich. Dielectric thickness may be increased or a connector or collar (e.g. 54) formed near the surface of the trench, as desired, and the remainder of the trench filled with polysilicon. Further connections may be formed by metallization or doping which may also form a conduction terminal 58 of a transistor 58' used to access or otherwise control the cell. Such a transistor may also be formed in a well 59 of opposite conductivity type if required by the design so long as the depth of the well remains above the electrode boundary 48 (although for some anticipated bias levels, a connection therebetween could be desirable).
In view of the foregoing, it is seen that the invention provides a low-cost, high yield process for forming a buried electrode which is of substantial flexibility for accommodation of a variety of designs, particularly designs for DRAMs including trench capacitors. The invention preserves the benefits of N-well CMOS technology and can be formed on low-cost p-type wafers or substrates while avoiding the process complexity of out-diffusion from dopant diffusion sources deposited in the trenches. The electrode formed in accordance with the invention can also support an arbitrary bias or range thereof, as may be required by an integrated circuit design and can be articulated and/or bounded at will, for example, to form memory partitions or accommodate other circuits such as decoders, sense amplifiers and peripheral circuits.
While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4688063 *||Oct 21, 1986||Aug 18, 1987||International Business Machines Corporation||Dynamic ram cell with MOS trench capacitor in CMOS|
|US4792834 *||Feb 1, 1988||Dec 20, 1988||Kabushiki Kaisha Toshiba||Semiconductor memory device with buried layer under groove capacitor|
|US4794434 *||Jul 6, 1987||Dec 27, 1988||Motorola, Inc.||Trench cell for a dram|
|US4801988 *||Oct 31, 1986||Jan 31, 1989||International Business Machines Corporation||Semiconductor trench capacitor cell with merged isolation and node trench construction|
|US4829017 *||Sep 25, 1986||May 9, 1989||Texas Instruments Incorporated||Method for lubricating a high capacity dram cell|
|US4873560 *||Feb 16, 1988||Oct 10, 1989||Hitachi, Ltd.||Dynamic random access memory having buried word lines|
|US4920389 *||Mar 7, 1989||Apr 24, 1990||Oki Electric Industry Co., Ltd.||Memory call array structure and process for producing the same|
|US5006909 *||Oct 30, 1989||Apr 9, 1991||Motorola, Inc.||Dram with a vertical capacitor and transistor|
|US5250829 *||Jan 9, 1992||Oct 5, 1993||International Business Machines Corporation||Double well substrate plate trench DRAM cell array|
|US5264716 *||Jan 9, 1992||Nov 23, 1993||International Business Machines Corporation||Diffused buried plate trench dram cell array|
|US5384474 *||Nov 5, 1993||Jan 24, 1995||International Business Machines Corporation||Double grid substrate plate trench|
|US5405790 *||Nov 23, 1993||Apr 11, 1995||Motorola, Inc.||Method of forming a semiconductor structure having MOS, bipolar, and varactor devices|
|US5476800 *||Jan 31, 1994||Dec 19, 1995||Burton; Gregory N.||Method for formation of a buried layer for a semiconductor device|
|US5571743 *||Aug 26, 1994||Nov 5, 1996||International Business Machines Corporation||Method of making buried-sidewall-strap two transistor one capacitor trench cell|
|EP0283964A2 *||Mar 18, 1988||Sep 28, 1988||Nec Corporation||Dynamic random access memory device having a plurality of improved one-transistor type memory cells|
|EP0298421A2 *||Jul 5, 1988||Jan 11, 1989||Kabushiki Kaisha Toshiba||Semiconductor device having different impurity concentration wells|
|EP0540443A2 *||Oct 9, 1992||May 5, 1993||International Business Machines Corporation||Complementary subcollectors with silicon epitaxial layers|
|JPH0228367A *||Title not available|
|JPH01292852A *||Title not available|
|JPH02135776A *||Title not available|
|JPH03232266A *||Title not available|
|JPH06120241A *||Title not available|
|JPS6072258A *||Title not available|
|JPS6224617A *||Title not available|
|JPS60105265A *||Title not available|
|JPS63246861A *||Title not available|
|1||"A 45-ns 16-Mbit DRAM with Triple-Well Structure"; Syuso Fujii et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989; pp. 1170-1175.|
|2||"New Well Structure For Deep Sun-μm CMOS/BiCMOS Using Thin Epitaxy Over Buried Layer and Trench Isolation"; Y. Okazaki et al.; NTT LSI Laboratories; 1990 Symposium on VLSI Technology; 1990 IEEE; pp. 83-84, (no month).|
|3||*||A 45 ns 16 Mbit DRAM with Triple Well Structure ; Syuso Fujii et al., IEEE Journal of Solid State Circuits, vol. 24, No. 5, Oct. 1989; pp. 1170 1175.|
|4||*||D. Kenney et al., Symp. VLSI Technol. 1992, pp. 14 15 A Buried Plate Trench Cell for a 64 mb DRAM , no month 1992.|
|5||D. Kenney et al., Symp. VLSI Technol. 1992, pp. 14-15 "A Buried-Plate Trench Cell for a 64-mb DRAM" , no month 1992.|
|6||*||New Well Structure For Deep Sun m CMOS/BiCMOS Using Thin Epitaxy Over Buried Layer and Trench Isolation ; Y. Okazaki et al.; NTT LSI Laboratories; 1990 Symposium on VLSI Technology; 1990 IEEE; pp. 83 84, (no month).|
|7||S. Wolf "Silicon Processing for the VLSI Era" vol. 2, pp. 482-491, 538-551, 604-609, no month 1990.|
|8||S. Wolf et al. "Silicon Processing for the VLSI Era" vol. 1, p. 282, no month 1986.|
|9||*||S. Wolf et al. Silicon Processing for the VLSI Era vol. 1, p. 282, no month 1986.|
|10||*||S. Wolf Silicon Processing for the VLSI Era vol. 2, pp. 482 491, 538 551, 604 609, no month 1990.|
|11||S.A. Abbas, IBM Tech. Discl. Bulletin, 18(10)(1976)3300 "MOSFET memory cell suing junction capacitance" Mar. 1976.|
|12||*||S.A. Abbas, IBM Tech. Discl. Bulletin, 18(10)(1976)3300 MOSFET memory cell suing junction capacitance Mar. 1976.|
|13||*||Wolf, Silicon Processing for the VLSI Era, vol. 2: Process Integration, pp. 482 491, 538 551, 604 609, no month 1990.|
|14||Wolf, Silicon Processing for the VLSI Era, vol. 2: Process Integration, pp. 482-491, 538-551, 604-609, no month 1990.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6180972 *||Jul 15, 1996||Jan 30, 2001||International Business Machines Corp.||Buried, implanted plate for DRAM trench storage capacitors|
|US6551909 *||Jul 31, 2000||Apr 22, 2003||Fuji Electric Co. Ltd.||Semiconductor device with alternating conductivity type layer and method of manufacturing the same|
|US7012289 *||Jan 21, 2003||Mar 14, 2006||Infineon Technologies Ag||Memory cell having a thin insulation collar and memory module|
|US20040032027 *||Jan 21, 2003||Feb 19, 2004||Martin Popp||Memory cell having a thin insulation collar and memory module|
|U.S. Classification||438/243, 438/238, 257/E21.396, 438/171, 438/386|
|International Classification||H01L21/8242, H01L21/334, H01L27/108, H01L21/822, H01L27/04|
|Jun 28, 1996||AS||Assignment|
Owner name: SIEMENS AKTIENGESELLSCHAFT, UNITED KINGDOM
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:008012/0503
Effective date: 19960627
|Jul 31, 2001||CC||Certificate of correction|
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