|Publication number||US5929798 A|
|Application number||US 08/965,450|
|Publication date||Jul 27, 1999|
|Filing date||Nov 6, 1997|
|Priority date||Nov 8, 1996|
|Publication number||08965450, 965450, US 5929798 A, US 5929798A, US-A-5929798, US5929798 A, US5929798A|
|Original Assignee||Lg Semicon Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (11), Classifications (10), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a high speed and low power D/A converter, and in particular to a high speed and low power D/A converter which is capable of accurately outputting an analog value and implementing a high speed operation by reducing noise and errors which occur during a code conversion.
2. Description of the Conventional Art
FIG. 1 illustrates the construction of a conventional 8-bit CMOS D/A converter which includes a column decoder 1 and a row decoder 2 receiving predetermined bit signals among 8-bit input signals, and a cell plate (matrix array) 3 having a plurality of current cells and outputting a predetermined level of current in accordance with the output signals from the column decoder 1 and the row decoder 2.
Here, each current cell is composed of a logic gate and a current source. The current level outputted by each current cell is identical (equally weighted).
The operation of the conventional 8-bit CMOS D/A converter will now be explained with reference to FIG. 1.
First, when 8-bit (B0-B7) digital signals are inputted, the column decoder 1 and the row decoder 2 decode predetermined bit signals among the 8-bit input signals for thus turning on the current sources of the current cells. When the current from the turned-on current sources flows through an externally connected load resistor R, an analog output voltage Vout is outputted in a voltage-dropped form.
Thus, in the case of converting 8-bit signals, it is possible to implement a total of 28 =256 discrete current levels.
When the current cells are equally weighted, namely, when the current cell plate 3 is composed of segmented cells, the current cells of the cell plate 3 are sequentially selected by adjusting the 8-bit input value, and then the current levels flowing from the selected current cells are combined, so that the amount of current outputted is monotonically increased from the 1st level to the 256th level. As a result, whenever one current cell is turned on, the currents from the current source are combined, so that it is possible to obtain an analog signal level which ranges from 1 to 256 steps.
When the current cells are differently weighted, namely, the current cells are weighted in steps of 1, 2, 4, 8, 16, . . . , n, the current cells are not sequentially turned on. Namely, the appropriately weighted current cells are selected for thus implementing a corresponding level.
Namely, in order to implement an analog level of 32, only the current cells corresponding to analog output level of 32 are turned on, and the other current cells are all turned off, for thus implementing an appropriate level output.
The conventional D/A converters have various problems, among is in providing a monotonic characteristic, namely, that as the digital value is increased, the analog value must correspondingly steadily increase.
In other words, the monotonic characteristic means that as a digital information value is gradually increased, the analog value is gradually increased without any decrease or nonlinearity. Therefore, when the DIA converter is used in a display system such as a digital television or a high definition television, the monotonic characteristic is a very important factor. In order to obtain a good monotonic characteristic, a desired linear characteristic must be obtained when converting digital signals into analog signals.
When configuring the current cells of the cell plate 3 using segmented cells, since the current cells are turned on one by one in order to obtain a predetermined analog level, it is possible to obtain a monotonic characteristic. However, the configuration and coding operation of the current cells become complicated, the power consumption is increased, and the conversion speed of the circuit is decreased.
In addition, when configuring the current cells of the cell plate 3 using weighted cells, the coding operation and cell configuration are more easily implemented. However, it is difficult to obtain a desired monotonic characteristic.
Therefore, the segmented cells and the weighted cells are used together in order to overcome the above-described problems. In this case, as the number of bits of the D/A converter is increased, the role of the weighted cells is increased. Therefore, it becomes still difficult to obtain a desired monotonic characteristic.
The second problem is in that much noise may be generated during code conversion.
When a digital value is increased by one binary digit, for example, the binary value to be converted changes from 01111111 into 10000000, as the binary value is changed from 0 to 1 or from 1 to 0 at each digit position, a discontinuity problem occurs due to noise which is generated during a short time.
Furthermore, since the D/A converter is operated at about 100 MHz or higher, such noise increases a delay time, which is required until a stable analog signal level is obtained, namely, a settling time, thus limiting the data conversion speed.
Accordingly, it is an object of the present invention to provide a high speed and low power D/A converter which overcomes the aforementioned problems encountered in the conventional art.
It is another object of the present invention to provide an improved high speed and low power D/A converter which is capable of accurately outputting an analog value and implementing a high speed operation by reducing noises and errors during a code conversion.
To achieve the above objects, there is provided a high speed and low power D/A converter which includes an upper cell plate from forming analog voltages of a 126th level to 1 255th level in accordance with decoding of inputted digital data values by a first column decoder and a first row decoder, a lower current cell plate for forming analog voltages of a 0th level to a 125th level in accordance with decoding of the inputted digital data values by a second column decoder and second row decoder, and a multiplexer for selectively outputting the analog voltages from the upper current cell plate or the lower current cell plate in accordance with a binary bit value of a most significant bit (MSB) of the inputted digital data.
Additional advantages, objects and features of the invention will become more apparent from the description which follows.
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
FIG. 1 is a schematic block diagram illustrating a conventional 8-bit D/A converter; and
FIG. 2 is a schematic block diagram illustrating the D/A converter according to the present invention.
FIG. 2 illustrates the D/A converter according to the present invention which includes an upper current cell plate 12 and a lower current cell plate 22 which are independently operated in accordance with the value of input data bit B7 which is the is MSB (Most significant Bit) of the inputted 8-bit data B0-B7.
The upper first plate 21 forms across a resistor R11 analog voltages ranging in level from a 126th level to a 256th level in accordance with the decoding of the inputted digital data B0-B6 values by a column decoder 10 and a row decoder 11, and the lower cell plate 22 forms across a resistor R12 analog voltages ranging in level from 0th level to a 125th level in accordance with the decoding of the inputted digital data B0-B6 by a column decoder 20 and a row decoder 21. A multiplexer 23 selects the voltage outputted by upper current cell plate 10 or the voltage outputted by lower current cell plate 11 in accordance with the value of MSB B7. Here, the other construction details of the D/A converter are configured identically with the conventional converter shown in FIG. 1.
The operation of the 8-bit D/A converter according to the present invention will now be explained.
First, when an 8-bit (B0-B7) digital value is inputted, the voltage developed across resistor R11 by the upper current cell plate 12 or the voltage developed across resistor R12 by the lower current cell plate 22 are selected by the multiplexer 23 developing upon the bit (B7) value, which is the MSB thereto, namely, 1 or 0.
The column decoders 10 and 20 respectively receive binary bit values B4, B6, and the row decoders 11 and 21 respectively receive binary bit values B0-B3, so that the current sources of the corresponding current cells are turned on. The current from the thusly turned-on current sources flows through the externally connected load resistors R11 and R12, so that respective analog output voltages are obtained as the voltage drops across R11 and R12. As a result, a predetermined voltage level among a 126th level to a 255th level is applied to the multiplexer 23 from the upper current cell plate 12 via resistor R11, and a predetermined voltage level among a 0th level to a 125th level is applied to the multiplexer 23 from the lower current cell plate 22 via resistor R12.
At this time, assuming the inputted bit value B7 is 1, the voltage applied from the upper plate 12 is selected and outputted by the multiplexer 23, and when the inputted bit value B7 is 0, the voltage applied from the lower plate 22 is selected and outputted.
For example, when configuring an 8-bit D/A converter of Vcc=5V, since the bit B7, which is the MSB, among the binary input bits of B7-B0 selects the voltage outputted from the upper cell plate 12 or from the lower cell plate 22, each cell plate needs implement only 126 discrete current levels, so that the number of weighted cells may be reduced by half.
As a result, in the present invention, since it is possible to reduce the number of the weighted cells, the error rate may be reduced by half. In addition, since the MSB which is most weighted is implemented by the coding value (0 or 1), it is possible to reduce noise during the conversion. Furthermore, because the number of current source cells which are used for generating high level analog signals is reduced by half, the power consumption is significantly reduced.
In more detail, if a 16-bit weighted cell is used in the conventional art, in the present invention, since an 8-bit weighted cell is used, it is possible to reduce an error rate by half in view of obtaining the monotonic characteristic.
In addition, since the MSB (B7) is used only as a control signal for the multiplexer 23, namely, the MSB (B7) is not used for controlling the weighted cells, the signal bits actually converted range from 0111111 to 1000000, which is a 7-bit signal form, so that it is possible to reduce the noise by half and the operational speed is increased compared to the conventional art.
As described above, in the present invention, the current cell plate of the conventional art is divided into an upper current cell plate for forming analog voltages of a 126th level to a 255th level and a lower current cell plate for forming analog voltages of a 0th level to 125th level. Therefore, since the output signal from each current cell plate is selected using the MSB, the number of weighted cells necessarily is decreased by half, so that it is possible to significantly reduce the error occurrence rate, noise and power consumption.
Although the preferred embodiment of the present invention has been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as recited in the accompanying claims.
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|U.S. Classification||341/153, 341/141|
|International Classification||H03M1/74, H03M1/68, H03M1/66, H03M1/00|
|Cooperative Classification||H03M1/685, H03M1/662, H03M1/747|
|Nov 6, 1997||AS||Assignment|
Owner name: LG SEMICON CO., LTD, KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BAEK, DAEBONG;REEL/FRAME:008817/0930
Effective date: 19971103
|Dec 18, 2002||FPAY||Fee payment|
Year of fee payment: 4
|Oct 12, 2004||AS||Assignment|
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF
Free format text: CHANGE OF NAME;ASSIGNOR:LG SEMICON CO., LTD.;REEL/FRAME:015246/0634
Effective date: 19990726
|Jan 10, 2005||AS||Assignment|
Owner name: MAGNACHIP SEMICONDUCTOR, LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYNIX SEMICONDUCTOR, INC.;REEL/FRAME:016216/0649
Effective date: 20041004
|Mar 25, 2005||AS||Assignment|
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUS
Free format text: SECURITY INTEREST;ASSIGNOR:MAGNACHIP SEMICONDUCTOR, LTD.;REEL/FRAME:016470/0530
Effective date: 20041223
|Feb 14, 2007||REMI||Maintenance fee reminder mailed|
|Jul 27, 2007||LAPS||Lapse for failure to pay maintenance fees|
|Sep 18, 2007||FP||Expired due to failure to pay maintenance fee|
Effective date: 20070727