Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS5930631 A
Publication typeGrant
Application numberUS 08/873,995
Publication dateJul 27, 1999
Filing dateJun 12, 1997
Priority dateJul 19, 1996
Fee statusLapsed
Publication number08873995, 873995, US 5930631 A, US 5930631A, US-A-5930631, US5930631 A, US5930631A
InventorsChih-Hsien Wang, Min-Liang Chen, Thomas Chang
Original AssigneeMosel Vitelic Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of making double-poly MONOS flash EEPROM cell
US 5930631 A
Abstract
The present invention discloses a double poly metal oxide/nitride/oxide semiconductor electrically erasable programmable read only memory (EEPROM) for use in semiconductor memories. The EEPROM structure includes a select gate, an oxide\nitride\oxide layer, and a control gate. The control gate is formed on the oxide\nitride\oxide layer. A lightly doped drain (LDD) structure is formed adjacent to the drain and underneath the control gate.
Images(3)
Previous page
Next page
Claims(4)
The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A method of fabricating a double-poly MONOS EEPROM on a semiconductor substrate, said method comprising the steps of:
forming a first silicon dioxide layer on said semiconductor substrate;
forming a first polysilicon layer on said first silicon dioxide layer;
patterning a first photoresist on said first polysilicon layer;
etching said first polysilicon layer and said first silicon dioxide to form a select gate and a gate oxide;
forming a second silicon dioxide layer on said select gate and said substrate;
etching said second silicon dioxide layer to form a side wall spacer adjacent to said gate oxide and select gate;
forming a lightly doped drain by using ion implantation;
removing said side wall spacer;
forming a dielectric layer on said select gate and said substrate;
forming a second polysilicon layer on said dielectric layer;
patterning a second photoresist on said second polysilicon layer;
etching said second polysilicon layer and said dielectric layer such that said dielectric layer and said second polysilicon layer extends from said lightly doped drain to a portion of said select gate; and
forming a heavily doped source and drain using ion implantation to form said MONOS EEPROM.
2. The method of claim 1, wherein said dielectric layer is composed of oxide\nitride\oxide layer.
3. The method of claim 2, wherein said oxide\nitride\oxide layer has a thickness of a range of 200-300 angstroms.
4. The method of claim 2, wherein said second polysilicon layer is used to form a control gate.
Description

This is a divisional of the prior application Ser. No. 08/684,517, filed Jul. 19, 1996, now U.S. Pat. No. 5,703,388 the benefit of the filing date of which is hereby claimed under 35 U.S.C. §120.

FIELD OF THE INVENTION

The present invention relates to an electrically erasable programmable read only memory (EEPROM), and more particularly, to a double-poly MONOS flash EEPROM cell.

BACKGROUND OF THE INVENTION

The electrically erasable programmable read only memory (EEPROM) market has divided for historical reasons into four fairly distinct product segments. These include the EAROM, EEPROM, EEPROM-EAROMs and non-volatile SRAMs. Different types of devices have been developed for specific applications requirements in each of these segments. The low density (below 8 k) EAROMs have been used in such applications as consumer radio tuners, automotive engine controllers, etc. Medium density EEPROMs have been required by microprocessor based applications such as distributed systems or changeable program store. These parts have been developed with a focus on the high endurance and high speed requirements.

The four basic technologies used to manufacture electrically reprogrammable ROMs all utilize to some extent Fowler-Nordheim tunneling which is cold electron tunneling through the energy barrier at a silicon-silicon dioxide interface and into the oxide conduction band. The earliest electrically reprogrammable ROM process in the early 1970s utilized a metal-nitride-oxide silicon combination (MNOS) for the gate region of a P-channel storage cell producing devices called EAROMs (electrically alterable ROMs). The thin silicon dioxide layer allows charges to tunnel through when a voltage is applied to the gate. These charges are trapped in the silicon dioxide to silicon nitride interface and remain trapped there since the materials are high quality insulators. A double polysilicon process is used in a cell consisting of a MNOS transistor and a select transistor.

For programming, a negative voltage is applied to the source and drain while the substrate and gate are grounded. The potential at the central portion of the channel became almost the same as that of the drain and source so that tunneling electrons move from the silicon to the nitride through the thin oxide layer and the electrons are trapped in the nitride. This made the threshold of the MNOS transistor shift in the positive direction so that it conducted more difficult. In the mode of erasing, electrons are emitted from the traps in the nitride by applying a negative voltage to the gate electrode while the source and the drain are grounded.

SUMMARY OF THE INVENTION

A double-poly MONOS EEPROM formed on a semiconductor substrate is disclosed. The EEPROM comprises a source formed in said substrate, a drain formed in said substrate, a gate oxide layer formed on said semiconductor substrate adjacent to said source and spaced apart from said drain by a spacing width, a select gate formed on said gate oxide layer, a dielectric layer formed on a portion of said select gate, a portion of said drain, and said spacing width, said dielectric layer used to store electrons, and a control gate formed on said dielectric layer, said control gate used to control the mode of said EEPROM.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a cross section view of a semiconductor wafer illustrating the structure of an EEPROM formed in accordance with the present invention;

FIG. 2 is a cross section view of a semiconductor wafer illustrating the formation of a select gate and gate oxide;

FIG. 3 is a cross section view of a semiconductor wafer illustrating the formation of a silicondioxide layer on the select gate and on the substrate;

FIG. 4 is a cross section view of a semiconductor wafer illustrating the step of forming a lightly doped drain;

FIG. 5 is a cross section view of a semiconductor wafer illustrating the step of forming a oxide\nitride\oxide layer and polysilicon layer on the select gate substrate;

FIG. 6 is a cross section view of a semiconductor wafer illustrating the step of forming a control gate; and

FIG. 7 is a cross section view of a semiconductor wafer illustrating the step of forming a heavily doped source and drain.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A double-poly MONOS (metal oxide\nitride\oxide semiconductor) flash electrically erasable programmable read only memory (EEPROM) is disclosed. As seen in FIG. 1, the EEPROM device comprises source and drain regions (denoted by n+) that are formed in the substrate of a semiconductor wafer 1. A lightly doped drain (LDD) structure 11 is formed adjacent to the drain for the purpose of reducing hot carriers near the drain junction. A silicon dioxide layer 5 is formed between the source and the lightly doped drain 11. Because silicon dioxide layer 5 serves as a gate oxide 5, it will be referred to as such.

A polysilicon select gate 7 is formed on the silicon dioxide layer 5 by the deposition of polysilicon. The length of the select gate 7 is shorter than the length of the channel between the source and the lightly doped drain 11, and therefore, the select gate 7 does not abut against lightly doped drain 11. A triple composition layer 13 is then formed on the select gate 7 and the source, lightly doped drain 11, and drain. The composition layer 13 is composed of oxide\nitride\oxide (O\N\O). By conventional masking and etching, the O\N\O layer 13 is made to extend over a portion of the select gate 7, the uncovered portion of the channel, and the lightly doped drain 11. A control gate 15 of polysilicon is then formed on the O\N\O layer 13.

In the programming mode, hot carriers tunnel from the channel to the O\N\O layer 13 and are trapped in the O\N\O layer 13. In order to accomplish this, the control gate, the select gate and the drain are positively biased while the source is ground.

In the erase mode, carriers tunnel from the O\N\O layer to the drain. In the erasure mode the drain is at the high voltage while the select gate is off so that there are no electrons flowing into the channel from the source. The select gate serves to conserve power because the device is erased without causing current to flow through the channel of the device. In addition, the cell of the present invention is better suited to military applications, because it is hardened against radiation. The cell also can operate with a relatively thick tunneling oxide. This provides greater data retention. Further, the cell requires relatively low voltage operation.

The formation of the double poly electrically erasable programmable read only memory (EEPROM) described herein includes many process steps that are well known in the art. For example, the process of photolithography masking and etching is used extensively herein. This process consists of creating a photolithography mask containing the pattern of the component to be formed, coating the wafer with a light sensitive material known as a photoresist, exposing the photoresist coated wafer to ultra-violet light through the mask to soften or harden parts of the photoresist (depending on whether positive or negative photoresist is used), removing the softened parts of the photoresist, etching to remove the materials left unprotected by the photoresist and stripping the remaining photoresist. This photolithography masking and etching process is referred to as "patterning and etching."

As will be seen below, this technique can be used to form a double-poly MONOS EEPROM of the present invention. Referring to FIG. 2, in the preferred embodiment, a silicon wafer is provided that is a single crystal substrate 1. The single crystal substrate 1 is P-type with a <100> crystallographic orientation.

First, a thick field oxide region (FOX) 3 is created for purposes of isolation. The FOX 3 region is created via photolithography and dry etching steps to etch a silicon nitride-silicon dioxide composite layer. After the photoresist is removed, and wet cleaned, a thermal oxidation in an oxygen steam ambient is used to form the FOX 3 region, at a thickness about 4000-6000 angstroms.

Next, a first silicon dioxide layer 5 is formed on the substrate 1 to act as the gate oxide 5. The first silicon dioxide layer is formed by using an oxygen-steam ambient, at a temperature between about 850 to 1000° C., to a thickness about 140 angstroms.

Next, a first polysilicon layer 7 is formed over the first silicon dioxide layer 5, silicon substrate 1, and field oxide regions 3. Next, a patterning and etching step is used to etch the first polysilicon layer and first silicon dioxide layer to form a gate oxide 5 and select gate 7 as shown in FIG. 2. The first polysilicon layer is formed using conventional chemical vapor deposition (CVD). It can be appreciated that other methods of depositing the first polysilicon layer can also be used. The thickness of the first polysilicon layer is optimally 2000 angstroms, and the first polysilicon layer is chosen from doped polysilicon or in-situ doped polysilicon.

Referring next to FIG. 3, a second silicon dioxide layer 9 is formed on the select gate 7, field oxide 3 and on the substrate 1. Then, an anisotropic etching process is performed to etch the second polysilicon layer 9 to form side wall spacers 9 as shown in FIG. 4. In the preferred embodiment, the ion source of the etching is oxygen. Next, an ion implantation is performed to create the lightly doped drain (LDD)) 11. The dosage of the implantation is 2E13. After the lightly doped drain 11 is formed, the side wall spacers 9 are removed by using wet etching.

Now turning to FIG. 5, a dielectric triple composition layer 13 is formed on the select gate 7. The dielectric layer 13 is composed of three separate layers of oxide, nitride, and oxide. The thickness of the O\N\O layer 13 is about 300 angstroms. Subsequently, a second polysilicon layer 15 is formed on the O\N\O layer 13 to a thickness about 200-300 angstroms. The second polysilicon layer 15 is used for forming a control gate and therefore will be referred to as such. Next, a patterning and etching step is used to etch the second polysilicon layer 15 and the O\N\O layer 13 to the structure of FIG. 6. As seen, the control gate 15 and the triple composition layer 13 cover a portion of the select gate, the uncovered portion of the channel, and the lightly doped drain 11.

Next, as seen in FIG. 7, an ion implantation step is applied to form the heavy doped source and drain. In addition, a rapid thermal process is performed to drive the ions into the substrate 1. Thus, an EEPROM as shown in FIG. 1 is formed.

As is understood by a person skilled in the art, the foregoing preferred embodiment of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.

While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4098924 *Oct 19, 1976Jul 4, 1978Westinghouse Electric Corp.Gate fabrication method for mnos memory devices
US4105805 *Dec 29, 1976Aug 8, 1978The United States Of America As Represented By The Secretary Of The ArmyFormation of metal nitride oxide semiconductor (MNOS) by ion implantation of oxygen through a silicon nitride layer
US4964080 *Mar 9, 1990Oct 16, 1990Intel CorporationThree-dimensional memory cell with integral select transistor
US5326999 *Nov 13, 1992Jul 5, 1994Samsung Electronics, Co., Ltd.Non-volatile semiconductor memory device and manufacturing method thereof
US5700728 *Nov 13, 1995Dec 23, 1997United Microelectronics CorporationMethod of forming an MNOS/MONOS by employing large tilt angle ion implantation underneath the field oxide
US5851881 *Oct 6, 1997Dec 22, 1998Taiwan Semiconductor Manufacturing Company, Ltd.Method of making monos flash memory for multi-level logic
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6051456 *Dec 21, 1998Apr 18, 2000Motorola, Inc.Semiconductor component and method of manufacture
US6090670 *Sep 5, 1997Jul 18, 2000Micron Technology, Inc.Highly efficient transistor for fast programming of flash memories
US6096605 *May 12, 1998Aug 1, 2000United Semiconductor Corp.Fabricating method of non-volatile flash memory device
US6168999 *Sep 7, 1999Jan 2, 2001Advanced Micro Devices, Inc.Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain
US6177318 *Oct 18, 1999Jan 23, 2001Halo Lsi Design & Device Technology, Inc.Integration method for sidewall split gate monos transistor
US6248633 *Oct 25, 1999Jun 19, 2001Halo Lsi Design & Device Technology, Inc.Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
US6387757 *Jan 17, 2001May 14, 2002Taiwan Semiconductor Manufacturing Company, LtdSacrificial self aligned spacer layer ion implant mask method for forming a split gate field effect transistor (FET) device
US6492234 *May 12, 1998Dec 10, 2002Stmicroelectronics S.R.L.Process for the selective formation of salicide on active areas of MOS devices
US6504755 *May 14, 1999Jan 7, 2003Hitachi, Ltd.Semiconductor memory device
US6784476Jan 3, 2002Aug 31, 2004Samsung Electronics Co., Ltd.Semiconductor device having a flash memory cell and fabrication method thereof
US6800901Oct 17, 2002Oct 5, 2004Stmicroelectronics S.R.L.Process for the selective formation of salicide on active areas of MOS devices
US6803276Jul 9, 2003Oct 12, 2004Samsung Electronics Co., Ltd.Semiconductor device having a flash memory cell and fabrication method thereof
US7071061Sep 26, 2005Jul 4, 2006Powerchip Semiconductor Corp.Method for fabricating non-volatile memory
US7179712 *Aug 14, 2003Feb 20, 2007Freescale Semiconductor, Inc.Multibit ROM cell and method therefor
US7285450Dec 21, 2005Oct 23, 2007Powerchip Semiconductor Corp.Method of fabricating non-volatile memory
US7394127Feb 2, 2005Jul 1, 2008Samsung Electronics Co., Ltd.Non-volatile memory device having a charge storage oxide layer and operation thereof
US7445993Dec 21, 2005Nov 4, 2008Powerchip Semiconductor Corp.Method of fabricating non-volatile memory
US7541637 *Aug 8, 2003Jun 2, 2009Infineon Technologies AgNon-volatile semiconductor memory element and corresponding production and operation method
US7687845 *Nov 21, 2007Mar 30, 2010Renesas Technology Corp.Nonvolatile semiconductor storage device having an element formation region and a plurality of element isolation regions and manufacturing method of the same
US7916539Jan 23, 2009Mar 29, 2011Analog Devices, Inc.Differential, level-shifted EEPROM structures
US8216908 *Jun 19, 2008Jul 10, 2012Nxp B.V.Extended drain transistor and method of manufacturing the same
US8877596 *Jun 24, 2010Nov 4, 2014International Business Machines CorporationSemiconductor devices with asymmetric halo implantation and method of manufacture
US9012968Apr 18, 2013Apr 21, 2015Renesas Electronics CorporationSemiconductor non-volatile memory device
US9257554 *Aug 13, 2014Feb 9, 2016Globalfoundries Singapore Pte. Ltd.Split gate embedded memory technology and method of manufacturing thereof
US9299715Apr 13, 2015Mar 29, 2016Renesas Electronics CorporationFabrication method and structure of semiconductor non-volatile memory device
US20050037581 *Aug 14, 2003Feb 17, 2005Hoefler Alexander B.Multibit ROM cell and method therefor
US20050184334 *Feb 2, 2005Aug 25, 2005Kim Ki-ChulNon-volatile memory device having a charge storage oxide layer and operation thereof
US20050224858 *Jul 28, 2004Oct 13, 2005Chih-Wei Hung[non-volatile memory structure and manufacturing method thereof]
US20060039200 *Mar 17, 2005Feb 23, 2006Ching-Sung YangNon-volatile memory cell, fabrication method and operating method thereof
US20060154409 *Sep 26, 2005Jul 13, 2006Saysamone PittikounMethod for fabricating non-volatile memory
US20060175652 *Aug 1, 2005Aug 10, 2006Ching-Sung YangNon-volatile memory and operating method thereof
US20060186481 *Jul 29, 2005Aug 24, 2006Ching-Sung YangNon-volatile memory and manufacturing method and operating method thereof
US20060205154 *May 5, 2006Sep 14, 2006Chih-Wei HungManufacturing method of an non-volatile memory structure
US20060226466 *Aug 8, 2003Oct 12, 2006Franz SchulerNon-volatile semiconductor memory element and corresponding production and operation method
US20060284223 *Jun 19, 2006Dec 21, 2006Dongbu Electronics Co., Ltd.CMOS image sensor and manufacturing method thereof
US20060286749 *Dec 21, 2005Dec 21, 2006Wei-Chung TsengMethod of fabricating non-volatile memory
US20060286752 *Dec 21, 2005Dec 21, 2006Wei-Chung TsengMethod of fabricating non-volatile memory
US20070108503 *Mar 30, 2006May 17, 2007Shi-Hsien ChenNon-volatile memory and manufacturing method and operating method thereof
US20070108504 *Mar 31, 2006May 17, 2007Yung-Chung LeeNon-volatile memory and manufacturing method and operating method thereof
US20080142876 *Nov 21, 2007Jun 19, 2008Tsuyoshi AriganeNonvolatile semiconductor storage device and manufacturing method of the same
US20100181618 *Jun 19, 2008Jul 22, 2010Nxp, B.V.Extended drain transistor and method of manufacturing the same
US20100188902 *Jan 23, 2009Jul 29, 2010Analog Devices, Inc.Differential, level-shifted EEPROM structures
US20120086070 *Dec 16, 2011Apr 12, 2012Digh HisamotoFabrication method and structure of semiconductor non-volatile memory device
CN100468700CAug 16, 2005Mar 11, 2009力晶半导体股份有限公司Method of manufacturing nonvolatile memory
CN100508164CAug 16, 2005Jul 1, 2009力晶半导体股份有限公司Nonvolatile memory unit, manufacturing method, and operation method
DE10203762B4 *Jan 25, 2002Apr 19, 2007Samsung Electronics Co., Ltd., SuwonNichtflüchtiges Halbleiterspeicherbauelement und Verfahren zu seiner Herstellung
Classifications
U.S. Classification438/286, 438/305, 257/E21.21, 257/E29.165, 257/E29.309, 257/E21.423, 438/266
International ClassificationH01L29/792, H01L29/51, H01L21/336, H01L21/28
Cooperative ClassificationH01L29/511, H01L29/66833, H01L29/792, H01L21/28282
European ClassificationH01L29/66M6T6F18, H01L21/28G, H01L29/51B, H01L29/792
Legal Events
DateCodeEventDescription
Nov 14, 2002FPAYFee payment
Year of fee payment: 4
May 24, 2004ASAssignment
Owner name: PROMOS TECHNOLOGIES INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOSEL VITELIC, INC.;REEL/FRAME:015334/0772
Effective date: 20040427
Jan 29, 2007FPAYFee payment
Year of fee payment: 8
Feb 28, 2011REMIMaintenance fee reminder mailed
Apr 11, 2011FPAYFee payment
Year of fee payment: 12
Apr 11, 2011SULPSurcharge for late payment
Year of fee payment: 11
Jul 27, 2011LAPSLapse for failure to pay maintenance fees
Sep 13, 2011FPExpired due to failure to pay maintenance fee
Effective date: 20110727