Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS5933128 A
Publication typeGrant
Application numberUS 08/648,996
Publication dateAug 3, 1999
Filing dateMay 17, 1996
Priority dateMay 17, 1995
Fee statusLapsed
Publication number08648996, 648996, US 5933128 A, US 5933128A, US-A-5933128, US5933128 A, US5933128A
InventorsMasaki Kuribayashi, Osamu Ikeda, Kazunori Katakura, Hironao Kimura, Hidetoshi Tsuzuki
Original AssigneeCanon Kabushiki Kaisha
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Chiral smectic liquid crystal apparatus and driving method therefor
US 5933128 A
Abstract
A liquid crystal apparatus includes (a) a liquid crystal panel including: a pair of substrates having thereon a group of scanning electrodes and a group of data electrodes, respectively, and provided with mutually different alignment characteristics, and a chiral smectic liquid crystal disposed between the substrates so as to form a pixel at each intersection of the scanning electrodes and the data electrodes, and (b) drive means for: sequentially applying a scanning selection signal to the scanning electrodes to select at least one scanning electrode, and applying a data signal having at least three peak values to the data electrodes in synchronism with the scanning selection signal. A DC bias voltage may be applied between the scanning electrodes and the data electrodes, and the polarity of the DC voltage may be switched for each prescribed period. The above system is suitable for obviating or suppressing the "sticking" phenomenon of a chiral smectic liquid crystal.
Images(24)
Previous page
Next page
Claims(84)
What is claimed is:
1. A liquid crystal apparatus comprising:
(a) a liquid crystal panel including: a pair of substrates having thereon a group of scanning electrodes and a group of data electrodes, respectively, and provided with mutually different alignment characteristics, and a chiral smectic liquid crystal disposed between the substrates so as to form a pixel at each intersection of the scanning electrodes and the data electrodes, and
(b) drive means for:
sequentially applying a scanning selection signal to the scanning electrodes to select at least one scanning electrode, and
applying a data signal having at least three mutually different peak values, with reference to a voltage level of a scanning non-selection signal applied to non-selected scanning electrodes, to the data electrodes in synchronism with the scanning selection signal, said data signal having said at least three peak values within a period of applying the scanning selection signal.
2. An apparatus according to claim 1, wherein pixels on a scanning electrode not receiving the scanning selection signal are supplied with an AC voltage caused by the data signal, the AC voltage having a time-average of zero with reference to a voltage level of the scanning electrode not receiving the scanning selection signal.
3. An apparatus according to claim 1, wherein the data signal applied in synchronism with the scanning selection signal has a first phase, a second phase and a third phase having voltages of mutually different peak values, the voltage of the second phase being equal to an average of the voltages of the first and third phases.
4. An apparatus according to claim 1, wherein the data signal applied in synchronism with the scanning selection signal has a first phase, a second phase and a third phase having voltages of mutually different peak values, the voltage of the second phase being equal to an average of the voltages of the first and third phases, the voltage of the second phase providing a voltage exceeding a threshold of the chiral smectic liquid crystal in combination with the scanning selection signal voltage.
5. An apparatus according to claim 4, wherein the second phase has a period of ΔT, and the first and third phases have a total period of ΔT.
6. An apparatus according to claim 5, wherein the first and third phases respectively have a period of ΔT/2.
7. An apparatus according to claim 1, wherein pixels on a scanning electrode not receiving the scanning selection signal are supplied with an AC voltage caused by the data signal;
the data signal applied in synchronism with the scanning signal provides a time-average value which is zero with reference to a difference between the time-average of the AC voltage applied to the pixels on a non-selected scanning line and the voltage level of such a non-selected scanning line;
the data signal applied in synchronism with the scanning selection signal has a first phase, a second phase and a third phase having voltages of mutually different peak values, the voltage of the second phase being equal to an average of the voltages of the first and third phases, the voltage of the second phase providing a voltage exceeding a threshold of the chiral smectic liquid crystal in combination with the scanning selection signal voltage, the second phase having a period of ΔT, and the first and third phases having a total period of ΔT.
8. An apparatus according to claim 7, wherein said difference is zero.
9. An apparatus according to claim 7, wherein said difference makes a DC component.
10. An apparatus according to claim 7, wherein the first and third phases respectively have a period of ΔT/2.
11. An apparatus according to claim 10, wherein said difference is zero.
12. An apparatus according to claim 10, wherein said difference makes a DC component.
13. An apparatus according to claim 1, wherein only one of said pair of substrates is provided with a uniaxial alignment characteristic and the other substrate is provided with a non-uniaxial alignment characteristic.
14. An apparatus according to claim 13, wherein said non-uniaxial alignment characteristic is a random alignment characteristic.
15. An apparatus according to claim 1, wherein said pair of substrates have alignment control films thereon composed of different film materials and respectively having a uniaxial alignment characteristic.
16. An apparatus according to claim 15, wherein one of the alignment control films comprises an organic film, and the other comprises an inorganic film.
17. An apparatus according to claim 1, wherein said chiral smectic liquid crystal is a liquid crystal developing a ferroelectric state.
18. An apparatus according to claim 1, wherein said chiral smectic liquid crystal is a liquid crystal developing both a ferroelectric state and an anti-ferroelectric state.
19. An apparatus according to claim 1, wherein said chiral smectic liquid crystal comprises at least one liquid crystal component having a fluorinated carbon terminal group including least one completely fluorinated carbon atom.
20. An apparatus according to claim 19, wherein said fluorinated carbon terminal group has 2-15 carbon atoms.
21. An apparatus according to claim 1, wherein said chiral smectic liquid crystal includes a temperature region where smectic A phase is developed from isotropic phase on temperature decease, and said chiral smectic liquid crystal comprises at least one liquid crystal component having a fluorinated carbon terminal group including least one completely fluorinated carbon atom.
22. An apparatus according to claim 21, wherein said fluorinated carbon terminal group has 2-15 carbon atoms.
23. A liquid crystal apparatus comprising:
(a) a liquid crystal panel including: a pair of substrates having thereon a group of scanning electrodes and a group of data electrodes, respectively, and provided with mutually different alignment characteristics, and a chiral smectic liquid crystal disposed between the substrates so as to form a pixel at each intersection of the scanning electrodes and the data electrodes, and
(b) drive means for:
sequentially applying a scanning selection signal to the scanning electrodes to select at least one scanning electrode, said scanning selection signal comprising voltages of at least a first phase and a second phase having mutually different peak values, and
applying a data signal having at least three mutually different peak values, with reference to a voltage level of a scanning non-selection signal applied to non-selected scanning electrodes, to the data electrodes in synchronism with the scanning selection signal, said data signal having said at least three peak values within a period of applying the scanning selection signal,
so that in the first phase, the pixels on the selected scanning electrode are supplied with a voltage exceeding one threshold of the chiral smectic liquid crystal to be non-selectively reset to a cleared state and, in the second phase, a selected pixel, among the cleared pixels is supplied with a voltage exceeding another threshold of the chiral smectic liquid crystal to be written into a display state.
24. An apparatus according to claim 23, wherein said data signal has a voltage waveform including a first phase, a second phase and a third phase having mutually different peak values, and the second phase of the data signal is synchronized with the second phase of the scanning selection signal.
25. An apparatus according to claim 23, wherein pixels on a scanning electrode not receiving the scanning selection signal are supplied with an AC voltage caused by the data signal, the AC voltage having a time-average of zero with reference to a voltage level of the scanning electrode not receiving the scanning selection signal.
26. An apparatus according to claim 23, wherein the data signal applied in synchronism with the scanning selection signal has a first phase, a second phase and a third phase having voltages of mutually different peak values, the voltage of the second phase being equal to an average of the voltages of the first and third phases.
27. An apparatus according to claim 23, wherein the data signal applied in synchronism with the scanning selection signal has a first phase, a second phase and a third phase having voltages of mutually different peak values, the voltage of the second phase being equal to an average of the voltages of the first and third phases, the voltage of the second phase providing a voltage exceeding a threshold of the chiral smectic liquid crystal in combination with the scanning selection signal voltage.
28. An apparatus according to claim 27, wherein the second phase has a period of ΔT, and the first and third phases have a total period of ΔT.
29. An apparatus according to claim 28, wherein the first and third phases respectively have a period of ΔT/2.
30. An apparatus according to claim 23, wherein pixels on a scanning electrode not receiving the scanning selection signal are supplied with an AC voltage caused by the data signal;
the data signal applied in synchronism with the scanning signal provides a time-average value which is zero with reference to a difference between the time-average of the AC voltage applied to the pixels on a non-selected scanning line and the voltage level of such a non-selected scanning line; and
the data signal applied in synchronism with the scanning selection signal has a first phase, a second phase and a third phase having voltages of mutually different peak values, the voltage of the second phase being equal to an average of the voltages of the first and third phases, the voltage of the second phase providing a voltage exceeding a threshold of the chiral smectic liquid crystal in combination with the scanning selection signal voltage, the second phase having a period of ΔT, and the first and third phases having a total period of ΔT.
31. An apparatus according to claim 30, wherein said difference is zero.
32. An apparatus according to claim 30, wherein said difference makes a DC component.
33. An apparatus according to claim 30, wherein the first and third phases respectively have a period of ΔT/2.
34. An apparatus according to claim 33, wherein said difference is zero.
35. An apparatus according to claim 33, wherein said difference makes a DC component.
36. An apparatus according to claim 23, wherein only one of said pair of substrates is provided with a uniaxial alignment characteristic and the other substrate is provided with a non-uniaxial alignment characteristic.
37. An apparatus according to claim 36, wherein said non-uniaxial alignment characteristic is a random alignment characteristic.
38. An apparatus according to claim 23, wherein said pair of substrates have alignment control films thereon composed of different film materials and respectively having a uniaxial alignment characteristic.
39. An apparatus according to claim 38, wherein one of the alignment control films comprises an organic film, and the other comprises an inorganic film.
40. An apparatus according to claim 23, wherein said chiral smectic liquid crystal is a liquid crystal developing a ferroelectric state.
41. An apparatus according to claim 23, wherein said chiral smectic liquid crystal is a liquid crystal developing both a ferroelectric state and an anti-ferroelectric state.
42. An apparatus according to claim 23, wherein said chiral smectic liquid crystal comprises at least one liquid crystal component having a fluorinated carbon terminal group including least one completely fluorinated carbon atom.
43. An apparatus according to claim 42, wherein said fluorinated carbon terminal group has 2-15 carbon atoms.
44. An apparatus according to claim 23, wherein said chiral smectic liquid crystal includes a temperature region where smectic A phase is developed from isotropic phase on temperature decease, and said chiral smectic liquid crystal comprises at least one liquid crystal component having a fluorinated carbon terminal group including least one completely fluorinated carbon atom.
45. An apparatus according to claim 44, wherein said fluorinated carbon terminal group has 2-15 carbon atoms.
46. An apparatus according to claim 23, wherein said drive means successively applies the scanning selection signals so that at least two consecutive scanning selection signals are partially overlapped with each other and applied to different scanning electrodes.
47. A liquid crystal apparatus comprising:
(a) a liquid crystal panel including: a pair of substrates having thereon a group of scanning electrodes and a group of data electrodes, respectively, and provided with mutually different alignment characteristics, and a chiral smectic liquid crystal disposed between the substrates so as to form a pixel at each intersection of the scanning electrodes and the data electrodes, and
(b) drive means including:
means for sequentially applying a scanning selection signal to the scanning electrodes to select at least one scanning electrode, and applying a data signal having at least three phases having mutually different peak values, with reference to a voltage level of a scanning non-selection signal applied to non-selected scanning electrodes, to the data electrodes in synchronism with the scanning selection signal,
means for applying a DC voltage uniformly to the data electrodes, and
means for switching a polarity of the DC voltage for each vertical scanning period or each horizontal scanning period.
48. An apparatus according to claim 47, wherein said data signal has a maximum voltage V0, and the DC voltage has a value in the range of 0.1V0 -5V0.
49. An apparatus according to claim 47, wherein said data signal has a maximum voltage V0, and the DC voltage has a value in the range of 0.5V0 -3V0.
50. An apparatus according to claim 47, wherein the polarity of the DC voltage is switched for each vertical scanning period.
51. An apparatus according to claim 47, wherein the polarity of the DC voltage is switched for each horizontal scanning period.
52. An apparatus according to claim 47, wherein the data signal has a first phase, a second phase and a third phase, the second phase has a period of ΔT, and the first and third phases respectively have a period of ΔT/2.
53. An apparatus according to claim 47, wherein pixels on a scanning electrode not receiving the scanning selection signal are supplied with an AC voltage caused by the data signal, the AC voltage having a time-average value equal to the value of the DC voltage.
54. An apparatus according to claim 47, wherein only one of said pair of substrates is provided with a uniaxial alignment characteristic and the other substrate is provided with a non-uniaxial alignment characteristic.
55. An apparatus according to claim 54, wherein said non-uniaxial alignment characteristic is a random alignment characteristic.
56. An apparatus according to claim 47, wherein said pair of substrates have alignment control films thereon composed of different film materials and respectively having a uniaxial alignment characteristic.
57. An apparatus according to claim 56, wherein one of the alignment control films comprises an organic film, and the other comprises an inorganic film.
58. An apparatus according to claim 47, wherein said chiral smectic liquid crystal is a liquid crystal developing a ferroelectric state.
59. An apparatus according to claim 47, wherein said chiral smectic liquid crystal is a liquid crystal developing both a ferroelectric state and an anti-ferroelectric state.
60. An apparatus according to claim 47, wherein said chiral smectic liquid crystal comprises at least one liquid crystal component having a fluorinated carbon terminal group including least one completely fluorinated carbon atom.
61. An apparatus according to claim 60, wherein said fluorinated carbon terminal group has 2-15 carbon atoms.
62. An apparatus according to claim 47, wherein said chiral smectic liquid crystal includes a temperature region where smectic A phase is developed from isotropic phase on temperature decease, and said chiral smectic liquid crystal comprises at least one liquid crystal component having a fluorinated carbon terminal group including least one completely fluorinated carbon atom.
63. An apparatus according to claim 62, wherein said fluorinated carbon terminal group has 2-15 carbon atoms.
64. A liquid crystal apparatus comprising:
(a) a liquid crystal panel including: a pair of substrates having thereon a group of scanning electrodes and a group of data electrodes, respectively, and provided with mutually different alignment characteristics, and a chiral smectic liquid crystal disposed between the substrates so as to form a pixel at each intersection of the scanning electrodes and the data electrodes, and
(b) drive means including:
means for sequentially applying a scanning selection signal to the scanning electrodes to select at least one scanning electrode, said scanning selection signal comprising voltages of at least a first phase and a second phase having mutually different peak values, and applying a data signal having at least three phases having mutually different peak values, with reference to a voltage level of a scanning non-selection signal applied to non-selected scanning electrodes, to the data electrodes in synchronism with the scanning selection signal,
so that in the first phase, the pixels on the selected scanning electrode are non-selectively reset to a cleared state and, in the second phase, a selected pixel among the cleared pixels is supplied with a voltage exceeding another threshold of the chiral smectic liquid crystal to be written into a display state;
means for applying a DC voltage uniformly to the data electrodes; and
means for switching a polarity of the DC voltage for each vertical scanning period or each horizontal scanning period.
65. An apparatus according to claim 64, wherein said data signal has a voltage waveform including a first phase, a second phase and a third phase having mutually different peak values, and the second phase of the data signal is synchronized with the second phase of the scanning selection signal.
66. An apparatus according to claim 64, wherein said drive means successively applies the scanning selection signals so that at least two consecutive scanning selection signals are partially overlapped with each other and applied to different scanning electrodes.
67. An apparatus according to claim 64, wherein said DC voltage is applied to scanning electrodes not supplied with the scanning selection signal.
68. An apparatus according to claim 64, wherein said DC voltage is applied uniformly to the data electrodes.
69. An apparatus according to claim 64, wherein said data signal has a maximum voltage V0, and the DC voltage has a value in the range of 0.1V0 -5V0.
70. An apparatus according to claim 64, wherein said data signal has a maximum voltage V0, and the DC voltage has a value in the range of 0.5V0 -3V0.
71. An apparatus according to claim 64, wherein the polarity of the DC voltage is switched for each vertical scanning period.
72. An apparatus according to claim 64, wherein the polarity of the DC voltage is switched for each horizontal scanning period.
73. An apparatus according to claim 64, wherein the data signal has a first phase, a second phase and a third phase, the second phase has a period of ΔT, and the first and third phases respectively have a period of ΔT/2.
74. An apparatus according to claim 64, wherein pixels on a scanning electrode not receiving the scanning selection signal are supplied with an AC voltage caused by the data signal, the AC voltage having a time-average value equal to the value of the DC voltage.
75. An apparatus according to claim 64, wherein only one of said pair of substrates is provided with a uniaxial alignment characteristic and the other substrate is a non-uniaxial alignment characteristic.
76. An apparatus according to claim 75, wherein said non-uniaxial alignment characteristic is a random alignment characteristic.
77. An apparatus according to claim 64, wherein said pair of substrates have alignment control films thereon composed of different film materials and respectively having a uniaxial alignment characteristic.
78. An apparatus according to claim 77, wherein one of the alignment control films comprises an organic film, and the other comprises an inorganic film.
79. An apparatus according to claim 64, wherein said chiral smectic liquid crystal is a liquid crystal developing a ferroelectric state.
80. An apparatus according to claim 64, wherein said chiral smectic liquid crystal is a liquid crystal developing both a ferroelectric state and an anti-ferroelectric state.
81. An apparatus according to claim 64, wherein said chiral smectic liquid crystal comprises at least one liquid crystal component having a fluorinated carbon terminal group including least one completely fluorinated carbon atom.
82. An apparatus according to claim 81, wherein said fluorinated carbon terminal group has 2-15 carbon atoms.
83. An apparatus according to claim 64, wherein said chiral smectic liquid crystal includes a temperature region where smectic A phase is developed from isotropic phase on temperature decease, and said chiral smectic liquid crystal comprises at least one liquid crystal component having a fluorinated carbon terminal group including least one completely fluorinated carbon atom.
84. An apparatus according to claim 83, wherein said fluorinated carbon terminal group has 2-15 carbon atoms.
Description
FIELD OF THE INVENTION AND RELATED ART

The present invention relates to a liquid crystal apparatus including a liquid crystal panel using a chiral smectic liquid crystal exhibiting a ferroelectric state or both a ferroelectric state and an anti-ferroelectric state, and a matrix drive means therefor.

A liquid crystal device using a chiral smectic liquid crystal in a chevron structure as disclosed in U.S. Pat. Nos. 4,900,132 or 4,997,264 has required a high-luminance light source in order to provide a display of a sufficient brightness because it is difficult to set a large tilt angle. U.S. Pat. No. 5,377,033, etc., have disclosed a device using a chiral smectic liquid crystal in a bookshelf structure capable of exhibiting a large tilt angle. The chiral smectic liquid crystal exhibiting a bookshelf structure does not exhibit cholesteric phase in the course of cooling from the isotropic phase but develops smectic A phase directly from the isotropic phase, so that it has been difficult to obtain a uniform alignment state by using the alignment control method for developing the alignment state in the chevron structure. EP-A 637622 has disclosed a chiral smectic liquid crystal panel realizing a bookshelf structure in a uniform alignment state by using a pair of substrates including one subjected to a uniaxial aligning treatment such as rubbing or oblique vapor deposition and the other substrate subjected to a random aligning treatment not providing a uniaxial alignment characteristic.

Further, it also has been reported that a uniform alignment of a chiral smectic liquid crystal exhibiting an anti-ferroelectric state and directly assuming smectic A phase from isotropic phase can be realized by applying a polyimide rubbing alignment technique to only one of a pair of substrates (Keizo ITO; "Switching among Three Stable States of Anti-Ferroelectric Stabilized (AFS) Ferroelectric Liquid Crystal (FLC)", Television Society (in Japanese), Vol. 44, No. 5, pp. 536-543 (1990)). The paper has also reported that a chevron structure is developed under no electric field and a bookshelf structure is developed under voltage application.

It has been found that such a liquid crystal panel using a chiral smectic liquid crystal allowing a high-brightness display is accompanied with a so-called "sticking" phenomenon that, during a display operation according to a matrix drive scheme, the alignment state of the chiral smectic liquid crystal is changed with time so that only one alignment state among a plurality of expected stable alignment states becomes a stable alignment state, because of factors such that an asymmetrical alignment control structure is provided to a pair of substrates and the chiral smectic liquid crystal used has a spontaneous polarization of 10 nC/cm2 or higher.

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide a liquid crystal apparatus capable of alleviating or suppressing the above-mentioned "sticking" phenomenon.

According to the present invention, there is provided a liquid crystal apparatus comprising:

(a) a liquid crystal panel including: a pair of substrates having thereon a group of scanning electrodes and a group of data electrodes, respectively, and provided with mutually different alignment characteristics, and a chiral smectic liquid crystal disposed between the substrates so as to form a pixel at each intersection of the scanning electrodes and the data electrodes, and

(b) drive means for:

sequentially applying a scanning selection signal to the scanning electrodes to select at least one scanning electrode, and

applying a data signal having at least three peak values to the data electrodes in synchronism with the scanning selection signal.

According to another aspect of the present invention, there is provided a liquid crystal apparatus comprising:

(a) a liquid crystal panel including: a pair of substrates having thereon a group of scanning electrodes and a group of data electrodes, respectively, and provided with mutually different alignment characteristics, and a chiral smectic liquid crystal disposed between the substrates so as to form a pixel at each intersection of the scanning electrodes and the data electrodes, and

(b) drive means for:

sequentially applying a scanning selection signal to the scanning electrodes to select at least one scanning electrode, said scanning selection signal comprising voltages of at least a first phase and a second phase having mutually different peak values, and

applying a data signal having at least three peak values to the data electrodes in synchronism with the scanning selection signal,

so that in the first phase, the pixels on the selected scanning electrode are supplied with a voltage exceeding one threshold of the chiral smectic liquid crystal to be non-selectively reset to a cleared state and, in the second phase, a selected pixel among the cleared pixels is supplied with a voltage exceeding another threshold of the chiral smectic liquid crystal to be written into a display state.

In the present invention, the data signal may have a voltage waveform including a first phase, a second phase and a third phase having mutually different peak values, and the second phase of the data signal may be synchronized with a second phase of the scanning selection signal.

In the present invention, the pixels on non-selected scanning electrode may be supplied with an AC voltage caused by the data signals, which AC voltage provides a time-average value of zero with reference to a voltage level of a non-selected scanning electrode.

In the present invention, the data signal applied in synchronism with the scanning selection signal may have voltages of mutually different peak values in the first phase, second phase and third phase, and the second phase voltage may have an average value of the first phase voltage and the third phase voltage.

The second phase voltage provides a voltage exceeding a threshold of the chiral smectic liquid crystal in combination with the scanning selection signal voltage.

The second phase may have a duration of ΔT which is equal to the total duration of the first phase and the third phase. The first and third phases may respectively have a duration of ΔT/2.

The data signal applied in synchronism with the scanning selection signal may provide a time-average voltage which is zero with reference to a difference between the above-mentioned time-average of the AC voltage and the voltage level of a non-selected scanning electrode. The data signal may have voltages of mutually different peak values in the first, second and third phases. The second phase voltage is equal to an average of the first phase and third phase voltages. The second phase may have a duration of ΔT which is equal to the total duration of the first phase and the third phase. The first and third phases may respectively have a duration of ΔT/2.

In the present invention, one of the substrates may be subjected to a uniaxial aligning treatment, and the other substrate may be subjected to a non-uniaxial aligning treatment (e.g., a random aligning treatment). Alternatively, the pair of substrates may comprise mutually different alignment control film, e.g., one of an organic film and the other of an inorganic film, both subjected to a uniaxial aligning treatment.

The chiral smectic liquid crystal may develop a ferroelectric phase or both of a ferroelectric and an anti-ferroelectric phase. The chiral smectic liquid crystal may include at least one liquid crystal component having a fluorinated carbon terminal group of, e.g., 2-15 carbon atoms, of which at least one carbon atom is completely fluorinated.

The drive means may apply scanning selection signals, including at least two successively applied scanning selections partially overlapping each other and applied to different scanning electrodes.

According to a further aspect of the present invention, there is provided a liquid crystal apparatus comprising:

(a) a liquid crystal panel including: a pair of substrates having thereon a group of scanning electrodes and a group of data electrodes, respectively, and provided with mutually different alignment characteristics, and a chiral smectic liquid crystal disposed between the substrates so as to form a pixel at each intersection of the scanning electrodes and the data electrodes, and

(b) drive means including:

means for sequentially applying a scanning selection signal to the scanning electrodes to select at least one scanning electrode, and applying a data signal having at least three peak values to the data electrodes in synchronism with the scanning selection signal,

means for applying a DC voltage between the scanning electrodes and the data electrodes, and

means for switching a polarity of the DC voltage.

According to the present invention, there is further provided a liquid crystal apparatus comprising:

(a) a liquid crystal panel including: a pair of substrates having thereon a group of scanning electrodes and a group of data electrodes, respectively, and provided with mutually different alignment characteristics, and a chiral smectic liquid crystal disposed between the substrates so as to form a pixel at each intersection of the scanning electrodes and the data electrodes, and

(b) drive means including:

means for sequentially applying a scanning selection signal to the scanning electrodes to select at least one scanning electrode, said scanning selection signal comprising voltages of at least a first phase and a second phase having mutually different peak values, and applying a data signal having at least three peak values to the data electrodes in synchronism with the scanning selection signal,

so that in the first phase, the pixels on the selected scanning electrode are supplied with a voltage exceeding one threshold of the chiral smectic liquid crystal to be non-selectively reset to a cleared state and, in the second phase, a selected pixel among the cleared pixels is supplied with a voltage exceeding another threshold of the chiral smectic liquid crystal to be written into a display state;

means for applying a DC voltage between the scanning electrodes and the data electrodes; and

means for switching a polarity of the DC voltage.

The data signal may have a waveform including a first phase, a second phase and a third phase, wherein the first and second phase have an identical first peak value, and the third phase has a second peak value different from the first peak value. The second phase of the data signal may be synchronized with the second phase of the scanning selection signal.

The drive means may apply scanning selection signals, including at least two successively applied scanning selections partially overlapping each other and applied to different scanning electrodes.

The drive means may apply the DC voltage to non-selected scanning electrode not receiving the scanning selection signal. The drive means may apply the DC voltage uniforming to the data electrodes.

The DC voltage may have a value in the range of 0.1V0 -5V0, preferably 0.5V0 -3V0, wherein V0 denotes a maximum voltage of the data signal.

The polarity of the DC voltage may be changed for every vertical scanning period (one-frame scanning period or one-field scanning period).

The data signal may have three phases including a first phase, a second phase and a third phase, wherein the second phase may have a duration of ΔT, and the first and third phases may respectively have a duration of ΔT/2.

The pixels on non-selected scanning electrodes are supplied with an AC voltage due to the data signal applied thereto and the AC voltage provides a time-average identical to the DC voltage value.

In the present invention, one of the substrates may be subjected to a uniaxial aligning treatment, and the other substrate may be subjected to a non-uniaxial aligning treatment (e.g., a random aligning treatment). Alternatively, the pair of substrates may comprise mutually different alignment control films, e.g., one of an organic film and the other of an inorganic film, both subjected to a uniaxial aligning treatment.

The chiral smectic liquid crystal may develop a ferroelectric phase or both of a ferroelectric and an anti-ferroelectric phase. The chiral smectic liquid crystal may include at least one liquid crystal component having a fluorinated carbon terminal group of, e.g., 2-15 carbon atoms, of which at least one carbon atom is completely fluorinated.

The chiral smectic liquid crystal may be one causing a phase transition from isotropic phase to chiral smectic phase in a temperature range on temperature decrease.

These and other objects, features and advantages of the present invention will become more apparent upon a consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a chiral smectic liquid crystal panel used in the invention.

FIG. 2 is a schematic plan view of a matrix electrode structure used in the present invention.

FIG. 3 is a block diagram of an embodiment of the liquid crystal apparatus of the invention.

FIG. 4 is a time chart for image data communication used in the apparatus of FIG. 3.

FIGS. 5A-5D, 7A-7D and 9A-9D are respectively a waveform diagram showing a set of drive signals applied to the electrodes used in the invention.

FIGS. 6A-6D, 8A-8D and 10A-10D are respectively a waveform diagram showing a set of voltage signals applied to the pixels based on the drive signals shown in FIGS. 5A-5D, 7A-7D and 9A-9D, respectively.

FIGS. 11A-11D through 13A-13D are three types of time-serial waveform diagrams obtained by using the drive signals shown in FIGS. 5A-5D.

FIGS. 14A-14D constitute a waveform diagram showing another set of drive signals.

FIGS. 15A-15D is a waveform diagram showing a set of drive voltages applied to the pixels based on the drive signals shown in FIGS. 14A-14D.

FIGS. 16A-16D and 17A-17D are respectively a waveform diagram showing another set of drive signals applied to the electrodes.

FIGS. 18A-18D constitute a waveform diagram showing a set of drive voltages applied to the pixels based on the signals shown in FIGS. 16A-16D or 17A-17D.

FIGS. 19A-19D and 20A-20D are respectively a waveform diagram showing another set of drive signals applied to the electrodes.

FIGS. 21A-21D constitute a waveform diagram showing a set of drive voltages applied to the pixels based on the signals shown in FIGS. 19A-19D or 20A-20D.

FIGS. 22A-22D and 23A-23D are different time-serial waveforms each obtained by using the drive signals shown in FIGS. 16A-16D.

FIGS. 24A-24D and 25A-25D are different time-serial waveforms each obtained by using the drive signals shown in FIGS. 17A-17D.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

As a chiral smectic liquid crystal developing a ferroelectric state in the present invention, it is preferred to use a chiral smectic liquid crystal containing at least one liquid crystal component having a fluorinated carbon terminal group of, e.g., 2-15 carbon atoms, of which at least one carbon atom is completely carbonated. Specific examples of such a chiral smectic liquid crystal may include the following Compositions 1-4 disclosed in U.S. Pat. No. 5,377,033.

Composition 1

76.5% 5-octyl-2-(4-(1,1-dihydroperfluoro-2-(2-butoxyethoxy)ethoxy)phenyl)pyrimidine

4.5% 5-octyl-2-(4-(1,1-dihydroperfluorooctyloxy)phenyl)pyrimidine

4.5% 5-nonyl-2-(4-(1,1-dihydroperfluorooctyloxy)phenyl)pyrimidine

10.0% (S)-4-(2-chloro-4-methylpentanoyloxy)phenyl-4-(1,1-dihydroperfluorobutoxy)benzoate.

The transition temperature upon cooling from the isotropic state (I) to the crystalline state (K) are I-SmA: 73 C., SmA-SmC*: 30 C. and SmC*-K: ←10 C.

Herein SmA denotes smectic A phase, and SmC* denotes chiral smectic C phase.

Composition 2

12.44% 5-hexyl-2-(4-(1,1-dihydroperfluoro-2-(2-butoxyethoxy)ethoxy)phenyl)pyrimidine

20.74% 5-octyl-2-(4-(1,1-dihydroperfluorohexyloxy)phenyl)pyrimidine

20.74% 5-nonyl-2-(4-(1,1-dihydroperfluorohexyloxy)phenyl)pyrimidine

20.74% 5-decyl-2-(4-(1,1-dihydroperfluorohexyloxy)phenyl)pyrimidine

8.30% 5-decyl-2-(4-(1,1-dihydroperfluorobutoxy)phenyl)pyrimidine

7.21% (S)-4-(2-chloro-4-methylpentanoyloxy)phenyl 4-(1,1-dihydroperfluorobutoxy)benzoate

3.25% 2,3-dicyano-4-octyloxyphenyl-4-(1,1-dihydroperflorohexyloxy)benzoate

6.58% 2,3-difluoro-4-octyloxyphenyl 4-(1,1-dihydroperfluorohexyloxy)benzoate.

The transition temperatures upon cooling from the isotropic state (I) to the crystalline state (K) are I-SMA: 78 C., SmA-SmC*: 59 C. and SmC*-K: 12 C.

Composition 3

13.80% 5-hexyl-2-(4-(1,1-dihydroperfluoro-2-(2-butoxyethoxy)ethoxy)phenyl)pyrimidine

23.00% 5-octyl-2-(4-(1,1-dihydroperfluorohexyloxy)phenyl)pyrimidine

23.00% 5-nonyl-2-(4-(1,1-dihydroperfluorohexyloxy)phenyl)pyrimidine

9.20% 5-decyl-2-(4-(1,1-dihydroperfluorobutoxy)phenyl)pyrimidine

8.00% (S)-4-(2-chloro-4-methylpentanoyloxy)phenyl 4-(1,1-dihydroperfluorobutoxy)benzoate.

The transition temperatures upon cooling from the isotropic state (I) to the crystalline state (K) are I-SmA: 81 C., SmA-SmC*: 54 C. and SmC*-K: 10 C.

Composition 4

90% 5-octyl-2-(4-(1,1-dihydroperfluoro-2-(2-butoxyethoxy)ethoxy)phenyl)pyrimidine

10% 5-octyl-2-(4-((S)-(2-chloro-4-methylpentanoyloxy)phenyl)pyrimidine.

The transition temperatures upon cooling from the isotropic state (I) to the crystalline state (K) are I-SmA: 76 C., SmA-SmC*: 30 C. and SmC*-K: ←10 C.

Specific examples of the chiral smectic liquid crystal developing both a ferroelectric state and an anti-ferroelectric state may include the following compounds of formulae (1)-(10) indicated below together with their phase transition series, wherein K denotes a crystal phase, SmX denotes an unidentified phase, SmA denotes smectic A phase, I denotes isotropic phase, and SmCA *, SmCr* and SmC* denote states in the chiral smectic C phase including SmCA * showing a ferroelectric state under voltage application and an anti-ferroelectric state under no voltage application, SmC* showing a ferroelectric state under no voltage application and SmCr* which is an unidentified phase, respectively, when placed in a non-helical alignment state by suppressing the helical alignment structure inherent to the chiral smectic C phase. ##STR1##

Specific examples of the liquid crystal device utilizing the anti-ferroelectricity may include those disclosed in U.S. Pat. No. 5,046,823, JP-A 6-95624, JP-A 6-202078 and JP-A 6-202082.

FIG. 1 is a schematic sectional view of a liquid crystal panel used in the present invention, including a pair of polarizers 11a and 11b disposed in cross nicols and sandwiching a panel (cell) structure including a pair of transparent substrates 12a and 12b of, e.g., glass, which are disposed to provide a spacing therebetween of, e.g., 1-5 μm, small enough to suppress the formation of a helical structure inherent to a chiral smectic liquid crystal.

The substrates 12a and 12b have thereon two groups of transparent electrodes 13a and 13b, respectively, one group being assigned as scanning electrodes (scanning lines) to which a scanning selection signal and a scanning non-selection signal are serially applied, and the other being assigned as data electrodes (data lines) to which data signals are applied in parallel.

The transparent electrodes 13a and 13b are coated with alignment control films 14a and 14b having mutually different alignment controlling characteristics. In this specific embodiment, only one alignment control film 14a is subjected to a uniaxial aligning treatment, such as rubbing or oblique vapor deposition, alignment control film 14b and the other is free from such a uniaxial alignment characteristic. Examples of the alignment control film 14a may include: aliphatic polyimide films subjected to rubbing disclosed in EP-A 450459, and polyimide films, polyamide films, polyamide-imide films and polyvinyl alcohol films, respectively subjected to rubbing disclosed in U.S. Pat. No. 4,639,089; and examples of the alignment control film 14b may include a laminate film of a sputtered SiO2 film and a calcined film of an organosilane compound as described below disclosed in U.S. Pat. No. 4,622,721, and a film of an insulating inorganic material, such as silicon nitride, silicon carbide, boron nitride, cerium oxide, silicon oxide, or magnesium fluoride, provided with a non-uniaxial alignment characteristic disclosed in U.S. Pat. No. 4,763,995. In the present invention, it is also possible to compose the alignment control film 14a having a uniaxial alignment characteristic and the alignment control film 14b having no uniaxial alignment characteristic of an identical material (e.g., an identical polyimide or an identical polyamide).

______________________________________Specific examples of organosilane compound______________________________________(1)  CH3 --NH--(CH2)3 --Si(OCH3)3(2)  NH2 --(CH2)2 --NH--(CH2)3 --Si(OCH3).sub.3(3)1 #STR2##(4)  NH2 --(CH2)3 --Si(OC2 H5)3(5)  Si(OC2 H5)4, CH3 --Si(OCH3)3(6)  CH3 --(CH2)4 --Si(OC2 H5)3(7)2 #STR3##(8)3 #STR4##(9)4 #STR5##(10) CH3 --(CH2)7 --Si(OCH3)3(11)5 #STR6##(12)6 #STR7##(13)7 #STR8##______________________________________

In a second embodiment of the asymmetric alignment structure, the alignment control films 14a and 14b are composed of different materials but are both subjected to a uniaxial aligning treatment, such as rubbing or oblique vapor deposition. For example, the alignment control film 14a may comprise a rubbed organic film of, e.g., polyimide film or polyamide film, and the alignment control film 14b may comprise a rubbed inorganic film, e.g., a calcined film of an organosilane compound as described above.

Between the alignment control films 14a and 14b, a chiral smectic liquid crystal 15 as described above is disposed. The chiral smectic liquid crystal is prevented from developing its own helical structure due to a boundary effect of the substrates 12a and 12b, and thus formed in a non-helical structure. The chiral smectic liquid crystal may preferably develop two stable alignment states in the case of a liquid crystal developing a ferroelectric state without developing an anti-ferroelectric state in the non-helical structure, and may preferably develop three stable alignment states in the case of a liquid crystal developing both a ferroelectric state and an anti-ferroelectric state. In a liquid crystal panel developing the above-mentioned two stable alignment states, the pair of cross nicol polarizers 11a and 11b are disposed so as to provide an extinction position (darkest state) when the liquid crystal is placed in one of the two stable alignment states. On the other hand, in a liquid crystal panel developing the above-mentioned three stable alignment states, the pair of cross-nicol polarizers 11a and 11b are disposed to provide an extinction position (darkest state) when the liquid crystal is placed in the anti-ferroelectric state and provide a bright state in the ferroelectric state.

FIG. 2 is a plan view of an electrode matrix, composed of scanning electrodes 13a (scanning lines S1, S2, S3, . . . ) and data electrodes 13b (data lines I1, I2, I3, . . . ).

FIG. 3 is a block diagram showing an arrangement of a ferroelectric liquid crystal display apparatus 101, and a graphic controller 102 which is provided in an apparatus body, such as a personal computer, as a display data supply source. FIG. 4 is a time chart for image data communication between the display apparatus 101 and the graphic controller 102 shown in FIG. 3. The display apparatus 101 includes a liquid crystal panel 103 having 1120 scanning electrodes and 1280 data electrodes arranged in a matrix, between which a ferroelectric liquid crystal is sealed up. The scanning electrodes and the data electrodes are connected to a scanning line drive circuit 104 and a data line drive circuit 105, respectively.

Hereinbelow, the operation of the display apparatus is described with reference to FIGS. 3 and 4. The graphic controller 102 supplies scanning line address data for designating a scanning line and image data (PD0-PD3) on the scanning line designated by the address data to a display drive circuit 104/105 (composed of a scanning line drive circuit 104 and a data line drive circuit 105) of the liquid crystal display apparatus 101. In this embodiment, the image data comprising the scanning line address data and the display data are transferred through the same transmission line, so that it is necessary to differentiate the above-mentioned two types of data. For the differentiation, a signal AH/DL is used. The AH/DL signal at a high level means scanning line address data, and the AH/DL signal at a low level means display data.

In the liquid crystal display apparatus 101, the scanning line address data are extracted from transferred image data PD0-PD3 by a drive control circuit 111 and then supplied to the scanning line drive circuit 104 in synchronism with a time for driving a designated scanning line. The scanning line address data are inputted to a decoder 106 in the scanning line drive circuit 104, and a designated scanning line in the display panel 103 is driven by a scanning signal generating circuit 107 with the aid of the decoder 106. On the other hand, the display data are introduced to a shift register 108 in the data line drive circuit 105 and shifted by a unit of 4 pixel data based on a transfer clock signal. When the shift of display data for one horizontal scanning line is completed by the shift register 108, the display data for 1280 pixels are transferred to a line memory disposed in parallel, memorized for a period of one horizontal scanning and are supplied to the respective data lines as display data signals through a data signal generating circuit 110.

Further, in this embodiment, the drive of the display panel 103 in the liquid crystal display apparatus 101 is not synchronized with the generation of the scanning line address data and display data in the graphic controller 102, so that it is necessary to synchronize the apparatus 101 and 102 at the time of image data transfer. A signal SYNC is in charge of the synchronization and is generated in the drive control circuit 111 in the liquid crystal display apparatus 101 at each one horizontal scanning period. The graphic controller 102 always monitors the SYNC signal, and transfers image data when the SYNC signal is at a low level and does not effect transfer after completing transfer of image data for one horizontal scanning line when the SYNC signal is at high level. More specifically, referring to FIG. 2, the graphic controller 102 immediately sets the AH/DL signal at high level and starts transfer of image data for one horizontal scanning line when it detects that the SYNC signal is at low level. The drive control circuit 111 in the liquid crystal display apparatus 101 set to the SYNC signal at high level during the image data transfer period. When the writing in the display panel 103 is completed after a prescribed one horizontal scanning period, the drive controller circuit (FLCD controller) 111 returns the SYNC signal to the low level so that it can receive image data for a subsequent scanning line.

FIGS. 5A-5D show a set of drive signals outputted from the scanning line drive circuit 104 and the data line drive circuit 105 including a scanning selection signal (SS), a scanning non-selection signal (SN), a data signal 1 (IS) and a data signal 2 (IN). The scanning selection signal SS has two polarity voltages of 2V0 and -2V0 with reference to the voltage level of the scanning non-selection signal SN. A former half period of 3ΔT/2 (period of voltage 2V0) of the scanning selection signal is used as a clearing (or reset) period, and a latter half period of ΔT (period of voltage -2V0) is used as a writing period. The scanning selection signal further includes a period of ΔT/2 (period of voltage 2V0) between the clearing period and the writing period, and a last period of ΔT/2 (period of voltage 0) for making an average of the data signals 1 and 2 zero. The data signal 1 includes a former ΔT/2 period (first phase) of voltage -3V0 /2, a latter ΔT/2 period (third phase) of voltage -V0 /2, and a ΔT period (second phase) of voltage V0 so that it provides an average voltage of zero. The data signal 2 has a waveform which is in anti-phase with the data signal 1.

At IS -SS and IN -SS in FIGS. 6A-6D are shown combinations of the scanning selection signal with the data signal 1 and the data signal 2, respectively, in FIGS. 5A-5D. Further, at IS -SN and IN -SN in FIGS. 6A-6D are shown combinations of the scanning non-selection signal with the data signal 1 and the data signal 2, respectively, in FIGS. 5A-5D.

The scanning selection signal may be sequentially applied to the scanning electrodes 13a one at a time (non-interlaced scanning) or with skipping of one or more electrodes (interlaced scanning). Particularly, in the case of repetitive scanning operation, the interlaced scanning mode may preferably be adopted. Further, when a demand for data rewriting on a display picture occurs as by a keyboard input, it is preferred to effect the non-interlaced scanning only for the scanning electrodes constituting the rewriting region in the display picture and effect the interlaced scanning for the scanning electrodes for the remaining non-rewriting region.

Combined signals IS -SS and IN -SS include a period of 3ΔT/2 in which a voltage exceeding one threshold voltage of the chiral smectic liquid crystal is applied, whereby the pixels on the selected scanning line are brought to one orientation state (e.g., one corresponding to a dark state) and the previously written states are cleared (reset) in this period. In the present invention, such a clearing period can also be 2ΔT, 2.5ΔT, 3ΔT or an even longer period. In the period of ΔT/2 subsequent to the clearing period and corresponding to an auxiliary signal application period, the pixels on the selected scanning line are supplied with a voltage of -7V0 /2 or -V0 /2. The auxiliary signal application period is provided in combination with a final auxiliary signal application period of ΔT/2 so that the pixels on non-selected scanning lines receive an AC voltage waveform. The period ΔT between the two auxiliary signal application period is a writing period, in which a voltage 3V0 exceeding another threshold voltage of the chiral smectic liquid crystal is selectively applied to pixels to provide another orientation state (e.g., one corresponding to a bright state) at the selected pixels and a voltage V0 not exceeding the threshold voltage of the chiral smectic liquid crystal is applied to the other non-selected pixels so that the orientation state formed in the clearing period is retained at the non-selected pixels.

FIGS. 7A-7D show another set of drive signals used in another embodiment, which are identical to those shown in FIGS. 5A-5D except for a different second data signal IN. FIGS. 8A-8D show a set of combined signals (voltage signals applied to pixels) based on the drive signals shown in FIGS. 7A-7D.

FIGS. 9A-9D show still another set of drive signals used in another embodiment, which are identical to those shown in FIGS. 5A-5D except that the length of the clearing period is changed to 3ΔT. FIGS. 10A-10D show a set of combined signals (voltage signals applied to pixels) based on the drive signals shown in FIGS. 9A-9D.

FIGS. 11A-11D and 12A-12D are respectively a time-serial waveform showing a succession of the scanning selection signal shown in FIGS. 9A-9D in parallel with some data signals. In the embodiment of FIGS. 12A-12D, a drive at a high frame frequency (e.g., of 15 Hz or higher) becomes possible even when the number of scanning lines is 1000 or larger. In the embodiment of FIGS. 12A-12D, no zero voltage period is used. In each of the embodiments of FIGS. 11A-11D and 12A-12D, the pixels on non-selected scanning lines are supplied with an AC voltage which becomes zero on a time-average.

On the other hand, a liquid crystal panel of the type utilizing a ferroelectric state and an anti-ferroelectric state of a chiral smectic liquid crystal may be driven by setting the voltages in the clearing period and the former auxiliary signal application period respectively to be zero and providing a DC component to the scanning non-selection signal in each of the sets of drive signals shown in FIGS. 5A-5D, 7A-7D and 9A-9D. In this instance, it is desirable to invert the polarities of the DC component and the voltage in the writing period of the scanning selection signal for each frame. A specific example of such drive signals may assume a time-serial waveform as shown in FIGS. 13A-13D by modifying the drive signals shown in FIGS. 9A-9D.

In each of the embodiments of FIGS. 11A-11D, 12A-12D and 13A-13D, the data signal applied in synchronism with the scanning signal provides a time average value which is zero with reference to a difference between the time-average of the AC voltage applied to the pixels on a non-selected scanning line and the voltage level of such a non-selected scanning line. Each data signal has different peak values in the first, second and third phases such that the second phase voltage is identical to the average of the first and third phase voltages. The combination of the second phase voltage and the scanning selection signal voltage provides a voltage exceeding a threshold voltage of the chiral smectic liquid crystal. The second phase period (ΔT) is equal to the total (ΔT) of the first and third phase periods. Further, the above-mentioned difference between the time-average of the AC voltage applied to the pixels on a non-selected scanning line and the voltage level of such a non-selected scanning line, is zero in the embodiments of FIGS. 11A-11D and 12A-12D, and is equal to the DC component (2V0) in the embodiment of FIG. 13.

In the present invention, the time-serial waveforms shown in FIGS. 11A-11D through 13A-13D obtained based on the drive signals shown in FIGS. 9A-9D may be modified by using the drive signals shown in FIGS. 5A-5D or FIGS. 7A-7D.

FIGS. 14A-14D and 15A-15D show two sets of drive signals obtained by modifying the sets of drive signals of FIGS. 5A-5D and 7A-7D, respectively, by using data signals each having three levels of peak values (in terms of absolute value). More specifically, in FIGS. 14A-14D and 15A-15D, a data signal IS has there peak values of V0, -V0 /2 and -30 /2, and a data signal IN has three peak values of V0, V0 /2 and 3V0 /2. Each data signal has a former and a latter auxiliary period each divided into sub-periods of ΔT/4 having different peak values.

In the present invention, the molecular perturbation becomes different at the beginning and the end of one horizontal scanning period in a non-selection period, so that it becomes difficult for a liquid crystal molecule to remain at one orientation state. As a result, even when a chiral smectic liquid crystal having a spontaneous polarization of 10 nC/cm2 or larger is used, the occurrence of "sticking" phenomenon with time in the case of continuous matrix-drive display operation for a long period can be sufficiently alleviated or suppressed.

Next, some embodiments of inverting the polarity of a bias electric field at a prescribed frequency at the time of non-selection will be described. The application of a simple bias electric field at the time of non-selection is disclosed in JP-A 62-28717 and JP-A 62-260125. The simple application of such a bias electric field application technique cannot solve the sticking problem. In the present invention, the direction or polarity of such a bias electric field at a prescribed frequency to solve the sticking problem.

FIGS. 16A-16D, 17A-17D, 18A-18D, 19A-19D and 20A-20D respectively show a set of drive signals outputted from the scanning line drive circuit 104 and the data line drive circuit 105 of the apparatus shown in FIG. 3, including a scanning selection signal SS, a scanning non-selection signal SN, a first data signal IS and a second data signal IN. The scanning selection signal SS has two polarity voltages of 2V0 and -2V0 with reference to the voltage level of the scanning non-selection signal SN.

In the embodiments of FIGS. 16A-16D and 17A-17D, a former half period of 2ΔT (period of voltage 2V0) of the scanning selection signal is used as a clearing (or reset) period, and a latter half period of ΔT (period of voltage -2V0) is used as a writing period in synchronism with a second phase of the data signals IS and IN. The scanning selection signal further includes a period of ΔT/2 (period of voltage 2V0) between the clearing period and the writing period, and a last period of ΔT/2 (period of voltage 0) in synchronism with the first phase and the third phase, respectively, of the data signals IS and IN, which are provided as auxiliary signal application periods.

In the embodiment of FIGS. 16A-16D, a scanning electrode not supplied with a scanning selection signal SS is supplied with a scanning non-selection signal SN comprising a DC voltage VDC of +1.5V0 or -1.5V0. Each of a first period and a second period may be repeated for one frame scanning period or one field scanning period (vertical scanning period), or set to one horizontal scanning period. Correspondingly, the polarity of the DC voltage VDC is switched after continuation for a corresponding period.

In the embodiment of FIGS. 17A-17D, a DC voltage DDC of +1.5V0 or -1.5V0 is uniformly applied to the data electrodes. Also in the embodiment of FIGS. 17A-17D, each of a first period and a second period may be repeated for one frame scanning period or one field scanning period (vertical scanning period), or set to one horizontal scanning period. Correspondingly, the polarity of the DC voltage VDC is switched after continuation for a corresponding period.

In FIGS. 18A-18D, at IS -SS and IN -SS are shown pixel signals (voltage signals applied to pixels) obtained by combinations of the scanning selection signal SS and the data signals IS and IN, respectively, in FIGS. 16A-16D or FIGS. 17A-17D; and at IS -SN and IN -SN are shown pixel signals obtained by combinations of the scanning non-selection signal SN and the data signals IS and IN, respectively, in FIGS. 16A-16D or FIGS. 17A-17D.

The scanning selection signal SS may be sequentially applied to the scanning electrodes 13a one at a time (non-interlaced scanning) or with skipping of one or more electrodes (interlaced scanning). Particularly, in the case of repetitive scanning operation, the interlaced scanning mode may preferably be adopted. Further, when a demand for data rewriting on a display picture occurs as by a keyboard input, it is preferred to effect the non-interlaced scanning only for the scanning electrodes constituting the rewriting region in the display picture and effect the interlaced scanning for the scanning electrodes for the remaining non-rewriting region.

Combined signals IS -SS and IN -SS include a period of 2ΔT in which a voltage exceeding one threshold voltage of the chiral smectic liquid crystal is applied, whereby the pixels on the selected scanning line are brought to one orientation state (e.g., one corresponding to a dark state) and the previously written states are cleared (reset) in this period. In the present invention, such a clearing period can also be 1.5ΔT, 2.5ΔT, 3ΔT or an even longer period. In the period of ΔT/2 subsequent to the clearing period and corresponding to an auxiliary signal application period. The auxiliary signal application period is provided in combination with a final auxiliary signal application period of ΔT/2 so that the pixels on non-selected scanning lines receive an AC voltage waveform. The period ΔT between the two auxiliary signal application period is a writing period, in which a voltage 3V0 exceeding another threshold voltage of the chiral smectic liquid crystal is selectively applied to pixels to provide another orientation state (e.g., one corresponding to a bright state) at the selected pixels and a voltage V0 not exceeding the threshold voltage of the chiral smectic liquid crystal is applied to the other non-selected pixels so that the orientation state formed in the clearing period is retained at the non-selected pixels.

FIGS. 19A-19D and 20A-20D show other sets of drive signals used in other embodiments which are identical to drive signals shown in FIGS. 16A-16D and 17A-17D, respectively, except that the voltage at the final ΔT/2 period was changed from zero to V0. It has been confirmed that such modification is effective for providing a larger drive margin during display drive. FIGS. 21A-21D show a set of pixel signals obtained by using any set of drive signals shown in FIGS. 19A-19D or FIG. 20.

FIGS. 22A-22D and 23A-23D show two types of time-serial drive signal waveform obtained by applying the scanning selection signal shown in FIGS. 16A-16D in different manners (i.e., without and with overlapping of consecutively applied scanning selection signals). According to the embodiment of FIGS. 23A-23D, a drive at a high frame frequency (e.g., 15 Hz or higher) can be realized even if the number of scanning lines exceeds 1000. In the embodiment shown in FIGS. 23A-23D wherein a pair of consecutive scanning selection signals having a partial overlapping with each other are applied to different scanning electrodes, the period of voltage zero is omitted from the data signals. In the embodiments of FIGS. 22A-22D and 23A-23D, a DC voltage of VDC is applied as a scanning non-selection signal, and pixels on scanning electrodes at the time of scanning non-selection receive AC voltages having a time-average value equal to the DC voltage VDC. The polarity of the DC bias voltage VDC is inverted for each frame scanning period.

FIGS. 24A-24D and 25A-25D show two types of time-serial drive signal waveform obtained by applying the scanning selection signal shown in FIG. 17 in different manners (i.e., without and with overlapping of consecutively applied scanning selection signals). According to the embodiment of FIG. 25, a drive at a high frame frequency (e.g., 15 Hz or higher) can be realized even if the number of scanning lines exceeds 1000. In the embodiment shown in FIGS. 25A-25D wherein a pair of consecutive scanning selection signals having a partial overlapping with each other are applied to different scanning electrodes, the period of voltage zero is omitted from the data signals. In the embodiments of FIGS. 24A-24D and 25A-25D, a DC voltage of VDC is applied as a scanning non-selection signal, and pixels on scanning electrodes at the time of scanning non-selection receive AC voltages having a time-average value equal to the DC voltage VDC. The polarity of the DC bias voltage VDC is inverted for each frame scanning period.

As described above, in the present invention, the direction of bias electric field applied to the liquid crystal is inverted for each prescribed period, so that it becomes difficult for liquid crystal molecules to remain in one state. As a result, even if a display operation according to a matrix drive scheme is performed for a long period by using a chiral smectic liquid crystal having a large spontaneous polarization of at least 10 nC/cm2, the "sticking" phenomenon with time can be sufficiently alleviated or suppressed.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4622721 *Dec 3, 1984Nov 18, 1986Rud-Kettenfabrik Rieger & Dietz Gmbh U. Co.Connecting device for components and for tensioning and/or control devices with belts
US4639089 *Jan 14, 1985Jan 27, 1987Canon Kabushiki KaishaLiquid crystal device
US4763995 *Dec 11, 1986Aug 16, 1988Canon Kabushiki KaishaOptical modulation device
US4776676 *Aug 24, 1987Oct 11, 1988Canon Kabushiki KaishaFerroelectric liquid crystal optical modulation device providing gradation by voltage gradient on resistive electrode
US4900132 *Aug 19, 1988Feb 13, 1990Tektronix, Inc.Chiral liquid crystal cell
US4997264 *Dec 1, 1988Mar 5, 1991The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern IrelandFerroelectric liquid crystal devices having a high surface tilt
US5046823 *Mar 24, 1989Sep 10, 1991Nippondenso Co., Ltd.Ferroelectric liquid crystal electro-optic apparatus and manufacturing method thereof
US5136408 *Oct 15, 1991Aug 4, 1992Canon Kabushiki KaishaLiquid crystal apparatus and driving method therefor
US5262082 *Apr 28, 1992Nov 16, 1993Minnesota Mining And Manufacturing CompanyFerroelectric liquid crystal compounds having perfluoroether terminal portions
US5267065 *Dec 30, 1991Nov 30, 1993Canon Kabushiki KaishaLiquid crystal apparatus
US5283564 *Dec 26, 1991Feb 1, 1994Canon Kabushiki KaishaLiquid crystal apparatus with temperature-dependent pulse manipulation
US5321419 *Jun 17, 1992Jun 14, 1994Canon Kabushiki KaishaDisplay apparatus having both refresh-scan and partial-scan
US5353041 *Nov 4, 1991Oct 4, 1994Canon Kabushiki KaishaDriving device and display system
US5377033 *Jan 13, 1994Dec 27, 1994Minnesota Mining And Manufacturing CompanyFerroelectric liquid crystal device with an organosilesquioxane alignment layer and a polyamide or polyester alignment layer
US5469281 *Aug 24, 1993Nov 21, 1995Canon Kabushiki KaishaDriving method for liquid crystal device which is not affected by a threshold characteristic change
US5471229 *Feb 9, 1994Nov 28, 1995Canon Kabushiki KaishaDriving method for liquid crystal device
US5489919 *Dec 28, 1993Feb 6, 1996Asashi Glass Company Ltd.Driving method of driving a liquid crystal display element
US5519411 *Jan 23, 1995May 21, 1996Canon Kabushiki KaishaLiquid crystal display apparatus
US5521727 *Dec 15, 1993May 28, 1996Canon Kabushiki KaishaMethod and apparatus for driving liquid crystal device whereby a single period of data signal is divided into plural pulses of varying pulse width and polarity
US5532713 *Apr 18, 1994Jul 2, 1996Canon Kabushiki KaishaDriving method for liquid crystal device
US5583534 *Feb 16, 1994Dec 10, 1996Canon Kabushiki KaishaMethod and apparatus for driving liquid crystal display having memory effect
US5594571 *Jun 2, 1995Jan 14, 1997Canon Kabushiki KaishaFerroelectric liquid crystal device and process for production thereof
US5602562 *Nov 24, 1993Feb 11, 1997Canon Kabushiki KaishaLiquid crystal apparatus and driving method
US5606343 *Sep 14, 1994Feb 25, 1997Canon Kabushiki KaishaDisplay device
EP0450459A2 *Mar 26, 1991Oct 9, 1991NOELL Abfall- und Energietechnik GmbHMethod and device for the biological purification of contaminated soils
EP0637622A1 *Aug 2, 1994Feb 8, 1995Canon Kabushiki KaishaLiquid crystal device
JPH0695624A * Title not available
JPH06202078A * Title not available
JPH06202082A * Title not available
JPS6228717A * Title not available
JPS62260125A * Title not available
Non-Patent Citations
Reference
1Ito, Keizo, "Switching Among Three Stable States of Anti-Ferroelectric Stabilized (AFS) Ferroelectric Liquid Crystal (FLC)", Television Society (in Japanese), vol. 44, No. 5, pp. 536-543 (1990).
2 *Ito, Keizo, Switching Among Three Stable States of Anti Ferroelectric Stabilized (AFS) Ferroelectric Liquid Crystal (FLC) , Television Society (in Japanese), vol. 44, No. 5, pp. 536 543 (1990).
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6219018 *May 12, 1999Apr 17, 2001Kabushiki Kaisha ToshibaActive matrix type display device
US6535193 *Sep 30, 1999Mar 18, 2003Canon Kabushiki KaishaDisplay apparatus
US6888522 *Mar 29, 2000May 3, 2005Minolta Co., Ltd.Information display apparatus
US8519918 *Dec 22, 2010Aug 27, 2013Gold Charm LimitedImage display apparatus and control method therefor
US20120162190 *Mar 5, 2011Jun 28, 2012Industrial Technology Research InstituteApparatus and method for driving multi-stable display panel
Classifications
U.S. Classification345/95, 349/136, 349/133, 345/97
International ClassificationG09G3/36
Cooperative ClassificationG09G2320/02, G09G2310/061, G09G3/3629, G09G3/3614, G09G2310/06
European ClassificationG09G3/36C6B
Legal Events
DateCodeEventDescription
Sep 25, 2007FPExpired due to failure to pay maintenance fee
Effective date: 20070803
Aug 3, 2007LAPSLapse for failure to pay maintenance fees
Feb 21, 2007REMIMaintenance fee reminder mailed
Apr 29, 2003CCCertificate of correction
Jan 9, 2003FPAYFee payment
Year of fee payment: 4
Jul 19, 1996ASAssignment
Owner name: CANON KABUSHIKI KAISHA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KURIBAYASHI, MASAKI;IKEDA, OSAMU;KATAKURA, KAZUNORI;AND OTHERS;REEL/FRAME:008075/0236
Effective date: 19960715