Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS5966601 A
Publication typeGrant
Application numberUS 08/786,598
Publication dateOct 12, 1999
Filing dateJan 21, 1997
Priority dateJan 21, 1997
Fee statusLapsed
Publication number08786598, 786598, US 5966601 A, US 5966601A, US-A-5966601, US5966601 A, US5966601A
InventorsChen Ling, Siu-han Liao
Original AssigneeHoltek Microelectronics Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of making non-volatile semiconductor memory arrays
US 5966601 A
Abstract
A new structure of a non-volatile semiconductor memory cell array and a method of fabricating the memory arrays. The circuit layout of the memory array not only comprises of the conventional floating gates, control gates, cell sources and cell drains, but also adds the local source regions to increase the coupling ratio. Besides, the new design can reduce the number of metal contact windows, further increase the packing density of the memory array. Furthermore, an additional isolation region is formed between two bit lines so as to increase the distance between two bit lines, which can minimize the possibility of cross talk due to shirking spacing.
Images(11)
Previous page
Next page
Claims(7)
What we claimed is:
1. A method for fabricating a non-volatile semiconductor memory cell, comprising the steps of:
(a) providing a P-type semiconductor substrate;
(b) forming a field oxide region and a tunnel oxide layer on said substrate;
(c) forming a first polysilicon layer on said substrate;
(d) sequentially depositing a first dielectric layer, a metal polycide layer, and a second dielectric layer overlaying said polysilicon layer to form a multi-layered structure;
(e) forming a plurality of stacked gates from said multi-layered structure using lithography and plasma-etching techniques, wherein each stacked gate containing, from top to bottom, said second dielectric layer, said metal polycide layer, said first dielectric layer, and said first polysilicon layer, and said first polysilicon layer becoming a floating gate and said metal polycide layer becoming a control gate;
(f) using said stacked gates as a mask, ion-implanting N-type impurities into a predetermined region of said substrate to form cell sources and cell drains;
(g) growing a cell source/drain oxide layer overlaying entire said substrate;
(h) depositing a thick oxide layer overlaying entire said substrate including said source drain region and covering entire said stacked gates
(i) forming a photoresist to protect the portion of said thick oxide layer which overlays said cell sources as well as cover sidewalls of said stacked gates adjacent to said cell sources;
(j) using an anisotropic etching technique to expose said cell drains and form sidewall spacers from said thick oxide layer adjacent to said cell drains, while leaving said cell sources and the portion of said stacked gates connected to said cell sources protected by a remaining portion of said thick oxide layer;
(k) depositing a conducting layer overlaying entire said substrate, then using lithography and plasma-etching techniques to form local sources and local bitlines from said cell drains in alternating locations, wherein said cell sources are insulated from said local sources and said local bitlines by said thick oxide layer, and said local sources and said local bitlines are formed without the need to specifically form contacts thereto.
2. The method for fabricating a non-volatile semiconductor memory cell according to claim 1 wherein said first polysilicon layer has a thickness between 500 and 2,000 Angstroms.
3. The method for fabricating a non-volatile semiconductor memory cell according to claim 1 wherein said metal polycide layer has a thickness between 1,000 and 3,000 Angstroms.
4. The method for fabricating a non-volatile semiconductor memory cell according to claim 1 wherein said first dielectric layer has an oxide/nitride/oxide structure with an aggregate oxide thickness between 100 and 300 Angstroms.
5. The method for fabricating a non-volatile semiconductor memory cell according to claim 1 wherein said N-type impurities are arsenic ions, which are ion-implanted at an energy level between 20 and 80 keV, and a dose between IE15 and 5E15 cm-2.
6. The method for fabricating a non-volatile semiconductor memory cell according to claim 1 wherein said conducting layer has a thickness between 2,000 and 4,000 Angstroms.
7. The method for fabricating a non-volatile semiconductor memory cell according to claim 1 wherein said conducting layer is formed from a material selected from the group consisting of polysilicon, tungsten, tungsten silicide, and titanium silicide.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method of fabricating non-volatile semiconductor memory devices, and more particularly to a memory device employing local sources having improved coupling ratio.

2. Description of the Prior Art

The trend of recent semiconductor device developing is that high density non-volatile memory has been expected to replace some part of the huge external storage device market of computers, because of its easy to access and low power dissipation.

Please refer now to FIG. 1, there is shown a cross sectional view of the conventional stack non-volatile memory array cell. A tunnel oxide 2 and a first polysilicon 3A layers are grown on a semiconductor substrate 1. The tunnel oxide layer and the first polysilicon layers are patterned by the conventional lithography and plasma-etching techniques to form the floating gates. A first dielectric 4 and a second polysilicon 5A layers are then deposited overlaying the floating gates. The first dielectric layer is typically made of oxide/nitride/oxide (ONO) sandwich structure. Thereafter, the control gates are patterned.

Next, source 6 and drain 7 regions are formed by ion implanting dopants into the semiconductor substrate which is not covered by the gates. A second dielectric layer 8 (usually made of doped oxide) is deposited on the entire substrate surface. Finally, contact windows 9 are opened by lithography and plasma-etching techniques again. The basic structure of a non-volatile memory cell is completed. Referring now to FIG. 2, there is shown the cell layout corresponding to FIG. 1. The areas marked 10 are the isolation regions.

According to the description above, there must be a contact window for every two cells that limits the packing density of the memory array. Besides, the silicon substrate which is not covered by the first polysilicon (S area of FIG. 2) has great possibilities to be undercut during the self-aligned etching process, which increases the resistance of the source lines. Furthermore, the distance between two adjacent metal lines is too close when cell size continuously shirking that creates cross talk problem. All these drawbacks degrade the performance of the non-volatile memory arrays. Therefore, the present invention provides a new design approach which reduces the cell area compared with the conventional cell without suffering the above problems.

SUMMARY OF THE INVENTION

It is the object of the present invention to provide a method of fabricating the non-volatile semiconductor memory array having higher coupling ratio.

It is another object of the present invention is to provide a novel design of the non-volatile semiconductor memory cell which can reduce the cell area and increase the packing density.

It is yet another object of the present invention to provide an easy and manufacturable non-volatile memory cell structure which can cut down the production cost.

It is a further object of the present invention to provide a low operation voltage non-volatile memory array which is portable.

It is still a further object of the present invention to provide an additional isolation region between two adjacent bit lines of the non-volatile memory cell which can improve the reliability of the device.

In accordance to these objects of this invention, a new method of fabricating non-volatile semiconductor memory array with high coupling ratio is achieved. First, a field oxide layer for isolation and a tunnel oxide layer are formed on the surface of the silicon substrate. Then, the active device area and isolation region are defined by the conventional lithography and etching techniques. Next, a first polysilicon layer is deposited, followed by the conventional lithography and plasma etching techniques to form the floating gate pattern. Then, a first dielectric, a metal polycide and a second dielectric layers are sequentially deposited overlaying the floating gate. Thereafter, the control gate pattern is formed by the conventional lithography and plasma etching techniques again. Next, the ion implantation technique is employed to form the cell source and cell drain regions of the non-volatile memory array. A cell source/drain oxide layer is then grown on the silicon substrate surface, followed by the spacer oxide layer deposition. The oxide spacers are formed on the sidewalls of the floating gates by the vertically unisotropically plasma-etching technique. Finally, the local bitline and local source are formed simultaneously that is one of the key points of the present invention. The non-volatile semiconductor memory cell array of the present invention is accomplished.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of this description, there is shown:

FIG. 1 shows a cross-sectional view of the non-volatile memory cell according to the prior art.

FIG. 2 shows the prior art non-volatile memory cell circuit layout corresponding to FIG. 1.

FIG. 3A shows the circuit layout of the non-volatile of the non-volatile memory cell according to the first preferred embodiment of the present invention.

FIG. 3B shows the equivalent circuit diagram corresponding to FIG. 3A.

FIG. 3C shows the circuit layout of the non-volatile memory cell according to the alternating embodiment of the present invention.

FIG. 3D shows the equivalent circuit diagram corresponding to FIG. 3C.

FIG. 3E through 3K schematically show the cross sectional view of the non-volatile memory cell according to the preferred embodiments of the present invention.

FIG. 3L shows the examples of the cell operation conditions obtainable with the preferred embodiments of the present invention.

FIG. 3M shows the Program Erase diagrams and their bias conditions corresponding to FIG. 3L.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now more particularly to FIG. 3A, there is shown the non-volatile memory cell circuit layout of the first preferred embodiment of the present invention. The memory cell comprises of: top select lines 31, selecting the cell address of the memory array; common source line 32; a plural columns and rows of floating gates 33, locating on the surface of a silicon substrate; a plural rows of control gate 34, continuously locating above the floating gates 33; a plural columns of local bitlines 35, locating on the surface of the silicon substrate; a plural columns of cell sources 36 and cell drains 37, alternatively arranging under the local bitlines 35, and the cell sources 36 and cell drains 37 are separated by the control gates 34; a plural rows of local sources 38, alternatively arranging with the cell drains 37 in each row; a plural columns of isolation region 39, isolating the adjacent cell drain 37 and local source 38.

Referring now to FIG. 3B, there is shown the equivalent circuit diagram corresponding to FIG. 3A. The local source lines are connected to the common source line 32 which is controlled by one bottom select 30 only. The symbols of WL(0)iB WL(1)iB . . . iBWL(n-2)iBWL(n-1) are representing the wordlines, while the symbols of Data(0)iB . . . iBData(m-1) are representing the datalines. The horizontal wordlines and the vertical datalines cross each other to form the n by m array structure.

Referring now to FIG. 3C, there is shown the non-volatile memory cell circuit layout of the alternating embodiment of the present invention. The layout is basically the same with the first preferred embodiment of FIG. 3A. The only difference is that each local source line 38 is independently controlled by its own control line.

Referring now to FIG. 3D, there is shown the equivalent circuit diagram corresponding to FIG. 3D. The local source lines are individually controlled by independent control lines of BS(0)iB . . . iBBS(m-1).

Referring to FIGS. 3E through 3L, the preferred embodiments of the present invention will be described in details. In the following description, numerous details are set forth in order to provide a thorough understanding of the present invention. It will be appreciated by one skilled in the art that variations of these specific details are while still achieving the results of the present invention. In other instance, well-known processing steps are not described in detail in order not unnecessarily to obscure the present invention.

Referring now to FIG. 3E, there is shown a cross sectional view of a partially completed silicon substrate which is cut from the word line direction BB of FIG. 3A. The starting material of the present invention is a monocrystalline P-type silicon substrate 41. First, a field oxide layer 42 for isolation and a tunnel oxide layer 46 are formed on the surface of the silicon substrate 41. The field oxide layer 42 may be formed by forming a layer of Silicon Oxide and Silicon Nitride thereon. Thereafter, an active device area and an isolation region are defined by the conventional lithography and etching techniques. The field oxide layer may serve as the isolation region. Because the silicon oxide layer on the silicon nitride grows slowly, a thin silicon oxide layer may be formed after the silicon nitride layer is removed. The active device area comprises of: cell channel; and cell source/drain regions.

The field oxide layer 42 is grown by thermal oxidation method, using steam at a temperature between about 900 to 1200 C., to a thickness of about 3000 to 6500 Angstroms. The tunnel oxide layer 46 is also formed by thermal oxidation, to a thickness of about 50 to 120 Angstroms.

Referring now to FIG. 3F, there is shown a cross sectional view of the silicon substrate also from the word line direction BB. First, a first polysilicon layer 47 is deposited, followed by the conventional lithography and plasma etching techniques to form the floating gate pattern. Then, a first dielectric 49, a metal polycide 51 and a second dielectric 53 layers are sequentially deposited overlaying the floating gate. Thereafter, the control gate pattern is formed by the conventional lithography and plasma etching techniques again.

The first polysilicon layer 47 is usually formed by in-situ phosphorus doped LPCVD method under a mixture of (15%PH3 +85%SiH4) and (5%PH3 +95%N2), the total pressure is about 1 torr, and at the reaction temperature about 550 C. to obtain a thickness of between 500 to 2000 Angstroms. The first polysilicon plasma etching process can use magnetic enhanced reactive ion etching (MERIE), electron cyclotron etching (ECR) or the conventional reactive ion etching (RIE) methods with reactant gases such as Cl2, SF6 and HBr. The first dielectric layer 49 is usually using oxide/nitride/oxide (ONO) triple layer with the equivalent oxide thickness of about 100 to 300 Angstroms. The polycide layer 51 is usually made of metal polycide materials such as tungsten silicide (WSi) or titanium silicide (TiSi) by low pressure chemical vapor deposition (LPCVD) technique to a thickness of about 1000 to 3000 Angstroms. The second dielectric layer is usually made of oxide or nitride by LPCVD technique also to a thickness of about 1000 to 3000 Angstroms.

Next, FIGS. 3G through 3K are the cross sectional views of the silicon substrate from the local bitline direction CC. Referring now to FIG. 3G, the ion implantation technique is employed to form the cell source and cell drain regions of the non-volatile memory array such as flash memory or the electrical programmable read only memory (EPROM) arrays. This is accomplished via ion implantation of arsenic (As75) ions, at an energy of 20 to 80 keV, and a dose between about 1E15 to 5E15 cm-2.

Referring now to FIG. 3H, first, a cell source/drain oxide layer 57 is grown on the silicon substrate surface, followed by the spacer oxide layer 59 deposition. The cell source/drain oxidation step is also severed as dopant drive in step, which is performed at a temperature range of about 900 to 1000 C. for about 30 minutes in a nitrogen ambient environment with less oxygen for the purpose of obtaining the desired junction depth. The spacer oxide layer 59 is usually made of silicon dioxide such as TEOS by the LPCVD or PECVD technique to a thickness of about 2000 to 4000 Angstroms.

Referring now to FIG. 3I, the photoresist pattern 61 is formed by the conventional lithography technique to protect the oxide layer above the cell source 36 region, but unprotect the drain area 37 and source area 38. The oxide spacers 59 are then formed on the sidewalls of the floating gates by the vertically unisotropically plasma-etching technique. The oxide plasma etching process is used the magnetic enhanced reactive ion etching (MERIE) method with reactant gases such as CF4, CHF3 and Ar.

Referring now to FIGS. 3J and 3K, the local bitline and local source line are formed simultaneously that is one of the key points of the present invention. First, a conducting layer 63 which has a thickness of about 2000 to 4000 Angstroms is deposited over the entire silicon substrate. Then, the local bitline and local source line patterns are formed by the conventional lithography and plasma etching techniques. The conducting layer is usually made of low resistivity materials such as polysilicon, tungsten, tungsten silicide (WSi) or titanium silicide (TiSi). FIG. 3J is the cross sectional view of the silicon substrate from the local bitline 35 of FIG. 3A, while FIG. 3K is the cross sectional view of the silicon substrate from the local source line 32 of FIG. 3A. The non-volatile semiconductor memory cell array of the present invention is completed.

Finally, referring now to FIG. 3L, an example of the cell operation conditions is shown. To program the cell, a pulse of low positive voltage (LV) is applied to the selected local bitline (drain) 37, with the selected wordline (control gate) 34 tied to a high negative voltage (-HV), the electrons are injected from floating gate 33 to local bitline 37 as shown in FIG. 3M(a). On the other hand, to erase the cell, a pulse of high positive voltage (HV) is applied to the selected wordline (control gate) 34, with the selected bitline (drain) 37 and local source 38 both tied to ground, the electrons are moving from channel to floating gate 33 as shown in FIG. 3M(b). To read the data stored in the cell, a pulse of low positive voltage (LV) is applied to both the selected wordline (control gate) 34 and bitline (drain) 37.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5149665 *Jul 10, 1991Sep 22, 1992Micron Technology, Inc.Conductive source line for high density programmable read-only memory applications
US5204542 *Oct 25, 1991Apr 20, 1993Oki Electric Industry Co., Ltd.Nonvolatile semiconductor memory device of shared contact scheme not having inclined wiring
US5274588 *Jul 25, 1991Dec 28, 1993Texas Instruments IncorporatedSplit-gate cell for an EEPROM
US5280446 *Jun 8, 1992Jan 18, 1994Bright Microelectronics, Inc.Flash eprom memory circuit having source side programming
US5282160 *Jul 18, 1991Jan 25, 1994Nec CorporationNon-volatile semiconductor memory having double gate structure
US5379254 *Oct 20, 1992Jan 3, 1995National Semiconductor CorporationAsymmetrical alternate metal virtual ground EPROM array
US5409854 *Mar 15, 1994Apr 25, 1995National Semiconductor CorporationMethod for forming a virtual-ground flash EPROM array with floating gates that are self aligned to the field oxide regions of the array
US5416349 *Dec 16, 1993May 16, 1995National Semiconductor CorporationIncreased-density flash EPROM that requires less area to form the metal bit line-to-drain contacts
US5554867 *Dec 9, 1994Sep 10, 1996Mitsubishi Denki Kabushiki KaishaNonvolatile semiconductor memory device having a memory cell transistor and a select transistor
US5589413 *Nov 27, 1995Dec 31, 1996Taiwan Semiconductor Manufacturing CompanyMethod of manufacturing self-aligned bit-line during EPROM fabrication
US5592001 *Apr 5, 1996Jan 7, 1997Kabushiki Kaisha ToshibaNon-volatile semiconductor memory device
US5834806 *Jun 12, 1997Nov 10, 1998Taiwan Semiconductor Manufacturing Company, Ltd.Raised-bitline, contactless, trenched, flash memory cell
Non-Patent Citations
Reference
1Kobayashi et al, "Memory Array Architecture and Decoding Scheme for 3V Only Sector Erasable Dinor Flash Memory", IEEE Journal of Solid State Circuits, vol. 29, No. 4, Apr. 1994 pp. 454-460, Apr. 1994.
2 *Kobayashi et al, Memory Array Architecture and Decoding Scheme for 3V Only Sector Erasable Dinor Flash Memory , IEEE Journal of Solid State Circuits, vol. 29, No. 4, Apr. 1994 pp. 454 460, Apr. 1994.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6033955 *Sep 23, 1998Mar 7, 2000Advanced Micro Devices, Inc.Method of making flexibly partitioned metal line segments for a simultaneous operation flash memory device with a flexible bank partition architecture
US6074914 *Oct 30, 1998Jun 13, 2000Halo Lsi Design & Device Technology, Inc.Integration method for sidewall split gate flash transistor
US6255170 *Apr 19, 2000Jul 3, 2001Hyundai Electronics Industries, Co., Ltd.Flash memory and method for fabricating the same
US6370081Feb 9, 2001Apr 9, 2002Kabushiki Kaisha ToshibaNonvolatile semiconductor memory
US6396086 *Sep 23, 1999May 28, 2002Kabushiki Kaisha ToshibaSemiconductor device and semiconductor integrated circuit having a conductive film on element region
US6512703Aug 6, 2001Jan 28, 2003Tokyo Shibaura Electric CoNonvolatile semiconductor memory
US6657892Jul 26, 2002Dec 2, 2003Kabushiki Kaisha ToshibaNonvolatile semiconductor memory
US6801458Aug 12, 2003Oct 5, 2004Kabushiki Kaisha ToshibaNonvolatile semiconductor memory
US6972229 *Dec 23, 2003Dec 6, 200502Ic, Inc.Method of manufacturing self-aligned non-volatile memory device
US7173850Aug 30, 2004Feb 6, 2007Kabushiki Kaisha ToshibaNonvolatile semiconductor memory
US7186612Apr 6, 2004Mar 6, 2007O2Ic, Inc.Non-volatile DRAM and a method of making thereof
US7232717May 28, 2003Jun 19, 2007O2Ic, Inc.Method of manufacturing non-volatile DRAM
US7301809Feb 5, 2007Nov 27, 2007Kabushiki Kaisha ToshibaNonvolatile semiconductor memory
US7333369Feb 5, 2007Feb 19, 2008Kabushiki Kaisha ToshibaNonvolatile semiconductor memory
US7463540Feb 5, 2007Dec 9, 2008Kabushiki Kaisha ToshibaNonvolatile semiconductor memory
US7488657 *Jun 17, 2005Feb 10, 2009Spansion LlcMethod and system for forming straight word lines in a flash memory array
CN102446816A *Oct 14, 2010May 9, 2012中芯国际集成电路制造(上海)有限公司Manufacturing method for contact holes in active region of split-grid type memory device
WO2005062944A2 *Dec 23, 2004Jul 14, 2005Kyu Hyun ChoiMethod of manufacturing self-aligned non-volatile memory device
Classifications
U.S. Classification438/257, 257/315, 257/E27.103, 257/E21.68
International ClassificationG11C16/04, H01L21/8247, H01L27/115
Cooperative ClassificationG11C16/0416, H01L27/11517, H01L27/115
European ClassificationH01L27/115F, G11C16/04F1, H01L27/115
Legal Events
DateCodeEventDescription
Dec 9, 2003FPExpired due to failure to pay maintenance fee
Effective date: 20031012
Oct 14, 2003LAPSLapse for failure to pay maintenance fees
Feb 7, 2000ASAssignment
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UTEK SEMICONDUCTOR CORP.;REEL/FRAME:010568/0175
Effective date: 19991221
Owner name: UNITED MICROELECTRONICS CORP. SCIENCE-BASED INDUST
Owner name: UNITED MICROELECTRONICS CORP. SCIENCE-BASED INDUST
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UTEK SEMICONDUCTOR CORP.;REEL/FRAME:010568/0175
Effective date: 19991221
Sep 21, 1998ASAssignment
Owner name: UTEK SEMICONDUCTOR CORP., TAIWAN
Free format text: CHANGE OF NAME;ASSIGNOR:HOLTEK MICROELECTRONICS, INC.;REEL/FRAME:009490/0001
Effective date: 19980630