|Publication number||US5981326 A|
|Application number||US 09/046,243|
|Publication date||Nov 9, 1999|
|Filing date||Mar 23, 1998|
|Priority date||Mar 23, 1998|
|Publication number||046243, 09046243, US 5981326 A, US 5981326A, US-A-5981326, US5981326 A, US5981326A|
|Inventors||Frank M. Wanlass|
|Original Assignee||Wanlass; Frank M.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Referenced by (10), Classifications (24), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention is a processing method for electrically isolating CMOS transistors. The method does not require any shallow trench isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.
High density complementary metal oxide silicon (CMOS) circuits require advanced isolation techniques. Local Oxidation of Silicon (LOCOS) has been used for several years for isolation. In this technique silicon dioxide is grown on the silicon field regions between devices, with silicon nitride preventing oxide growth on the silicon regions that will become device channels and junctions. LOCOS is not suitable for isolating very small submicron transistors, because the oxide growth will encroach laterally beneath the nitride masking layer for a distance that will substantially reduce small device dimensions.
More recently shallow trench isolation (STI) has become popular for submicron isolation. In this technique a shallow trench is etched in the silicon surrounding the active device, the trench is overfilled with silicon dioxide, and chemical mechanical polishing is used to planarize the surface to the original silicon surface. STI is not without problems: 1- The silicon etch can damage the silicon. 2- Source to drain leakage can develop along the sharp corner at the edge of the silicon. 3- The gate oxide breakdown voltage can be lowered along this sharp corner.
The present invention is a method for implanting a channel stop dopant into field regions between transistor active regions, self aligning relatively thick silicon dioxide over these field regions and providing thin oxide in the active regions that are self aligned to the field regions.
FIG. 1 is across section of a portion of a wafer at the beginning of this invention, where wells have been previously formed, where SiO2 has been grown and amorphous Si has been deposited, and where photoresist has been patterned to define NMOS transistors.
FIG. 2 shows the wafer after implanting boron.
FIG. 3 shows the wafer after the first amorphous Si etch.
FIG. 4 shows the wafer after coating with and patterning photoresist to define PMOS transistors.
FIG. 5 shows the wafer after implanting phosphorus and etching Si.
FIG. 6 shows the wafer after depositing SiO2.
FIG. 7 shows the wafer after chemical mechanical polishing of the deposited SiO2.
FIG. 8 shows the wafer after removing the amorphous Si.
The following is a description of a preferred process flow for isolating CMOS transistors according to this invention, where the thicknesses shown are representative of the requirements for a low voltage CMOS logic circuit. Other thicknesses can be used for different applications.
1. FIG. 1 shows, at the start of the process, a portion of a silicon (Si) wafer 1 with previously implanted and diffused P well region 2, and N well region 3. Also shown is a grown silicon dioxide (SiO2) layer 4 with a thickness of ˜10 nm, and a deposited amorphous Si layer 5 with a thickness of ˜200 nm. A photoresist pattern 6N defines the location of NMOS transistor regions in the P well, and the photoresist entirely covers the N well.
2. With the photoresist in place a boron implant is performed. As shown in FIG. 2, the implant energy should be adjusted to place the boron ions 7 at an approximate depth equal to the amorphous Si thickness, but the energy should not be high enough to penetrate the combined photoresist and amorphous Si thickness. The dose should be at least enough to make the implanted boron concentration equal to 3 or 4 times the original boron concentration of the P well at the silicon substrate surface; this will insure a high field inversion voltage. Optionally, the amorphous Si can be partially anisotropically plasma etched to reduce its thickness before this boron implant.
3. Next the amorphous Si is completely anisotropically plasma etched, stopping at the underlying thin SiO2. FIG. 3 shows the wafer at this point after photoresist removal.
4. Next, as shown in FIG. 4, photoresist 6P is applied and patterned to define the PMOS transistors, and to completely cover the P well.
5. A phosphorus implant is performed with enough energy to place the ions 8 at the interface between the silicon wafer and the SiO2, with the dose high enough to make the implanted concentration 3 or 4 times the concentration of the N well at the silicon surface. Again, optionally, the amorphous Si can be partially anisotropically plasma etched to reduce its thickness before this phosphorus implant.
6. Next the amorphous Si is etched to the underlying thin oxide. FIG. 5 shows the wafer at this point after photoresist removal.
7. After a good wafer cleaning silicon dioxide 9 is deposited to a thickness greater than the amorphous silicon thickness, as shown in FIG. 6. Optionally, at this point the wafer can be subjected to a brief high temperature cycle to improve the quality and density of the deposited SiO2.
8. Next chemical mechanical polishing is performed on the SiO2 using the amorphous Si as an etch stop; FIG. 7 shows the results of this.
9. Finally the amorphous Si is removed, the thin underlying oxide is removed and a fresh new gate oxide 10 is grown; FIG. 8 shows this. The temperature required to grow the new gate oxide will anneal the implantations.
Subsequent processing for forming transistors can proceed using well known procedures.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6117715 *||Aug 28, 1998||Sep 12, 2000||Samsung Electronics Co., Ltd.||Methods of fabricating integrated circuit field effect transistors by performing multiple implants prior to forming the gate insulating layer thereof|
|US6809006||Sep 12, 2002||Oct 26, 2004||Hynix Semiconductor Inc.||Method of semiconductor device isolation|
|US7265405||Jan 9, 2004||Sep 4, 2007||Infineon Technologies Ag||Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts|
|US8143119 *||Mar 27, 2012||Renesas Electronics Corporation||Method of manufacturing semiconductor device having plural transistors formed in well region and semiconductor device|
|US8299543||Oct 30, 2012||Renesas Electronics Corporation||Method of manufacturing semiconductor device having plural transistors formed in well region and semiconductor device|
|US20030049911 *||Sep 12, 2002||Mar 13, 2003||Kim Bong Soo||Method of semiconductor device isolation|
|US20040195596 *||Jan 9, 2004||Oct 7, 2004||Kae-Horng Wang||Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts|
|US20100078734 *||Sep 14, 2009||Apr 1, 2010||Nec Electronics Corporation||Method of manufacturing semiconductor device having plural transistors formed in well region and semiconductor device|
|DE10133873A1 *||Jul 12, 2001||Jan 30, 2003||Infineon Technologies Ag||Verfahren zur Herstellung von Kontakten für integrierte Schaltungen|
|DE10133873B4 *||Jul 12, 2001||Apr 28, 2005||Infineon Technologies Ag||Verfahren zur Herstellung von Kontakten für integrierte Schaltungen|
|U.S. Classification||438/227, 148/DIG.1, 257/E21.544, 148/DIG.51, 438/298, 438/692, 148/DIG.85, 438/482, 257/E21.545, 438/443, 257/E21.574, 148/DIG.117|
|International Classification||H01L21/762, H01L21/765, H01L21/761|
|Cooperative Classification||Y10S148/117, Y10S148/085, Y10S148/051, H01L21/762, H01L21/765, H01L21/761|
|European Classification||H01L21/762, H01L21/761, H01L21/765|
|May 28, 2003||REMI||Maintenance fee reminder mailed|
|Nov 10, 2003||LAPS||Lapse for failure to pay maintenance fees|
|Jan 6, 2004||FP||Expired due to failure to pay maintenance fee|
Effective date: 20031109