US 6043633 A Abstract A method and apparatus for controlling a boost converter, which offers improved power factor correction by compensating for the distorting effects of parasitic capacitance and parasitic oscillations. By precise adjustments to the closing time of the boost switch, the effects of parasitic capacitance can be reduced or eliminated. A zero current detector capable of detecting both forward and reverse zero current points facilitates the compensation. The method and circuit of the present invention are well-suited to integration with an inexpensive digital controller such as a microprocessor, and a method of dithering to enhance the time resolution of clocked digital circuits is presented.
Claims(14) 1. A zero current detector for a boost converter, the boost converter including a boost switch with a first connection to an inductor having an inductor current, the zero current detector operative to detecting zero inductor current, the zero current detector comprising:
(a) a capacitor connected to the first connection; (b) a first diode with a second connection to said capacitor and a third connection to the boost switch; (c) a second diode connected to said second connection; and (d) a zero current sense output point at said second connection. 2. The zero current detector as in claim 1, further operative to the detection of zero forward inductor current and zero reverse inductor current.
3. A method for controlling a boost converter for power factor correction, the boost converter having a boost switch and an inductor with an inductor current, the method comprising the steps of:
(a) providing a zero current detector operative to the detection of zero reverse inductor current; and (b) closing the boost switch when said zero current detector detects said zero reverse inductor current. 4. A method for controlling a boost converter for power factor correction, the boost converter having a boost switch and an inductor current, the boost switch having an effective time interval for being closed, the method comprising the steps of:
(a) predetermining a minimum inductor current; (b) providing a minimum current discriminator, said minimum current discriminator operative to determining that the inductor current is equal to said minimum inductor current; (c) closing the boost switch; (d) waiting until said minimum current discriminator determines that the inductor current is equal to said minimum inductor current; (e) commencing the effective time interval; (f) waiting for the completion of the effective time interval; and (g) opening the boost switch. 5. A method for using a clocked digital circuit to generate a duty cycle for use in a pulse-width modulator for power factor correction, the clocked digital circuit operative to generating a plurality of discrete time intervals, the duty cycle having at least one state with an intermediate time interval distinct from any of the discrete time intervals generated by the clocked digital circuit, the method comprising the step of constructing a group of a plurality of time intervals selected from the plurality of discrete time intervals generated by the clocked digital circuit, such that the average of the time intervals of said group approximates the intermediate time interval.
6. A method for controlling a power converter having an inductor and a switching transistor, the switching transistor being coupled from one end of the inductor to a common voltage potential, the inductor having an inductor current capable of being substantially zero flowing in either direction, the method comprising the steps of:
(a) detecting when the inductor current increases from the reverse direction and reaches zero; and (b) turning on the switching transistor. 7. A method for controlling a power converter for providing power factor correction, the power converter including an inductor having an inductor current and a stored inductor energy, and a switching transistor having a parasitic capacitance storing a parasitic capacitance energy, the switching transistor being coupled from one end of the inductor to a common voltage, the method comprising the steps of:
(a) determining a predetermined effective time interval during which the switching transistor should remain on to achieve a desired power factor correction; (b) determining a minimum value for the inductor current which would result in the stored inductor energy being substantially equal to the parasitic capacitance energy; (c) turning on the switching transistor; (d) commencing a measurement of elapsed time when the inductor current reaches said minimum value; and (e) turning off the switching transistor when said elapsed time substantially equals said predetermined effective time interval. 8. A method for controlling a duty cycle of a switching power converter using a clocked digital circuit driven by a digital clock having a fixed clock period, the method comprising the steps of:
(a) determining a desired duty cycle time period; (b) determining a lower number of clock periods having a sum lower than said desired duty cycle time period; (c) determining a higher number of clock periods having a sum higher than said desired duty cycle time period; (d) adjusting the duty cycle of the switching power converter to have a first time period equal to the sum of the lower number of clock periods for a first number of cycles; and (e) adjusting the duty cycle of the switching power converter to have a second time period equal to the sum of the higher number of clock periods for a second number of cycles, wherein an average time period of said first number of cycles each having said first time period and said second number of cycles each having said second time period is substantially equal to said desired duty cycle time period. 9. A zero current detector for a power converter having an inductor and a switching transistor, the switching transistor being coupled from one end of the inductor having an inductor current to a common voltage, the zero current detector circuit comprising:
(a) a capacitor having a first end and a second end, said first end being coupled to the one end of the inductor; (b) a first diode having a first anode and a first cathode, said first anode being coupled to the common voltage and said first cathode being coupled to said second end of said capacitor; (c) a second diode having a second anode and a second cathode, said second anode being coupled to said second end of said capacitor and said second cathode being coupled to a higher voltage than the common voltage, the zero current detector producing an output voltage at said second end of said capacitor indicative of the inductor current. 10. The zero current detector as in claim 9, wherein the inductor has an inductor current ranging over negative, zero, and positive values, the zero current detector being adapted so that said output voltage has a first level when the inductor current ranges over a positive value, and so that said output voltage has a second level when the inductor current ranges over a negative value.
11. The zero current detector of claim 10, wherein said first voltage level is substantially equal to said higher voltage, and said second voltage level is substantially equal to the common voltage.
12. The zero current detector of claim 10, wherein said output voltage is adapted to transition from said first level to said second level when the inductor current decreases from a positive value and substantially reaches a zero value.
13. The zero current detector of claim 10, wherein said output voltage is adapted to transition from said second level to said first level when the inductor current increases from a negative value and substantially reaches a zero value.
14. A power converter for providing power factor correction, the power converter comprising:
(a) an inductor having an inductor current, said inductor current ranging over negative, zero, and positive values; (b) a switching transistor having a parasitic capacitance, the switching transistor being coupled from one end of said inductor to a common voltage; (c) a zero current detector adapted to output a zero current sense output when said inductor current is substantially zero; (d) a minimum current discriminator adapted to output a minimum current signal when said inductor current reaches a predetermined value; (e) a timing circuit adapted to output a timing signal at the end of a predetermined effective time interval after being activated; (f) a pulse-width modulator for turning on and turning off said switching transistor, said pulse-width modulator receiving said zero current signal, said minimum current signal, and said timing signal, said pulse-width modulator being adapted to: i) turn on said switching transistor when said zero current sense output is received; ii) activate said timing circuit when said minimum current signal is received; and iii) turn off said switching transistor when said timing signal is received. Description The present invention relates to a method and apparatus for active power factor correction, and, more particularly, to an improved method and apparatus for critical mode and discontinuous mode control of boost converters. Power factor is a measure of the efficiency of electrical utilization by electrical loads. Because instantaneous electrical power equals the current multiplied by the voltage, an electrical load which draws a large current at a low voltage and which sustains a high voltage while drawing little current does not utilize the power delivery capabilities of its power supply efficiently. For maximum efficiency, a load should always draw a current that is proportional to the voltage applied across the load. That is, the load should appear as a resistive impedance to the power supply. For a purely resistive load, the power factor equals unity, whereas for loads which depart from this ideal behavior the power factor will be less than one. A low power factor is undesirable from a standpoint of equipment and power main utilization, and in most cases it is necessary to provide means of increasing a low power factor toward unity. For inductive or capacitive loads, power factor correction is usually accomplished by the use of passive components which eliminate high-order harmonics and reduce the first harmonic phase difference between the voltage and current to as close to zero as possible. At higher frequencies, however, the problem of total harmonic distortion becomes more important than phase shift, and active electronic means are needed to perform the correction. This is especially true in cases involving non-linear loads. Power supplies, for example, particularly high-frequency power supplies, create severe total harmonic distortion which leads to a low power factor. This problem associated with total harmonic distortion and the reduction of power factor is illustrated in FIG. 1, to which reference is now briefly made. FIG. 1 illustrates the input voltage and current waveforms as functions of the time t for a device which rectifies alternating current and charges a capacitor. This is a common configuration for power supplies. In FIG. 1 a full-wave rectified input voltage V A common means of shaping the input current waveform to be proportional to the input voltage waveform is to use a boost converter. The basic topology of prior art boost converters is shown in FIG. 2, to which reference is now made. This topology is referred to as the "boost topology." A boost converter is a type of DC-to-DC power converter whose output voltage at a load Z The present application uses the terms "closed" and "on" equivalently to denote a state of a switching device wherein the switching device conducts electric current, and uses the terms "opened" and "off` equivalently to denote a state of a switching device wherein the switching device does not conduct electric current. The present application uses the term "closing" to denote the action of putting a switching device into the closed state, and uses the term "opening" to denote the action of putting a switching device into the opened state. The present application uses the term "inductive charging" to denote the driving of current through an inductor by an external voltage in order to build a magnetic field. The present application uses the term "inductive discharging" to denote the driving of current by an inductor due to the collapse of the inductor's magnetic field. Once boost switch 14 is opened, the current driven by inductor 10 flows into load Z It is noted that the boost topology relies on the principle of pulse-width modulation, wherein the duty cycle of the boost switch is altered by varying the respective time intervals of the pulses corresponding to the closed and opened states. The present application uses the term "duty cycle" to denote a repeated sequence of two alternating states, each state of which has a specified time interval. The present application uses the term "pulse-width modulator" ("PWM") to refer to any circuit which performs pulse-width modulation. The present application uses the term "time interval" to denote a period or duration of time as distinct from the occurrence of an instant of time. Both the start and end of a time interval are instants of time, and the time interval is the period of time between them. There are three principal operating modes for a boost converter. operating modes are distinguished by how current flows through inductor 10 (FIG. 2). One operating mode is referred to as the "continuous mode," wherein input current I The continuous mode is typically used for high power applications. A drawback of the continuous mode is that a high reverse current flows briefly through diode 12 and boost switch 14 (FIG. 2) until diode 12 recovers, thereby putting stress on diode 12. Another drawback of the continuous mode is that inductor 10 must have a high value of inductance. A further drawback of the continuous mode is that it generally requires an analog multiplier for regulating the cycle by which boost switch 14 is operated, and this adds complexity and cost to the implementation. The discontinuous mode is useful at low power levels. Diode 12 recovers at zero current and there is therefore no stress on diode 12 and boost switch 14. However, the drawback to the discontinuous mode is that there is usually an associated high ripple current. The critical mode is the most commonly-used operating mode for boost converters. As with the discontinuous mode, diode 12 (FIG. 2) recovers with zero current and therefore there is no stress on diode 12. The critical mode, however, has the capability of controlling higher power than the discontinuous mode and has a lower ripple current. The critical mode also has advantages over the continuous mode. The critical mode is easier to implement than the continuous mode, and the critical mode offers better feedback loop stability and can utilize a smaller inductor. In order to operate a boost converter in the critical mode, it is necessary to detect when input current I Unfortunately, although boost converters are able to perform power factor correction efficiently for a variety of loads, certain deficiencies of the prior art zero-detection method for critical mode operation lead to a residual total harmonic distortion at low power levels, caused by parasitic oscillations resulting from parasitic capacitance in the components of the boost converter. These low power levels occur at small loads, and they also occur during the normal operating cycle at the points when the input voltage V Furthermore, the techniques used in the prior art to implement a zero current detector are not wholly satisfactory. For example, inductor 10 (FIG. 2) may be provided with a secondary coil, to function as a flyback transformer for sensing the collapse of the magnetic field and thereby providing a zero current detector which can detect zero forward inductor current (J. H. Alberkrack and S. M. Barrow, "An Economical Controller Corrects Power Factor", Power Conversion, September 1992 Proceedings, p. 322-329). Techniques such as this, however, can involve significant additional expense in a low-cost circuit for power factor correction, and moreover are limited to detecting the zero forward inductor current. To compensate for the effect of the parasitic capacitance of a boost converter, it is desirable to also detect zero reverse inductor current. Therefore, it would be highly advantageous to have a less expensive method for implementing a zero current detector which can detect both zero forward inductor current and zero reverse inductor current. This goal is also met by the present invention. Moreover, it is desirable to be able to utilize certain types of digital circuits in pulse-width modulators because of their versatility and low cost. In particular it is highly desirable to be able to utilize clocked digital circuits, including but not limited to microprocessors and microcontrollers, in pulse-width modulators. The present application uses the term "clocked digital circuit" to denote any electrical circuit which is synchronized by, triggered by, or which otherwise operates in accordance with discretely timed clock signals that repeat at regular time intervals. Unfortunately, although clocked digital circuits are able to output control signals having durations of calculated time intervals, the calculated time intervals output by a clocked digital circuit are constrained to always be multiples of a basic time interval which is equal to the period of the clock which drives the clocked digital circuit multiplied by the number of clock cycles required for the relevant operations. The present application uses the term "resolution" to denote the minimum time interval which a clocked digital circuit can output. For example, if a clocked digital circuit has a clock period of 500 nanoseconds and requires 10 clock cycles to perform a particular timing operation, then the time intervals which can be output by this clocked digital circuit will be limited to time intervals which are multiples of 5 μsec, and hence the resolution of this clocked digital circuit is 5 microseconds. Such a clocked digital circuit is able to output time intervals such as 5 microseconds, 10 microseconds, 15 microseconds, 20 microseconds, and so forth, but is not able to output time intervals such as 6 microseconds, 13.5 microseconds, 17 microseconds, or 19 microseconds. For effective power factor correction, however, it may be necessary to be able to adjust the time intervals of a duty cycle to a finer resolution than an otherwise suitable clocked digital circuit can attain. This goal is also met by the present invention. According to the present invention there is provided an innovative zero current detector which is easy and inexpensive to implement. Moreover, the zero current detector of the present invention allows detecting both zero forward inductor current and zero reverse inductor current. This allows detecting the zero current points of the parasitic oscillations of the parasitic capacitance in the components of the boost converter, and according to the present invention there is also provided an innovative method of compensating for this parasitic capacitance. To compensate for the effect of the parasitic capacitance on waveform shape it is necessary to dynamically adjust the timing of the closing of boost switch 14 (FIG. 2) pulse by pulse according to the V Furthermore, because an optimized operating mode of a boost converter needs to be changed according to changing V The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein: FIG. 1 shows the input voltage and current waveforms for a non-linear load which involves the charging of a capacitor, such as a power supply. FIG. 2 shows the topology of a prior art boost converter. FIG. 3 shows the continuous mode of operation for a boost converter. FIG. 4 shows the discontinuous mode of operation for a boost converter. FIG. 5 shows the critical mode of operation for a boost converter. FIG. 6 shows the duty cycle, the pre-closed instant, and the post-closed instant of a boost converter boost switch. FIG. 7 shows the sources of parasitic capacitance in a boost converter. FIG. 8 shows the influence of parasitic capacitance. FIG. 9 shows inductor current ringing due to parasitic capacitance, and also shows the zero current points. FIG. 10 shows a zero current detector according to the present invention. FIG. 11 shows the signal edges from the zero current detector according to the present invention. FIG. 12 shows the delay introduced into the critical mode timing by the method according to the present invention. FIG. 13 shows the time interval delay for the post-closed instant. FIG. 14 is a functional block diagram of a control circuit according to the present invention. FIG. 15 is a timing chart of the control circuit according to the present invention. The present invention is of a method and apparatus for implementing a zero current detector for critical mode and discontinuous mode operation of a boost converter, and a method and apparatus for regulating the switching of the boost converter to eliminate the total harmonic distortion resulting energy stored in parasitic capacitance in the boost converter components. Specifically, the method and apparatus of the present invention are especially well-suited to the use of digital control of the boost converter. The principles and operation of a zero current detector and method for control of a boost converter according to the present invention may be better understood with reference to the drawings and the accompanying description. Referring now to the drawings, FIG. 7 shows the sources of parasitic capacitance in a boost converter. A capacitance C FIG. 6 shows a typical duty cycle for a boost switch. There are two distinct cases in which parasitic capacitance C The pre-closed instant Case: As is known in the art, an inductive circuit containing a parasitic capacitance will exhibit parasitic oscillations (parasitic resonances). In the case of the boost topology, these parasitic oscillations interfere with power factor correction at the pre-closed instant. To see this, consider the case where charge has been stored on parasitic capacitance C If, however, the proper period for boost switch 14 to be closed is significantly smaller than Δt, such as only 5 μsec, then inductive charging of inductor 10 cannot take place. Such short inductive charging periods occur when the ratio V The method according to the present invention properly compensates for the parasitic capacitance and the associated parasitic resonance in the pre-closed instant case, as described below. FIG. 9 shows a current flow which occurs in inductor current ringing and the zero current points associated therewith. Currents above a zero inductor current line 32 correspond to forward inductor current denoted as I In order to facilitate the use of the method of the present invention as described above, the apparatus of the present invention includes an innovative zero current detector, and embodiment of which is shown in FIG. 10. The zero current detector according to the present invention includes a capacitor 20 to isolate a zero current sense output point 26 from the voltage on inductor 10 and from output voltage V FIG. 11 shows a zero current sense output point voltage waveform 40 from zero current sense output point 26 (FIG. 10), a zero forward inductor current edge 36, and a zero reverse inductor current edge 38, which occurs after zero forward inductor current edge 36 by a time interval delay τ, corresponding to half the period of the parasitic oscillation. Also shown in FIG. 11 is a boost switch control signal 42 which derives the timing of its transition from boost switch opened to boost switch closed from zero reverse inductor current edge 38. FIG. 12 shows a time interval delay 50 between an inductive discharging interval 52 and an inductive charging interval 54. time interval delay 50 is introduced by the method according to the present invention, and corresponds to τ, half the period of the parasitic oscillation. The post-closed instant Case: When boost switch 14 is opened, parasitic capacitance C FIG. 13, to which reference is now made, illustrates the method according to the present invention for compensating for the effects of the parasitic capacitance at the post-closed instant. The principle of the method is to extend the time interval during which boost switch 14 (FIG. 7) is closed, by a predetermined compensating time interval T At absolute no load, T the energy absorbed by parasitic capacitance C FIG. 13 shows an inductor current waveform 60 as a function of time t. Inductor current waveform 60 has a zero forward inductor current time 64 and a zero reverse inductor current time 66. Inductor current waveform 60 reaches a peak at a peak inductor current time 70. The peak inductor current is predetermined in order to achieve a desired power factor correction. FIG. 13 also shows the minimum inductor current I Time 82 determines maximum inductor current time 70, and therefore the maximum of inductor current I In another embodiment of the present invention, starting closed time 78 begins at zero forward inductor current pulse 72 rather than at zero reverse inductor current pulse 74. In this manner, compensating time interval T FIG. 14 is a functional block diagram of an embodiment of a device according to the present invention, which also incorporates the zero current detector of the present invention as described above. FIG. 14 also shows components and features of a boost converter which is being controlled by the circuit according to the present invention. Components and features of the boost converter include input voltage V Note that FIG. 14 is a functional block diagram, in that one or more of the components indicated as blocks need not be physically separate components. Certain integrated components, such as programmable digital microcontrollers and microprocessors, contain the logic and support circuitry to implement many or all of the functional blocks shown in FIG. 14. Integrating many or all of the functional units shown in FIG. 14 into a single component serves to reduce manufacturing costs significantly. An additional advantage in integrating these components into a programmable controller is that such a device can easily change the operating mode of the boost converter from critical mode to discontinuous mode as circumstances warrant. Such a power factor correction device can adapt to operating and load conditions that fluctuate heavily. In particular, the discontinuous mode is advantageous to use at low output power levels. FIG. 15 shows a timing chart of the circuit shown in FIG. 14, for operation in both the critical mode and the discontinuous mode. The waveforms of FIG. 15 correspond to those of FIG. 13 and are correlated to the circuit of FIG. 14. A waveform 300 shows inductor current I Because clocked digital circuits are employed in embodiments of the present invention to implement power factor correction pulse-width modulator 100 (FIG. 14) it may be necessary to improve the time resolution of clocked digital circuits to meet the requirements of determining time interval T
k=m(n+1-n') (8) The larger m becomes the more accurately k may be chosen. The value of m should be chosen so that the dithering is reasonably accurate, but the number of consecutive duty cycles should be kept small enough that the averaging takes place over a period that is small compared to the input current period. In the numerical example given above, τ=5 microseconds, n=6 (30 microseconds), n+1=7 (35 microseconds), n'=6.4 (32 microseconds), and m=5. Applying Equation (8), it is seen that k=3 and m-k=2, giving the sequence 30 microseconds, 35 microseconds, 30 microseconds, 35 microseconds, 30 microseconds. The different time interval values should be intermixed as uniformly as possible for a given distribution. In summary, this dithering method allows a clocked digital circuit which generates discrete time intervals to generate a duty cycle for use in a pulse-width modulator for power factor correction, where the time interval of a state of the duty cycle is intermediate between two adjacent discrete time intervals which can be generated by the clocked digital circuit. The present application uses the term "adjacent" in the context of two discrete values to denote that there is no discrete value intermediate between the adjacent values; that is, an "intermediate" value is less than the greater of the two adjacent discrete values, but greater than the lesser of the two adjacent discrete values. The dithering method consists of constructing a group of (more than one) consecutive time intervals, the time intervals of which are selected from among the discrete time intervals of the clocked digital circuit, such that the average of the time intervals of the group will approximate the desired time interval or the state of the duty cycle. While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made. Patent Citations
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