|Publication number||US6058414 A|
|Application number||US 09/004,135|
|Publication date||May 2, 2000|
|Filing date||Jan 7, 1998|
|Priority date||Jan 7, 1998|
|Publication number||004135, 09004135, US 6058414 A, US 6058414A, US-A-6058414, US6058414 A, US6058414A|
|Inventors||Ravindranath Kasinath Manikundalam, Jayashree Ramanathan|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (40), Classifications (6), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates generally to multiple processor computer systems and more specifically to the assignment of resources to computer system processes. More particularly, the present invention relates to the dynamic assignment of input/output resources to application programs in an asymmetric multiple processor computer system in which input/output resources exist on a subset of the multiple processors.
2. Background and Related Art
Multiple processor computer systems are those in which more than one processing element or CPU is used to process a given workload. A multiple processor system may have two, four, or more processors within a computer cabinet or in several enclosures connected to form a single processing entity.
Symmetric multiprocessors (SMP) have shared memory that is accessible by all of the processors in the complex. Shared memory enables the task scheduling function of the system to assign a task to the processor that has the necessary resources for that task. Such resources may include input/output devices such as displays, printers, or communications devices. In a symmetric multiprocessing system the shared memory environment enables a task to be scheduled on a processor with a certain resource and later rescheduled through the shared memory to a different processor.
Asymmetric multiple processor systems contain resources that are physically attached to only a subset of the processors. An asymmetric system includes configurations such as clustered computer systems which may reside in different processor cabinets and be linked by a high speed bus or switching mechanism. The scheduler in prior art asymmetric multiple processor systems typically assigns an application to a processor having the resources required to complete the application execution. The application is statically bound to the processor with the resources. There is no provision for unbinding the application from a processor and there is no ability to reschedule the application process on a different processor with different resources during its execution.
An asymmetric multiple processor system according to the present invention is shown generally in FIG. 1 as 100. Computer processors C1-C3 102, 104, 106 each have certain resources attached R1-R7. Resource 1 108 is physically attached to processor C1 102. Only processor C1 can directly access or use resource 1 108. Indirect access to the resource is provided by, for example, sending an interprocess message to the processor with the required resource. Indirect access is costly to performance and much less desirable than direct access. The number of resources assigned to any one processor depends upon the particular system structure. A cluster of computer systems may have all resource attached to a single processor or they may be distributed evenly among the processors. The specific allocation of resources to processors is immaterial to the present invention.
Resources such as permament storage disk devices 120 can be shared among processors. The sharing of disk resources enables the processors to communicate and to cooperate in the execution of applications. The ability to be shared amongst processors depends on the type of resource. Typically, the input/output resources other than disk devices can only be attached to a single processor and cannot be shared between or among processors.
Prior art asymmetric multiprocessing systems have a technical problem in that static binding of applications to processors creates load balancing and performance problems. If several applications require access to a particular resource, e.g. R1 108, the processor C1 supporting that resource can become overloaded while the other processors in the complex lack work. This results in poorer system throughput due to the bottleneck of C1. A second problem arises when an application requires access to different resources on different processors. If a particular application requires the use of R1 108 and R3 110, a scheduling problem results. The prior art systems also do not effectively handle the case where less than all of the processors have access to a particular resource. If, for example, only two of the three processors were able to access a device, prior art asymmetric multiprocessing scheduling would enable only one processor to be statically bound to an application process and would not perform any load balancing between the subset of processors.
A technical problem therefore exists to develop a method and system to enable dynamic scheduling of applications and processes using resources that are shared by one or more, but less than all of the processors in an asymmetric multiple processor complex.
The present invention is directed to providing a method and system for dynamically assigning application processes to multiple processor elements able to directly access a resource. Scheduling an application process on the processor that has physical access to a resource is more efficient than providing logical access to the resource on another processor. The present invention maintains in the operating system a list of processors with the types of resources connected to those processors. Each executing application or process registers with the operating system to access a specific resource or I/O device. Upon completion of resource access the application deregisters indicating that access to the device is no longer required. The present invention also provides operating system notification to an application when the application's resource requirements could cause unproductive scheduling of tasks between processors or thrashing of the processors handling the application.
A system for dynamically binding an executable process to a resource in a computer system having two or more processors, the system including storing a mapping of resources to processors having access to those resources, means for intercepting an executable application process request for access to a resource, means for dynamically binding an executable application process to a processor having access to a resource.
It is therefore an object of the present invention to provide an operating system ability to determine the resources available on each processor in an asymmetric multiple processor complex.
It is another object of the present invention to provide dynamic binding of applications to processors having resources required by that application. It is yet another object of the invention to deregister and unbind the application from a processor when access to that processor is no longer required.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawing wherein like reference numbers represent like parts of the invention.
FIG. 1 is a block diagram illustrating an example of an asymmetric multiple processor complex according to the present invention.
FIG. 2 is a block diagram illustrating the processor components in a processor in an asymmetric multiple processor complex.
FIG. 3 is an illustration of the processes and the memory of a computer system according to the present invention.
FIGS. 4(a) and 4(b) are illustrations of a resource registry and processors to resource mapping tables according to the present invention.
FIG. 5 is a flow chart depicting the process steps of an application executing in the system according to the present invention.
FIGS. 6(a) and 6(b) illustrate flow charts of application process to resource binding according to the present invention.
An asymmetric multiple processor system includes two or more processing resources or CPUs that contain resources not physically attached to all processors. A generalized layout of such a system is shown in FIG. 1. Each of the computer systems connected to form the asymmetric multiple processor will have at least a CPU 210 memory 212 and network or communications connectivity 214. In addition, one or more of the processor complexes will have an I/O controller 216 which may be connected to permanent or removable storage media 218, a printer 220, and display mouse and keyboard 222, 224, 226. The network controller will connect the processor complex 202 to other processor complexes 204 and 206 through interconnection means 230 which may be a network, bus, or switch type of interconnection. Any number of processor complexes can be connected in this way limited only by the ability of the operating system to manage the complex.
The execution of applications in an asymmetric multiprocessing system is controlled by the operating system. An "application" includes all types of processing by the computer system including functions of the operating system itself as well as user defined tasks or processes for accomplishing a certain result. The operating system for an asymmetric multiple processor operates in the memory 212 of one or more of the processing complexes. The operating system for an asymmetric multiple processor system must include logic for scheduling application processes on the various processor complexes and for managing the communication of processor requests and requirements between the processing elements.
The operating system executing in the memory of an asymmetric multiple processor complex is shown in greater detail in FIG. 3. Only the components of the operating system of interest to the present invention are described. These components reside generally in the memory 302 of a processor complex. Applications waiting for execution are maintained in the queue 304. The processor task scheduler 307 determines the application to be executed based on the priority and other scheduling algorithms that do not form a part of this invention. The scheduler loads an application into the loaded application area 308.
The operating system according to the present invention, is modified to maintain a record of processors that have access to each resource. Resources include input/output (I/O) devices and other devices which can be accessed by less than all of the processors in a multiprocessor complex. The operating system maintains a resource table 400 that maintains a list of processors from which each resource or I/O device may be accessed. The list is dynamically updated based on the addition or deletion of processors with access to a resource. A resource registery (FIG. 4(b)) is maintained which maps applications to the resources they need. A privileged operating system entity handles the registration and updates of the resource registry and applies device authorization information to control the access to that resource.
The present invention is practiced in connection with an operating system such as the IBM OS/2 Operating System or the IBM AIX Operating System. These operating systems run on a variety of computers including computer processors from the Intel Corporation, PowerPC Microprocessors from IBM Corporation and other types of microprocessors. The present invention is not limited to a particular operating system or particular processor and can be implemented in the processing logic for various operating systems. The present invention is therefore extendible to operating systems such as the UNIX Operating System, the MacIntosh Operating System, the Microsoft Windows Operating System, and others.
The present invention implements an operating system application programming interface (API) that enables an application or process to designate the resources required for that application. The application can register to access a resource in the registry 304. Upon completion of resource use, the application invokes a second API to deregister the application from the resource.
An application is bound to a particular processor and resource based on the requirements of that application. Access to the resource or device is granted or denied based on the privileges held by an application. Binding occurs dynamically when the application requires access to the resource. For example, an attempt to access an unbound resource will cause a fault to an I/O port or I/O memory area (a "port fault" or a "memory fault"). This fault is intercepted and processed by the resource binder 306 which dynamically binds the application to the processor having the required resource as depicted in the processor resource map 400. It also updates the resource registry entry for the application. In contrast to prior art systems, the application is not statically bound to that processor and once resource access is completed, the application deregisters indicating that the resource is no longer needed and can be bound to other processors as required.
If more than one processor can access a particular device the operating system resource binder schedules the application to the least busy processor.
The applications may also indicate to the resource registry that no resources are required thereby enabling the application to be scheduled on any processor without regard to processor resource connections.
The flow of execution for a particular application is shown generally in FIG. 5. The application performs certain computations 502 until an attempt is made to access resource 1 450. This access will cause an exception to be raised (a fault) and binding to occur as discussed above. Additional computation 506 and additional accesses 508 can occur during the life of the process until it is terminated.
The operating system analyzes the resource requirements presented to the resource registry 304 and provides feedback on thrashing to the application process. Thus, if resource 1 and resource 6 are on different processors and the application logic repeatedly accesses one then the other of the resources this could cause the application to first be scheduled on one processor then move to a second causing thrashing back and forth between the processors consuming significant processor time in scheduling rather than in productive computation activity. The present invention provides APIs that enable the application to recognize such thrashing and provide feedback to the developer to enable tuning of the application to avoid or minimize switching between processors.
When an application registers to access a resource the operating system registry 304 ensures that the application is authorized to access those resources. The registry is a privileged entity that enforces resource access authorizations. When an application is granted access to a resource the local kernel updates applications resource authorization information but does not bind the application to any given processor.
An I/O device as an example of a resource that will be used in the following discussion. Access to an I/O device is typically through an I/O port known to the application or by accessing a specific memory location that is mapped to the I/O device. Since the application according to the present invention has not been bound to a processor or device, it does not have access to the needed I/O port or memory area. Application access to the I/O port or memory area it will raise an exception or fault and the processor will provide to the operating system exception handler one of the following exceptions including the invalid address accessed: (1) invalid port access when the processor does not recognize the I/O port; (2) unprivileged port access when the processor recognizes the I/O port, but the application is unauthorized to access this port. The processor generates an invalid memory access when the processor is unable to access a particular memory address. No exception occurs when an authorized application executes an instruction on the I/O port or I/O memory of a device when this application is scheduled on a processor which can access this device. When an invalid port access occurs but the application is authorized to access the address in question, the operating system binds the application to one of the processors that has access to the address in question. When an unprivileged port access occurs and the application is not authorized to access the address an application error is raised. When an invalid memory address access occurs and the physical memory address corresponds to a device I/O memory but the application is authorized to access that memory, it is bound locally to one of the processors that has access to the requested memory. If the application is not authorized to access the address in question an application error is raised. This processing logic is shown generally in FIGS. 6(a) and 6(b).
Implementation of the present invention in a computer system requires modifications to the process scheduling logic, to the port and memory exception handling logic and to the logic for assigning processes to processors in an asymmetric multiple processor complex. The present invention is implemented as a method or system for performing the above functions. In the preferred embodiment it is formed as a computer program product stored on a computer readable medium for causing an asymmetric computer system to perform the above-identified functions.
It will be understood from the foregoing description that various modifications and changes may be made in the preferred embodiment of the present invention without departing from its true spirit. It is intended that this description is for purposes of illustration only and should not be construed in a limiting sense. The scope of this invention should be limited only by the language of the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4677546 *||Aug 17, 1984||Jun 30, 1987||Signetics||Guarded regions for controlling memory access|
|US5475843 *||Oct 21, 1993||Dec 12, 1995||Borland International, Inc.||System and methods for improved program testing|
|US5535417 *||Sep 27, 1993||Jul 9, 1996||Hitachi America, Inc.||On-chip DMA controller with host computer interface employing boot sequencing and address generation schemes|
|US5627958 *||Mar 17, 1995||May 6, 1997||Borland International, Inc.||System and method for improved computer-based training|
|US5815664 *||Mar 19, 1996||Sep 29, 1998||Fujitsu Limited||Address reporting device and method for detecting authorized and unauthorized addresses in a network environment|
|US5907704 *||Oct 2, 1996||May 25, 1999||Quark, Inc.||Hierarchical encapsulation of instantiated objects in a multimedia authoring system including internet accessible objects|
|US5987471 *||Nov 13, 1997||Nov 16, 1999||Novell, Inc.||Sub-foldering system in a directory-service-based launcher|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6580708 *||May 25, 1999||Jun 17, 2003||Samsung Electronic Co., Ltd.||Method of multi-processing data in ARCNET|
|US7058727||Oct 11, 2001||Jun 6, 2006||International Business Machines Corporation||Method and apparatus load balancing server daemons within a server|
|US7103625 *||Oct 5, 2000||Sep 5, 2006||Veritas Operating Corporation||Virtual resource ID mapping|
|US7412703 *||Sep 19, 2003||Aug 12, 2008||Sedna Patent Services, Llc||Low cost, highly accurate video server bit-rate compensation|
|US7415709||Aug 6, 2004||Aug 19, 2008||Symantec Operating Corporation||Virtual resource ID mapping|
|US7650469||Sep 6, 2006||Jan 19, 2010||International Business Machines Corporation||Determining whether a non-running processor has access to an address space|
|US7814252 *||Oct 12, 2010||Panasonic Corporation||Asymmetric multiprocessor|
|US8205210||Jun 19, 2012||Comcast Ip Holdings I, Llc||Associating processes with processing elements and adjusting association|
|US8296771 *||Oct 23, 2012||Cray Inc.||System and method for mapping between resource consumers and resource providers in a computing system|
|US8473401 *||Dec 19, 2007||Jun 25, 2013||CLS Services, Ltd.||System and method for processing and settling payment instructions relating to various financial instruments|
|US8533674||Mar 31, 2009||Sep 10, 2013||Clouding Ip, Llc||Method, system and apparatus for providing pay-per-use distributed computing resources|
|US8584131 *||Mar 30, 2007||Nov 12, 2013||International Business Machines Corporation||Method and system for modeling and analyzing computing resource requirements of software applications in a shared and distributed computing environment|
|US9158355||Jun 30, 2008||Oct 13, 2015||Marvell World Trade Ltd.||Dynamic core switching|
|US9317338||Oct 21, 2013||Apr 19, 2016||International Business Machines Corporation||Method and system for modeling and analyzing computing resource requirements of software applications in a shared and distributed computing environment|
|US20030023785 *||Nov 28, 2001||Jan 30, 2003||Fujitsu Limited||Data processing program, computer readable recording medium recorded with data processing program and data processing apparatus|
|US20030055863 *||Jul 24, 2001||Mar 20, 2003||Spiegel Michael G.||Method and apparatus for managing system resources in an information handling system|
|US20030126304 *||Dec 31, 2001||Jul 3, 2003||Wyatt David A.||Method for attaching a resource to a parent within a global resource namespace|
|US20040148390 *||Sep 19, 2003||Jul 29, 2004||Cleary Geoffrey Alan||Low cost, highly accurate video server bit-rate compensation|
|US20050010924 *||Aug 6, 2004||Jan 13, 2005||Hipp Burton A.||Virtual resource ID mapping|
|US20050044547 *||Aug 18, 2003||Feb 24, 2005||Gipp Stephan Kurt||System and method for allocating system resources|
|US20070087739 *||Oct 13, 2006||Apr 19, 2007||Lg-Nortel Co., Ltd.||Wireless local loop base station controller and a method for performing call processing using the same|
|US20070198723 *||Jan 18, 2007||Aug 23, 2007||Samsung Electronics Co., Ltd.||Apparatus and method for managing resources in containment framework environment|
|US20070283128 *||Jun 5, 2007||Dec 6, 2007||Matsushita Electric Industrial Co., Ltd.||Asymmetric multiprocessor|
|US20080059719 *||Sep 6, 2006||Mar 6, 2008||International Business Machines Corporation||Determining Whether A Non-Running Processor Has Access To An Address Space|
|US20080154771 *||Dec 20, 2006||Jun 26, 2008||Philip Paul Trickey||System and method for processing and settling payment instructions relating to various financial instruments|
|US20080184258 *||Dec 17, 2007||Jul 31, 2008||Keisuke Toyama||Data processing system|
|US20080244600 *||Mar 30, 2007||Oct 2, 2008||Platform Computing Corporation||Method and system for modeling and analyzing computing resource requirements of software applications in a shared and distributed computing environment|
|US20080288748 *||Jun 30, 2008||Nov 20, 2008||Sehat Sutardja||Dynamic core switching|
|US20080301226 *||Aug 12, 2008||Dec 4, 2008||Geoffrey Alan Cleary||Low cost, highly accurate video server bit-rate compensation|
|US20090210356 *||Mar 31, 2009||Aug 20, 2009||Abrams Peter C||Method, system and apparatus for providing pay-per-use distributed computing resources|
|US20100280936 *||Dec 19, 2007||Nov 4, 2010||Cls Bank International||System and method for processing and settling payment instructions relating to various financial instrumets|
|US20110113221 *||Aug 18, 2008||May 12, 2011||Telefonaktiebolaget L M Ericsson (Publ)||Data Sharing in Chip Multi-Processor Systems|
|US20130282568 *||Jun 24, 2013||Oct 24, 2013||Cls Services Ltd.||System and method for processing and settling payment instructions relating to various financial instruments|
|US20140052432 *||Oct 17, 2013||Feb 20, 2014||Michael Deubzer||Method for a design evaluation of a system|
|CN101086722B||Jun 6, 2007||Nov 10, 2010||松下电器产业株式会社||Asymmetric multiprocessor system|
|WO2010020828A1 *||Aug 18, 2008||Feb 25, 2010||Telefonaktiebolaget L M Ericsson (Publ)||Data sharing in chip multi-processor systems|
|WO2012036954A2 *||Sep 7, 2011||Mar 22, 2012||Rambus Inc.||Scheduling amongst multiple processors|
|WO2012036954A3 *||Sep 7, 2011||Jun 28, 2012||Rambus Inc.||Scheduling amongst multiple processors|
|WO2012048402A1 *||Sep 28, 2011||Apr 19, 2012||Mosaid Technologies Incorporated||Method, system and apparatus for multi-level processing|
|WO2016022308A3 *||Jul 24, 2015||Apr 14, 2016||Qualcomm Incorporated||Directed event signaling for multiprocessor systems|
|Cooperative Classification||G06F9/4856, G06F9/5044|
|European Classification||G06F9/50A6H, G06F9/48C4P2|
|Jan 7, 1998||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MANIKUNDALAN, RAVINDRANATH K.;RAMANATHAN, JAYASHREE;REEL/FRAME:008927/0512;SIGNING DATES FROM 19971121 TO 19971124
|Sep 25, 2003||FPAY||Fee payment|
Year of fee payment: 4
|Nov 12, 2007||REMI||Maintenance fee reminder mailed|
|May 2, 2008||LAPS||Lapse for failure to pay maintenance fees|
|Jun 24, 2008||FP||Expired due to failure to pay maintenance fee|
Effective date: 20080502