|Publication number||US6086386 A|
|Application number||US 08/862,151|
|Publication date||Jul 11, 2000|
|Filing date||May 22, 1997|
|Priority date||May 24, 1996|
|Also published as||EP0901695A1, EP0901695A4, WO1997044859A1|
|Publication number||08862151, 862151, US 6086386 A, US 6086386A, US-A-6086386, US6086386 A, US6086386A|
|Inventors||Joseph Fjelstad, Thomas H. DiStefano, Konstantine Karavakis, Anthony B. Faraci, Tan Nguyen|
|Original Assignee||Tessera, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Referenced by (210), Classifications (70), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present application claims the benefit of United States Provisional Application, Ser. No. 60/018,304, filed May 24, 1996, the disclosure of which is hereby incorporated by reference herein.
The present invention relates to components useful for mounting semiconductor chips and related electronic components, to assemblies made using such components and to methods of making such components and assemblies.
Modern electronic devices utilize semiconductor chips, commonly referred to as "integrated circuits" which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip and equipped with terminals for interconnection to external circuit elements. Such substrates may be secured to an external circuit board or chassis. Alternatively, in a so-called "hybrid circuit" one or more chips are mounted directly to a substrate forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted to the substrate. In either case, the chip must be securely held on the substrate and must be provided with reliable electrical interconnection to the substrate. The interconnection between the chip itself and its supporting substrate is commonly referred to as "first level" assembly or chip interconnection, as distinguished from the interconnection between the substrate and the larger elements of the circuit, commonly referred to as a "second level" interconnection.
The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as "input-output" or "I/O" connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial numbers of I/O connections.
The size of the chip and substrate assembly is a major concern. The size of each such assembly influences the size of the overall electronic device. More compact assemblies, with smaller distances between chips provide smaller signal transmission delays and hence permit faster operation of the device.
First level interconnection structures connecting a chip to a substrate ordinarily are subject to substantial strain caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated within the chip tends to heat the chip and substrate, so that the temperatures of the chip and substrate rise each time the device is turned on and fall each time the device is turned off. As the temperatures change, the chip and substrate may expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate. This relative movement deforms the electrical interconnections between the chip and substrate and places them under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause breakage of the electrical interconnections.
Moreover, despite all of the efforts made during manufacture of the chips, some chips will be defective. These defects often cannot be detected until the chip is operated under power in a test fixture or in an actual assembly. A single bad chip can make a larger assembly including numerous chips and other valuable components worthless, or can require painstaking procedures to extricate the bad chip from the assembly. Therefore, the chips and the mounting components used in any chip assembly system should permit testing of chips and replacement of defective chips before the chips are fused to a substrate. The cost of the chip and substrate assembly is also a major concern.
All these concerns, taken together, present a formidable engineering challenge. Various attempts have been made heretofore to provide first-level interconnection structures and methods to meet these concerns. At present, the most widely utilized primary interconnection methods are wire bonding, tape automated bonding or "TAB" and flip-chip bonding.
In wire bonding, the substrate has a top surface with a plurality of electrically conductive contact pads or lands disposed in a ring-like pattern. The chip is secured to the top surface of the substrate at the center of the ring-like pattern, so that the chip is surrounded by the contact pads on the substrate. The chip is mounted in a face-up disposition, with the back surface of the chip confronting the top surface of the substrate and with the front surface of the chip facing upwardly, away from the substrate, so that electrical contacts on the front surface are exposed. Fine wires are connected between the contacts on the front face of the chip and the contact pads on the top surface of the substrate. These wires extend outwardly from the chip to the surrounding contact pads on the substrate. In wire bonded assembly, the area of the substrate occupied by the chip, the wires and the contact pads of the substrate is substantially greater than the surface area of the chip itself. Moreover, the wire bonding process does not provide any pre-testing of the chip, so that the chip must be tested using separate equipment. Thus, the bare chip must be tested using separate equipment before the wire bonding process. Testing a bare chip poses numerous practical difficulties. Thus, it is difficult to make reliable low inductance electrical connections with all of the contacts on the chip simultaneously. Elder et al, U.S. Pat. No. 5,123,850 and Jameson et al, U.S. Pat. No. 4,783,719 disclose chip testing fixtures in which conductive elements on a flexible device are pressed against electrical contacts of the chip.
In the TAB process, a polymer tape is provided with thin layers of metallic material forming conductors on a first surface of the tape. These conductors are arranged generally in a fan-out pattern and extend generally radially, away from the center of the pattern. The chip is placed on the tape in a face down arrangement, with contacts on the front surface of the chip confronting the conductors on the first surface of the tape. The contacts on the chip are bonded to the conductors on the tape. Because the leads utilized in tape automated bonding extend outwardly in a radial, fan-out pattern from the chip, the assembly is much larger than the chip itself. Enochs, U.S. Pat. No. 4,597,617 and Matta et al, U.S. Pat. No. 5,053,922 disclose variants of the TAB process in which the outer ends of the leads on the tape are placed in contact with the substrate by mechanical pressure, rather than by metallurgical bonding.
In flip-chip bonding, contacts on the front surface of the chip are provided with bump leads such as balls of solder protruding from the front surface of the chip. The substrate has contact pads arranged in an array corresponding to the array of contacts on the chip. The chip, with the solder bumps, is inverted so that its front surface faces toward the top surface of the substrate, with each contact and solder bump on the chip being positioned on the appropriate contact pad of the substrate. The assembly is then heated so as to liquefy the solder and bond each contact on the chip to the confronting contact pad of the substrate. Because the flip-chip arrangement does not require leads arranged in a fan-out pattern, it provides a compact assembly. The area of the substrate occupied by the contact pads is approximately the same size as the chip itself. Moreover, in flip-chip bonding, the contacts on the chip may be arranged in a so-called "area array" covering substantially the entire front face of the chip. Flip-chip bonding therefore is well suited to use with chips having large numbers of I/O contacts. However, assemblies made by flip-chip bonding are quite susceptible to thermal stresses. The solder interconnections are relatively inflexible, and may be subjected to very high stress upon differential expansion of the chip and substrate. These difficulties are particularly pronounced with relatively large chips. Moreover, it has been difficult to test a chip having an area array of contacts before attaching the chip to the substrate.
One solution has been the use of sockets or spring-like contacts to connect the bump leads to the substrate. As microelectronic chips have decreased in size, the pitch of the solder bump interconnections has become finer, requiring a finer pitch on mating sockets. At the same time, the mating sockets must still compensate for pitch error and height error in the solder bumps on the chip. Such accommodation for solder bump location tolerances becomes increasingly more difficult as the sockets are more tightly packed in a connector.
Sockets or contacts for connecting microelectronic elements to a substrate typically add considerable height to the chip package. Because packaging space is typically at a premium in all directions, there is a need for lower profile socket or contact connectors.
U.S. Pat. No. 3,795,037 to Luttmer discloses using a large number of separate, flexible gold wires extending through a resilient medium to a connection surface, at which the gold wires terminate. The gold wires are electrically connected on the opposite side of the resilient layer to leads in a substrate. When an array of bump leads is brought into contact with the connection surface, certain of the gold wires contact each of the bump leads, and provide conductors through the resilient layer. The resilient material and the gold wires flex upon contact by the bump leads, providing compliance.
U.S. patent application Ser. No. 08/511,131, assigned to the same assignees as the present application and hereby incorporated by reference herein, discusses sockets having metallic projections arranged circumferentially around a hole for receiving a bump lead. The metallic projections deflect as the bump lead is urged into the hole.
Kohn et al., U.S. Pat. No. 5,199,879 discloses a pin socket having a plurality of deflectable tabs projecting at least partially across an opening. Matsumoto et al., U.S. Pat. No. 4,893,172 and Noro et al., U.S. Pat. No. 5,086,337, disclose variants of the flip-chip approach using flexible spring-like elements connected between a chip and a substrate.
Nishiguchi et al, U.S. Pat. No. 5,196,726 discloses a variant of the flip-chip approach in which non-meltable bump leads on the face of the chip are received in a cup-like sockets on the substrate and bonded therein by a low-melting point material. Beaman, U.S. Pat. No. 4,975,079 discloses a test socket for chips in which dome-shaped contacts on the test substrate are disposed within conical guides. The chip is forced against the substrate so that the solder balls enter the conical guides and engage the dome-shaped pins on the substrate. Enough force is applied so that the dome-shaped pins actually deform the solder balls of the chip.
Rai et al, U.S. Pat. No. 4,818,728 discloses a first substrate such as a chip with studs or bump leads protruding outwardly and a second substrate with recesses having solder for engaging the bump leads. Malhi et al, U.S. Pat. No. 5,006,792 discloses a test socket in which a substrate has an exterior ring-like structure and numerous cantilever beams protruding inwardly from the ring-like structure. Contacts are disposed on these cantilever beams so that the same can be resiliently engaged with contacts of a chip when the chip is placed in the socket. Nolan et al, A Tab Tape-Based Bare Chip Test and Burn Carrier, 1994 ITAP And Flip Chip Proceedings, pp. 173-179 discloses another socket with cantilevered contact fingers for engaging the contacts on a chip; in this case the contact fingers are formed on a flexible tab tape and reinforced by a silicone material so as to provide forcible engagement and a wiping action with the chip contact.
Hill et al, Mechanical Interconnection System For Solder Bump Dice, 1994 ITAP And Flip Chip Proceedings pp. 82-86, discloses a test socket for flip chip devices with solder bumps. The socket has rough, dendritic structures on contact pads; here again, the chip with the solder bumps thereon is forced into the engagement with the rough, dendritic structures so as to make temporary contact for testing.
The reference "MCM to Printed Wiring Board (Second Level) Connection Technology Options" by Alan D. Knight, (in Multichip Module Technologies and Alternatives, ed. by Daryl Ann Doane and Paul D. Franzon, Van Nostrand, 1993, pp. 504-509 and pp. 521-523), together with the corresponding U.S. Patent of Evans et al, U.S. Pat. No. 4,655,519 and Grabbe, U.S. Pat. No. 5,228,861 disclose additional connection systems using deformable contacts. Despite all of these efforts in the art, however, there have still been needs for improved components for connecting semiconductor chips and other microelectronic components; for improved methods for connecting such chips and components and for improved systems which include the connected chips and components.
The present invention addresses these needs. One aspect of the invention provides a connecting assembly for connecting a microelectronic element having an array of bump leads comprises a substrate having electrically conductive leads, and a resilient, sheetlike body having first and second major surfaces. The second major surface faces the substrate and is spaced apart from the substrate. A support structure having gaps and solid portions extends between the second major surface of the sheetlike body and the substrate. An array of generally laminar contacts is secured to the first major surface of the body in registration with the array of bump leads on the microelectronic element to be mounted, and in alignment with the gaps in the support structure. Each of the contacts is surrounded by an associated portion of the sheetlike body, which is supported at its periphery by solid portions of the support structure. The portion of the sheetlike body is deflectable toward the substrate upon urging the bump leads on a microelectronic element against the corresponding contacts.
The resilience of the sheetlike body reduces the need for deflection of the metallic contacts themselves. Because the sheetlike material is more flexible than a standalone metallic contact, a contact of the invention may be smaller than an all-metallic contact having similar resilience. This makes possible a contact array having a finer pitch thus permitting a finer pitch of the bump leads on the microelectronic device.
In addition, the resilient, sheetlike body is less likely to plastically deform than an all-metallic contact. This permits the re-use of the connecting device of the invention as a test fixture that makes repeated, reliable connections with the microelectronic element.
The support structure may be an array of posts. In that embodiment, the array of posts may be electrically connected to the leads of the substrate and the contacts of the array may be electrically connected to the posts. In one embodiment, each of the deflectable portions of the body is supported by four posts. The array of contacts and the array of posts may be rectilinear arrays having row and column directions, wherein the posts are offset from the contacts in diagonal directions, oblique to the row and column directions. The posts may be solid core solder balls or may be conductive vias.
At least one post from the group of posts may electrically connect a respective contact to a lead on the substrate. The portion of the sheetlike body associated with the respective contacts deflects in response to downward forces exerted by a respective bump lead on the microelectronic element. The sheetlike body may have relief apertures in the portions associated with the contacts for increasing flexibility of the sheetlike body.
The contacts may be coated with solder in order to more readily bond with solder bumps on the microelectronic element. The connecting assembly may further comprise a conductive layer on the second major surface of the sheetlike body for controlling impedence. That layer may further include conductive traces for interconnecting the contacts, or the conductive traces may be used alone on the second major surface of the sheetlike body.
In applications where bonding is not desired between the contacts and bump leads on the microelectronic element, an anti-wetting agent may be deposited on the contacts.
The support structure may alternatively be a support layer wherein the gaps are holes, and an edge of a hole defines the periphery of the portion of the sheetlike body associated with a corresponding contact.
The sheetlike body may have a plurality of holes disposed in an array corresponding to the array of contacts, with the contacts extending inwardly over the holes. The contacts may have asperities protruding upwardly to contact the microelectronic element.
The connecting assembly may further have a frame for aligning the microelectronic element to the sheetlike body and a biasing structure for urging the microelectronic element against the sheetlike body.
In another aspect of the invention, a method is provided for making connections to the microelectronic element having an array of bump leads. A connector is provided having a sheetlike body, a substrate, an array of contacts on a first major surface of the sheetlike body, and an array of posts on a second major surface of the sheetlike body. The posts space the sheetlike body away from the substrate. Each of the contacts are on a portion of the sheetlike body having at its perimeter two or more of the posts.
The microelectronic element is aligned with the connector so that the array of contacts is in registration with the array of bump leads. The microelectronic element is then urged toward the sheetlike body so that the array of bump leads contacts the array of contacts, and each portion of the sheetlike body is resiliently deflected between two or more posts and a bump lead.
Each of the contacts may be electrically connected to one of the posts, and the posts may be electrically connected to the leads in the substrate, so that by urging the microelectronic element toward the sheetlike body, an electrical connection is made between the bump leads and the leads in the substrate.
After electrically connecting the leads to the substrate, the microelectronic element may be electrically tested through the electrical connection to determine whether the microelectronic element is acceptable. If the element is acceptable, the contacts may be bonded permanently to the bump leads.
In another embodiment of the invention, a connector is provided for mounting a microelectronic element to a substrate. The connector comprises a resilient, sheetlike body having first and second major surfaces, and a plurality of generally laminar contacts secured to the first major surface of the body. The contacts are disposed in an array corresponding to an array of bump leads on the microelectronic device to be mounted. Each contact is adapted to engage a corresponding bump lead. The connector further comprises an array of terminal posts on the second major surface of the sheetlike element. The terminal posts are electrically connected to the contacts. The terminal posts can thus be bonded to a substrate to electrically connect the contacts to the substrate, and to support the body with a stand-off space between the body and the substrate. To electrically connect the microelectronic element to the substrate, the microelectronic element is urged against the body so that bump leads on the element are engaged by contacts on the body, and portions of the body surrounding the contacts are resiliently deflected into the stand-off space.
The sheetlike body may have a plurality of holes disposed in an array corresponding to the array of bump leads on the microelectronic element, and each of the contacts may extend inwardly over one of the holes from the first major surface. Each contact may further include at least one projection extending over the hole associated with that contact. The contact may further include a plurality of projections extending inwardly from circumferentially spaced locations around the hole.
The connector may further have a protective layer formed over the leads. The terminal posts may be solid core solder balls.
The sheetlike body may have a plurality of holes corresponding to the terminal posts, the terminal posts being electrically connected to the contacts through the holes. The electrical connection may be made by a plurality of laminar contact tabs on the first surface of the sheetlike body.
The array of contacts and the array of terminal posts may be rectilinear arrays having row and column directions, and the terminal posts may be offset from the contacts in diagonal directions, oblique to the row and column directions.
The connector may further have support posts that are not electrically connected to any contact for further supporting the body.
In a further embodiment of the invention, a socket is provided for engaging a bump lead on a microelectronic element. The socket has a resilient, dielectric sheet with first and second major surfaces, and an electrically conductive contact secured to the first major surface of the sheet. The contact has an active contact portion. The socket further comprises a supporting substrate for the first surface, the substrate first surface being juxtaposed with the dielectric sheet's second major surface. The substrate first surface has a conductive terminal thereon. A plurality of posts are spaced around the active contact portion. The posts mechanically support a portion of the sheet surrounding the contact with respect to the substrate such that there is a gap between the sheet and the substrate. One of the posts electrically connects the terminal and the contact. The sheet deflects when the bump lead is engaged with the active contact portion of the contact.
An aperture may extend between the first and second major surfaces of the sheet. The active contact portion of the contact is aligned with the aperture and extends partially over the aperture.
The posts may be solid core solder balls, or may be vias. A spacer may be positioned between each of the posts and the first surface of the substrate, wherein the spacer electrically connects the post to the substrate and provides greater vertical height for deflection of the sheet. The spacer may include a laminar substrate having an aperture aligned with the active contact portion of the contact.
The socket may further comprise a second contact and a second plurality of posts mechanically supporting the second portion of the sheet surrounding a second active contact portion of the second contact. In this case, the first plurality of posts and the second plurality of posts have at least one post in common. The flexible sheet in that case may further include a conductive layer secured to the second major surface and interconnecting the first and second contacts.
The foregoing and other objects, features and advantages of the present invention will be more readily apparent from the detailed description of the preferred embodiments set forth below, taken in conjunction with the accompanying drawings.
FIG. 1 is a diagrammatic plan view of a connecting assembly with connectors in accordance with one embodiment of the invention;
FIG. 2a is a fragmentary plan view depicting a portion of a connector for use in the connecting assembly of FIG. 1;
FIG. 2b is a fragmentary plan view depicting a portion of a connector of another embodiment for use in the connecting assembly of FIG. 1;
FIG. 3 is a partial cross-sectional view of the connecting assembly illustrated in FIG. 1 taken along line III--III, together with a microelectronic element to be mounted;
FIG. 4 is a diagrammatic sectional view of the connecting assembly shown in FIG. 1 taken along line IV--IV, together with a microelectronic element to be mounted;
FIG. 5 is a schematic plan view of a connector in accordance with another embodiment of the invention;
FIG. 6 is a diagrammatic sectional view of a connecting assembly in accordance with one embodiment of the invention;
FIG. 7 is a diagrammatic exploded view of the connecting assembly of FIG. 6;
FIG. 8 is a diagrammatic exploded view of a connecting assembly in accordance with another embodiment of the invention;
FIG. 9 is a diagrammatic perspective view of a substrate comprising a portion of a connecting assembly in accordance with one embodiment of the invention;
FIG. 10 is a diagrammatic sectional view of a connecting assembly according to another embodiment of the invention, together with a microelectronic element to be mounted;
FIG. 11 is a diagrammatic plan view of a connecting assembly with connectors in accordance with another embodiment of the invention;
FIG. 12 is a perspective, diagrammatic partial cross-sectional view of a connecting assembly according to one embodiment of the invention;
FIG. 13 is a perspective, diagrammatic partial cross-sectional view of a connecting assembly according to another embodiment of the invention;
FIG. 14 is a diagrammatic partial cross-sectional view of a connecting assembly according to another embodiment of the invention;
FIG. 15 is a diagrammatic plan view of a connecting assembly with connectors in accordance with another embodiment of the invention;
FIG. 16 is a diagrammatic sectional view of a connecting assembly according to another embodiment of the invention, together with a microelectronic element to be mounted; and
FIG. 17 is a diagrammatic sectional view of a connecting assembly according to another embodiment of the invention, together with a microelectronic element to be mounted.
A connecting assembly 5 (FIG. 3) according to on e embodiment of the present invention includes a connector or interposer 10, a substrate 41 and a support structure with solid portions such as noncollapsible structural elements or posts 23 supporting the connector 10 above the substrate 41. The substrate 41 (FIG. 9) in this arrangement is a multi-layer laminated circuit panel with numerous electrical leads 50, of which only a few are schematically indicated. Leads 50 extend in mutually orthogonal, horizontal directions parallel to the top and bottom surfaces of the substrate. In accordance with 3 conventional semi-conductor industry practice, the horizontal directions are referred to as the "x" and "y" directions. Further, the direction `upward` as used herein refers to the direction from the substrate toward the microelectronic element to be mounted, with the microelectronic element being `above` or `on top of` the substrate.
The substrate further includes vertical or z-direction leads 52 interconnecting the various horizontal leads 50. Some of the z-direction leads, as well as possibly some horizontal leads 50, are exposed at the top surface 43 of the substrate 41. These exposed leads are connected to terminals 42 (FIG. 3) disposed in a rectilinear grid of uniform pitch in the x- and y- directions. Terminals 42 may include, for example, flowable conductive materials such as solders, eutectic bonding alloys, polymeric materials with metallic fillers and the like, and they may also include structures such as vertically extensive vias. The substrate is formed principally from dielectric materials supporting and insulating the leads. Substrate 41 may also include other elements conventional in multi-layer circuitry, such as ground and power potential planes and the like.
A connector 10 according to the invention for connecting substrate 41 to a microelectronic element includes a sheetlike dielectric connector body 24 (FIGS. 1, 3) having a first surface 32 facing upwardly, away from the substrate 41, and a second surface 33 facing downwardly, toward the substrate. Thus, the second surface 33 of the sheetlike body 24 faces the top surface 43 of the substrate 41. According to the presently described embodiment, the sheetlike element 24 has numerous holes 27 extending through it from the first surface 32 to the second surface 33. The connector body 24 is desirably less than about 100 microns thick, and more desirably less than about 50 microns thick. In a preferred embodiment, the sheetlike element is between about 25 and 40 microns in thickness. To provide centering forces as further discussed hereinbelow, the diameter of the hole 27 should be slightly smaller than the diameter of the bump leads of the microelectronic element to be connected.
As shown in FIGS. 1-3, an elongated metallic contact tab 21 is associated with each hole 27. Each contact tab overlies the first surface 32 of the connector body 24. Each contact tab includes an active contact portion 22 comprising a ring-like structure at one end of the tab 21 encircling the opening of the hole 27, and a plurality of projections 28 extending inwardly from the ring-like structure. The projections 28 protrude over the opening of the hole 27 (FIG. 29). The projections are separated from one another by slots 31 (FIG. 2a). The projections 28 of each contact tab 21 cooperatively define the active contact portion 22 overlying the hole 27.
The holes 27 and the associated contact tabs 21 are arranged on the top surface 32 of the sheetlike body 24 in a rectilinear grid array, as shown in FIG. 1. The grid array of active contact portions 22 corresponds with a grid array of contacts such as solder bumps 46 (FIG. 3) on a microelectronic element 45 to be connected.
Each contact tab 21 extends to a noncollapsing structural element or post 23 connected to the contact tab 21 through the sheetlike body 24. In a preferred embodiment, holes 40 (FIG. 3) are provided in sheetlike body 24, exposing an undersurface of the contact tabs 21. The posts 23 are bonded directly to the contact tabs 21 through the holes.
As seen in FIG. 1, the active contact portions 22 and the holes 27 are arranged in rows extending in the x-direction and columns extending in the y-direction. Each contact tab 21 is arranged at an oblique angle, at 45 degrees to the x-direction (and hence 45 degrees to the y-direction), so that each post 23 is offset in this oblique direction from the active contact portion 22 and hole 27. Thus, the posts 23 are also arranged in a rectilinear array of rows and columns extending in the x- and y- directions, but this array is offset from the array of holes 27 and active contact portions 22.
The pitch or spacing of the posts 23 on the connector 10 matches the spacing of the terminals 42 on the top surface 43 of the substrate 41. The posts 23 are bonded to the z-leads 52 (FIG. 3), making an electrical and mechanical connection between the contact tabs 21 in the connector 10 and the leads 50, 52 in the substrate 41.
The rectilinear arrays can have essentially any pitch or spacing between adjacent elements. Preferably, however, the pitch of each array is a pitch which corresponds to a standard pitch for contacts on the surfaces of microelectronic elements such as semi-conductor chips having "array area" contacts. Microelectronic elements having contacts with a pitch of about 0.5 mm or less between adjacent elements as measured along a row or along a column are known.
Contact tabs 21, and the projections 28 incorporated therein, are generally laminar. As used in this disclosure, the term "laminar" means sheet-like or plate-like. That is, a laminar structure has two oppositely-directed major faces and has edges, the major faces having surface areas substantially greater than the surface areas of the edges. A laminar structure is not necessarily planar. For example, the laminar structures may have bumps or asperities projecting upwardly from their top surfaces. Contact tabs 21 may be formed from metallic materials, preferably those having good electrical conductivity and good processing properties in etching and plating processes such as those commonly used for microelectronic components. Materials which can be used include copper and copper bearing alloys such as beryllium copper and phosphor bronze. The metal of the contact tab and of the projection is between about 10 and 50 microns thick, and more desirably between about 10 and 25 microns thick. Standard lithographic processing techniques may be used to fabricate the contact tabs. The dimensions of the components will vary somewhat depending upon the pitch selected and the nature of the microelectronic components to be engaged with the connector. However, for a system having a pitch of about 0.75 mm, the width w of each contact tab (FIG. 2a) is about 0.45 mm, whereas as the length 1 between the center of the active contact 22 and the center of the post 23 may be about 0.53 mm. The hole in the sheetlike element 24 below the active contact area 22 is about 0.35 mm in diameter, and the projections 28 extend over the hole 27 approximately 50 microns per side.
The contact tabs 21 are preferably covered by a solder mask or coverlay layer 37 (FIG. 3) to protect the underlying copper tabs during bonding to a microelectronic element 45 so that solder from the connection is not wicked away by the tab 21, and so that adjacent tabs are not bonded together. The coverlay layer 37 also protects the underlying copper tabs during testing of a microelectronic element in the event that solder in the microelectronic element liquefies during testing. The coverlay 37 has a hole 38 in the active contact area 22 to expose the overlying projections 28 of the metallic contact tabs 21.
The contact tabs 21, including the overlying projections 28, may further be covered with an anti-wetting agent. For example, osmium, rhodium, rhenium, graphite or another suitable substance may be electroplated onto the contacts 22 (or possibly the projections 28 only) in order to prevent solder from wetting the contacts. The anti-wetting agent permits the connector assembly to be used as a socket for burn-in and testing of a microelectronic element at high test temperature ranges, which may be as high as 150° C. Under these conditions, solder in the bump leads may liquefy or soften, and may bond to the contacts in the absence of an anti-wetting agent.
On the other hand, it is desirable to encourage solder wetting of the contact tabs 21 in those embodiments wherein a permanent solder joint is to be formed between the bump leads 46 of the microelectronic element 45 and the connector 10. In that case, the projections 28 of the contact tabs 21 are tinned or coated with solder in order to facilitate solder joining to the mating bump leads 46. The mechanical and electrical connections between the microelectronic element 45 and the contact tabs 21 are made permanent by cycling the assembly including the microelectronic element and the connector through a soldering temperature cycle. During the soldering process, the solder that is initially on the projections 28 is melted and flowed onto the bump leads 46 of the microelectronic element. The solder wets the projections 28 of the contacts and joins them to their respective bump leads, allowing the projections to penetrate the bump leads in the case where the bump leads 46 comprise a flowable solder ball, such as eutectic Sn-Pb solder.
A ground or power plane layer 61 may be provided on the bottom surface 33 of the flexible sheet 24, as shown in FIG. 3. Such a layer comprises a solid layer covering all or substantial portions of the bottom surface 33 of the flexible layer 24. Depending on the requirements of the individual connector, the layer 61 may comprise a ground layer in some regions of the connector, and a power plane layer in other regions of the connector, wherein the regions are electrically isolated by gaps in the layer 61. The layer 61 may be used to control impedance in the microelectronic element 45 and in the connector 10 and substrate 41.
Alternatively, the layer 61 may comprise a plurality of conductive traces that electrically interconnect selected contacts in a test pattern, or for providing additional interconnections supplementing those in the substrate 41. In one example of such an embodiment, conductive traces within the layer may be used for connecting two or more posts 23 with a single solder bump 46 on a microelectronic element. This may be done by directly interconnecting the posts 23 using conductive traces in the layer 61. Alternatively, the leads 21 could be interconnected to the conductive traces by vias (not shown) through the flexible layer 24. In either case, a significant quantity of test circuitry may be included in the layer 61 for the testing of a microelectronic element 45. Finally, the layer 61 may comprise a combination of interconnecting conductive traces in certain areas where such traces are needed, and ground or power plane regions in other areas where interconnecting conductive traces are not needed.
The post 23 preferably comprises a solid core solder ball having a solid core 35 of an electrically conductive, relatively high-melting-point material such as copper or nickel, surrounded by a layer of electrically conductive, heat activatable bonding material 36 such as solder. By making the connection between the connector 10 and the substrate 41 using an array of solid core solder balls, standard ball grid array processes and equipment may be used to assemble those components.
Thus, when the posts 23 are bonded to the contact tab 21 and to the leads 52 in the substrate 41, the solid core 35 remains intact, forming a standoff space 57 (FIG. 3) between the top surface 43 of the substrate 41 and the second surface 33 of the sheetlike element 24. The standoff space 57 has a predetermined thickness 58 established by the size of the noncollapsing portion of the post 23; i.e., by the diameters of cores 35.
In another embodiment of the invention shown in FIG. 16, a via 366 is used in place of the solid core solder ball to form a post. The via 366 comprises a hollow, substantially cylindrical or hourglass-shaped post formed from copper, gold, other conductive material or alloys thereof. The via may alternatively be shaped as another surface of revolution, such as a cone or a barrel-shaped element. The via 366 extends through an aperture 365 in the contact tab 321, and through an aperture 340 in the flexible sheet 324. The via terminates above the contact tab 321 with a flange 368 in contact with the tab. The tab and the via are in electrical contact. The via extends downward below the flexible sheet 324 a fixed distance 358, which establishes the stand-off distance between the connector 310 and a substrate 341. The via 366 terminates in a lower wall 369 to form a cup-shaped element. In use, the connector 310 is connected to the substrate 341 by soldering an array of vias 366 onto a corresponding array of terminals 342 on the substrate 341.
Vias, such as via 366, may be formed by using a sacrificial layer (not shown) of resist or other suitable material. The sacrificial layer has an aperture in registry with the aperture 340 in the flexible layer 324 and the aperture 365 in the contact tab 321. The three apertures are formed concurrently in order to assure alignment. After forming the apertures, an additional sacrificial layer (not shown) is applied over the first sacrificial layer in order to form a lower wall 369 in the via 366. After appropriately masking the upper surface of the contact tabs 321, the via is formed in a conventional manner by plating the sides and bottom of the aperture, together with a small area surrounding the aperture on the contact tab 321. The sacrificial layers are then removed, leaving the residual via 366. A solder mask layer 337 may be formed over the contact tab 321 and upper flange 368 of the via 366.
In another version of the connector, shown in FIG. 17, the via 370 is inverted with respect to the embodiment of FIG. 16. In this embodiment, no aperture is necessary in the contact tab 372, and only a single sacrificial layer (not shown) need be formed in order to form the via 370. The via 370 is formed by plating an aperture in the sacrificial layer from the side opposite the contact tab 372.
While the embodiments of FIGS. 16 and 17 incorporating a via as a post have good structural integrity, additional resistance to crushing in the z-direction may be provided by filling the via with solder, or any other suitable material. In the embodiment shown in FIG. 17, the solder 371 also provides a bonding material for bonding to substrate terminal 342. Alternatively, a more compliant material may be placed within the via in order to prevent crushing or buckling of the via walls while at the same time providing some resilience to absorb thermal cycling and other forces. For example, a polymer, a high durometer elastomer, a conductive elastomer or other suitable material may be provided within the via.
Each of the contact tabs 21 is connected to a lead 52 in the substrate 41 through one of the posts 23 as described above. Additional noncollapsing structural elements 25, 26 (FIG. 1), that do not serve as conductors, may also be provided in order to further support the connector 10 above the top surface 43 of the substrate 41. For example, some contact tabs may be omitted at locations where the microelectronic package is missing bump leads. In such a location in the regular grid pattern of the connector 10, non-collapsing structural elements 26 may be provided solely for the purpose of supporting the connector 10. Further, additional noncollapsing structural elements 25 may be provided around the periphery of the grid array of contact tabs 21 in order to provide support for the connector 10 at the periphery. Additional metal elements 30 formed from the same thin metal as the contact tabs may be provided on the connector above each additional noncollapsing structural element 25, 26, in order to provide a bonding surface for the post. The additional metal elements 30 may be formed as one or more large linear elements or buses.
Each active contact portion (or `contact`) 22 of the grid array of FIG. 1 is located at the center of a surrounding portion 60 of the resilient connector 10, which, in turn, is supported by four posts (FIGS. 1, 4). Even the corner socket 53, shown in the lower left hand corner of FIG. 1, is disposed within an array of three peripheral posts 25 and a post 23 associated with the corner socket 53. Other grid array systems, wherein each active contact portion 22 is supported by two, by three, by four or by five or more posts 23, may also be employed. Thus, a single post typically provides an electrical connection for a socket and mechanical support for a plurality of adjacent sockets.
In a connection method according to the invention, a microelectronic element such as element 45 (FIGS. 3, 4) is engaged with the connector assembly 5. The microelectronic element 45 has a plurality of bump leads 46, each protruding from the bottom surface 49 of the element 45. The bump leads are disposed in a rectilinear grid having the same pitch as the grid of active contact portions 22 (FIG. 1). In this regard, although the bump leads should be dispersed only at the locations defined by such grid, there is no requirement that a bump lead be present at every such location. That is, the grid of bump leads need not be fully populated. For example, the bump leads may be disposed at every other location, every third location and so forth, so that the populated bump lead locations have an effective pitch of 2, 3 or some other integral multiple of the pitch of the holes in the connector.
Each bump lead 46 is in the form of a generally spherical ball, similar in construction to posts 23, electrically connected to the internal circuitry of the element 45. Each bump lead may include an internal sphere or core formed from an electrically conductive, relatively strong metal such as copper or nickel. Each sphere, in turn, is covered with a layer of electrically conductive, heat activatable bonding material such as solder.
Microelectronic element 45 is engaged with the connecting assembly 5 by bringing the microelectronic element 45 into proximity with the connecting assembly so that the contact bearing surface 49 of the element 45 is juxtaposed with the top surface 32 of the sheetlike element 24. The microelectronic element 45 is positioned so that the array of bump leads 46 is in rough registration with the array of active contact portions 22 of the contact tabs 21 (FIG. 3). The microelectronic element 45 is then urged downward so that the bump leads 46 contact the projecting portions 28 of the contact tabs 21. The metal corners of the projections 28 contact and wipe against the solder bump 46. While scraping or wiping contact between the projections 28 and the solder bump 46 may not be necessary to electrically connect the two components, it increases reliability by penetrating any oxide layer that may have formed on the connecting surfaces.
As downward motion of the microelectronic element 45 relative to the connecting assembly 5 continues, connector 10 is deflected between the solder bumps 46 and the noncollapsing structural elements 23 (FIG. 4). The sheetlike element 24 resiliently deforms, with each solder bump 46 resiliently deflecting a surrounding portion 60 of the sheetlike element 24 downward into the standoff space 57 between the sheetlike element and the substrate 41.
Each portion 60 surrounding an active contact area 22 on the connector 10 has, at its periphery, a group of at least two, and more preferably three, supporting posts 23. In the currently most preferred embodiment, shown in FIG. 1, the periphery of surrounding portions 60 includes a group of four posts 23. As the surrounding portion 60 of the sheetlike element 24 is deflected into the standoff space 57, the sheetlike element is stretched. The posts force the sheetlike element 24 upward, and the bump leads 46 force the sheetlike element downward. The resilience of the sheetlike element 24 maintains contact between the protruding portions 28 of the contact tab 21 and the bump lead 46.
The resilience of the sheetlike element provides tolerance for misalignment and position errors in the array of bump leads 46, and in the array of active contacts 22. For example, as shown in FIG. 3, the centerline 47 of the bump lead 46 may not be properly aligned with the center line 29 of the active contact 22. The misalignment 48 is accommodated by asymmetric deflection of the surrounding portion 60 of the sheetlike element 24. The resiliency of the sheetlike element also compensates for unevenness in the heights of the individual bump leads 46 on the microelectronic element 45.
Furthermore, some self-centering forces are exerted on the bump leads 46 as a result of the socket-like qualities of the active contacts 22. Thus, a slightly misaligned microelectronic element will be urged to a position wherein the bump leads are better aligned with the active contacts 22 as the microelectronic element is forced downward onto the connector 10.
Because resiliency in the connector 10 results from a resilience of the sheetlike element 34 in addition to elastic deformation of the metallic contact tabs 21, the connector 10 is less likely to be plastically deformed through use than are connectors of the prior art. For this reason, the connector 10 and connecting assembly 5 are particularly suitable as reusable test fixtures for testing microelectronic elements. The connector assembly 5 may also be used as a permanent mount for microelectronic elements, by activating the bonding component of the bump leads 46, permanently bonding the microelectronic element to the connector assembly 5.
The connector of the invention is especially suited for testing and then selectively bonding microelectronic elements during the assembly process. In this application, the microelectronic element is first urged against the connector of the invention using a first force F1, sufficient to make contact between each bump lead and a corresponding socket. The microelectronic element is then tested. If the microelectronic element is rejected, it is removed from the connector and replaced with another microelectronic element. If the microelectronic element passes the test, it is then urged against the connector with a second force F2, greater than force F1, that actually inserts each bump lead into a respective socket. The bump lead may then be bonded to the connector, without interrupting contact between the connector and the microelectronic element. A connector having a somewhat larger aperture 27 in the dielectric layer is provided for this application, in order to permit the bump lead to penetrate the socket. The connector assembly of the invention is especially suited for this application because of its low profile as compared with typical test fixtures, making is suitable as a permanent connector for the microelectronic assembly.
In another embodiment of the invention, shown in FIG. 15, a connector 210 has a flexible layer 224 with a grid array of holes 227, and a corresponding array of contact tabs 221 in registry with the holes 227. In an active contact portion 222 of each contact tab 221, a plurality of projections 228 extends inwardly, protruding over the opening of the hole 227. The contact tabs are generally elongate, and further have a connection portion 230 extending over a hole 240 in the flexible sheet 224. The hole 240 exposes the connection portion 230 for connecting the contact tab 221 to a post (not shown) as described above.
The flexible sheet 224 is further provided with a plurality of arcuate slots or relief apertures 263 surrounding the active contact portion 222. The arcuate slots define bridges of the flexible layer 224 between the slots for providing support to the areas surrounding the active contact portion 222. The arcuate slots 263 provide additional flexibility and elasticity to the flexible layer 224 in the immediate vicinity of the active contact portions 222. Such additional flexibility permits relative movement of the individual contact portions 222 during engagement with solder bump leads on a microelectronic element, and during thermal cycling of the substrate and the microelectronic element.
The contact tab 221 further comprises a necked-down portion 262 between the active contact portion 222 and the connection portion 230 of the contact tab 221. The necked-down portion allows closer placement of the surrounding arcuate slots 263, and reduces the cross sectional area of the stiffer contact tab 221. Both of these effects increase the flexibility of the region of the connector 210 immediately surrounding the active contact portion 222.
The contact tab may have other configurations than that shown in FIG. 2a. For example, a contact tab 21a (FIG. 2b) may have rounded overlying projections 28a separated by rounded slots 31a. The gradually curved features of this embodiment have increased manufacturability because of the natural tendency of photolithography and etching processes to produce rounded corners.
In another example, contact tab 70 (FIG. 5) increases in width from a relatively small width where it makes contact with the post 23 to a relatively large width to surround the hole in the flexible sheetlike element 24. The projections 71 comprise curved arms configured to scrape the bump lead as the bump lead is forced downward toward the sheetlike element 28. Other contact projection configurations and contact tab geometries may also be used as is known in the art.
The contact tab may have features in addition to or in place of contact projections in order to enhance contact between the contact tab and the solder bump of the microelectronic element. For example, contact tab 90 (FIG. 10) has asperities 91 facing upward away from the sheetlike body 24. Such asperities are described in commonly assigned U.S. Pat. No. 5,632,631, which is hereby incorporated in its entirety herein. The asperities 91 may have sharp edges or corners on upper surfaces thereon. As the microelectronic element 25 is urged against the connector, the asperities 91 penetrate any oxide coating that may exist on the solder bump 46, providing a reliable electrical connection. The resiliency of the sheetlike layer 24 assures that contact is made between each of the solder bumps 46 and the associated asperities on the connector. In certain applications, such as the embodiment shown in FIG. 10, the hole in the active contact region through the sheetlike element 24 may be eliminated. Asperities may alternatively be used in conjunction with projecting portions of the contact extending over a hole in the sheetlike body 24.
Electrical connection between the contact tabs and the substrate need not be made through one of the posts 23 near that active contact. Instead, circuit traces 96 (FIG. 11) on the sheetlike element 24 may lead to contacts 97 on the periphery of the sheetlike element 24, where electrical connections between the substrate and contacts 95 may be made.
In another embodiment of the invention, the support structure is a support layer 101 (FIG. 12) between the sheetlike body 110 and the substrate 41. The support layer may be a dielectric such as polyimide or another suitable material. The support layer 101 has gaps such as hole 103, and solid portions 111. Active contact portions 105 of the contact tabs 107 are located immediately above the holes 103 in the support layer 101. The perimeter of the hole 103 defines a portion 120 of the sheetlike body 110 associated with an active contact portion 105. Upon contact with a solder bump (not shown), the active contact portions 105 move into the hole 103 as the associated portion 120 of the sheetlike element 110 deflects downward.
Electrical connection is made between the active contact portion 105 and terminals 42 in the substrate 41 by connecting the contact tab 107 to a via 109 in the sheetlike body 110. The via 109 has an electrical conductor extending therethrough, making electrical contact with a ring-like electrical conductor 102 which may be formed by plating the inside of the hole 103 in the support structure 101. The ring-like structure 102 electrically connects the via 109 with the terminal 42 in the substrate 41.
A hole 115 in the flexible sheet 110, in combination with protruding portions 106 of the active contact area 105, provide for wiping/scraping of the solder bumps as the contact is deflected downward.
In another embodiment of the invention (FIG. 13), the support layer 101 has a metallic, ring-shaped conductor 102 connected to a terminal 42 in the substrate 41 as described above. The electrical connection between the contact tab 130 and the conductor 102, however, is made through the hole 115 to connect in the sheetlike element 110. A conductor 131 is formed in the hole 115, for example by plating, to connect the contact tab 130 with a lead 132 on the second surface of the sheetlike element 110, opposite the contact tab 130. Electrical contact is therefore made between the contact tab 130 and the terminal 42 through the conductor 131, the lead 132 and the conductor 102.
Additional travel for deflection of the sheetlike element 24 may be provided by spacing the support structure such as posts 23 away from the substrate 41 using a glue layer or other spacing layer 150 (FIG. 14). The spacing layer 150 has a hole 152 in registry with the active contact portion 22 of the contact tab 21. When a solder bump (not shown) deflects the sheetlike layer 24 toward the substrate 41, the hole 152 provides additional clearance for additional downward travel. Similar results may be had by forming the hole 152 directly in the substrate. Such a configuration further reduces the height of the total assembly.
The connector of the invention may be used in conjunction with a biasing fixture 80 according to another embodiment of the invention (FIGS. 6, 7). The connector 10 is aligned with and bonded to the array of terminals 42 and the substrate. In this embodiment, the frame 70 compresses the outer periphery of the connector 10 against the substrate 41. The frame may be attached to the substrate 41 by means of pins 72 that pass through the frame 70 into holes (not shown) provided in the substrate 41. The holes provided for pin 72 are in registry with the array of terminals in the substrate, and therefore in registry with contacts 22 on the connector 10. The frame 70 is therefore aligned with the contacts.
A window 71 in the frame 70 is provided for aligning the microelectronic element 45 with the contacts in the connecting element 10. The microelectronic element 45 is urged against the connecting element 10 by a leaf spring 73 having a bowed portion 74. The leaf spring is retained in a cover 76 by two pins 75. The cover 76 may be removably attached to the frame 70 by engaging slotted holes 77 in the cover with the he ads of pins 72. With the cover 76 in place, the leaf spring 73 urges the microelectronic element 45 against the connector 10, deflecting the sheetlike element 24 as described above. The microelectronic element is thereby electrically connected to the substrate 41 for testing, burning, bonding or permanent use.
In another fixture as shown in FIG. 8, a frame 80 has a window 82 for locating the microelectronic element 45 with respect to the connector 10. A cover element 83 has a larger, clearance window to provide access for insertion of the microelectronic element 45 into the window 82 in the frame 80. The frame and the cover are attached to the substrate 41 by means of screws 81. In addition, the frame may be precisely located by means of dowels (not shown) extending through the substrate and the frame. After insertion of the microelectronic element 45 into the window 82, a spring clip 84 is clipped over the cover 83. A protruding portion 85 of the spring clip 84 urges the microelectronic element 45 against the connector 10, completing the electrical connection between the microelectronic element 45 and the substrate 41.
As will readily be appreciated, numerous other variations and combinations of the features discussed above can be used without departing from the present invention. For example, the holes 27 in the sheetlike element 24 may be eliminated, and active contact 22 may comprise a continuous portion of the contact tab 21 in the area where the bump lead 46 contacts the connector 10. While such a configuration does not provide the self-centering and scraping features of the preferred embodiment, fewer process steps are necessary in fabrication. Further, the support structure between the sheetlike layer and the substrate may comprise a plurality of metallic rings, each ring centered around an active contact portion of a contact tab.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of principles and applications of the present invention. For example, the posts or spacers may be fabricated from a compliant, conductive material such as silver-filled epoxy or another material having suitable structural integrity, thereby providing additional compliance between the sockets and the underlying substrate. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5053922 *||Aug 31, 1989||Oct 1, 1991||Hewlett-Packard Company||Demountable tape-automated bonding system|
|US5086337 *||Sep 13, 1988||Feb 4, 1992||Hitachi, Ltd.||Connecting structure of electronic part and electronic device using the structure|
|US5133495 *||Aug 12, 1991||Jul 28, 1992||International Business Machines Corporation||Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween|
|US5152695 *||Oct 10, 1991||Oct 6, 1992||Amp Incorporated||Surface mount electrical connector|
|US5199879 *||Feb 24, 1992||Apr 6, 1993||International Business Machines Corporation||Electrical assembly with flexible circuit|
|US5282312 *||Dec 31, 1991||Feb 1, 1994||Tessera, Inc.||Multi-layer circuit construction methods with customization features|
|US5430614 *||Nov 8, 1993||Jul 4, 1995||Particle Interconnect Inc.||Electrical interconnect using particle enhanced joining of metal surfaces|
|US5474458 *||Jul 13, 1993||Dec 12, 1995||Fujitsu Limited||Interconnect carriers having high-density vertical connectors and methods for making the same|
|US5615824 *||Mar 24, 1995||Apr 1, 1997||Tessera, Inc.||Soldering with resilient contacts|
|US5723347 *||Oct 24, 1996||Mar 3, 1998||International Business Machines Corp.||Semi-conductor chip test probe and process for manufacturing the probe|
|US5784262 *||Nov 6, 1995||Jul 21, 1998||Symbios, Inc.||Arrangement of pads and through-holes for semiconductor packages|
|US5811982 *||Mar 12, 1996||Sep 22, 1998||International Business Machines Corporation||High density cantilevered probe for electronic devices|
|US5812378 *||Aug 4, 1995||Sep 22, 1998||Tessera, Inc.||Microelectronic connector for engaging bump leads|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6208156 *||Sep 3, 1998||Mar 27, 2001||Micron Technology, Inc.||Test carrier for packaging semiconductor components having contact balls and calibration carrier for calibrating semiconductor test systems|
|US6249135 *||Mar 16, 1999||Jun 19, 2001||Fujitsu Limited||Method and apparatus for passive optical characterization of semiconductor substrates subjected to high energy (MEV) ion implantation using high-injection surface photovoltage|
|US6298552 *||Feb 10, 2000||Oct 9, 2001||Hon Hai Precision Ind. Co., Ltd.||Method for making socket connector|
|US6303408||Feb 3, 1999||Oct 16, 2001||Tessera, Inc.||Microelectronic assemblies with composite conductive elements|
|US6316952 *||May 12, 1999||Nov 13, 2001||Micron Technology, Inc.||Flexible conductive structures and method|
|US6359455 *||Feb 23, 2000||Mar 19, 2002||Tokyo Electron Limited||Probing card|
|US6375475 *||Mar 6, 2001||Apr 23, 2002||International Business Machines Corporation||Method and structure for controlled shock and vibration of electrical interconnects|
|US6388895 *||Apr 26, 2001||May 14, 2002||Ching Feng Blinds Ind. Co., Ltd.||Telecommunication main distribution frame structure|
|US6417027||Aug 24, 2000||Jul 9, 2002||Micron Technology, Inc.||High density stackable and flexible substrate-based devices and systems and methods of fabricating|
|US6437591 *||Mar 25, 1999||Aug 20, 2002||Micron Technology, Inc.||Test interconnect for bumped semiconductor components and method of fabrication|
|US6443750||Aug 3, 2000||Sep 3, 2002||Fci Americas Technology, Inc.||Electrical connector|
|US6450824 *||Aug 3, 2000||Sep 17, 2002||Fci Americas Technology, Inc.||Connector including movable cover|
|US6500528 *||Apr 27, 2000||Dec 31, 2002||Tessera, Inc.||Enhancements in sheet processing and lead formation|
|US6511347 *||Jun 28, 2001||Jan 28, 2003||International Business Machines Corporation||Terminating floating signals on a BGA module to a ground plane on a ball grid array (BGA) circuit board site|
|US6565364 *||Dec 22, 1999||May 20, 2003||Mirae Corporation||Wafer formed with CSP device and test socket of BGA device|
|US6573610 *||Jun 2, 2000||Jun 3, 2003||Siliconware Precision Industries Co., Ltd.||Substrate of semiconductor package for flip chip package|
|US6602431||Nov 15, 2002||Aug 5, 2003||Tessera, Inc.||Enhancements in sheet processing and lead formation|
|US6617671 *||Jun 10, 1999||Sep 9, 2003||Micron Technology, Inc.||High density stackable and flexible substrate-based semiconductor device modules|
|US6628133||Nov 26, 2002||Sep 30, 2003||Micron Technology, Inc.||Methods of testing integrated circuitry|
|US6661247||Apr 9, 2001||Dec 9, 2003||Fujitsu Limited||Semiconductor testing device|
|US6687978||Dec 15, 2000||Feb 10, 2004||Micron Technology, Inc.||Method of forming tester substrates|
|US6708399||Apr 12, 2001||Mar 23, 2004||Micron Technology, Inc.||Method for fabricating a test interconnect for bumped semiconductor components|
|US6763581 *||Oct 21, 2002||Jul 20, 2004||Yukihiro Hirai||Method for manufacturing spiral contactor|
|US6765288||Sep 6, 2002||Jul 20, 2004||Tessera, Inc.||Microelectronic adaptors, assemblies and methods|
|US6785144||Aug 24, 2000||Aug 31, 2004||Micron Technology, Inc.||High density stackable and flexible substrate-based devices and systems and methods of fabricating|
|US6849953||Aug 29, 2001||Feb 1, 2005||Tessera, Inc.||Microelectronic assemblies with composite conductive elements|
|US6853210||Jul 18, 2002||Feb 8, 2005||Micron Technology, Inc.||Test interconnect having suspended contacts for bumped semiconductor components|
|US6882169||Oct 16, 2003||Apr 19, 2005||Fujitsu Limited||Semiconductor testing device|
|US6921272 *||May 12, 2003||Jul 26, 2005||International Business Machines Corporation||Method and apparatus for providing positive contact force in an electrical assembly|
|US6980017 *||Mar 10, 1999||Dec 27, 2005||Micron Technology, Inc.||Test interconnect for bumped semiconductor components and method of fabrication|
|US6995577||Sep 18, 2003||Feb 7, 2006||Micron Technology, Inc.||Contact for semiconductor components|
|US7002362||Apr 26, 2004||Feb 21, 2006||Micron Technology, Inc.||Test system for bumped semiconductor components|
|US7028398 *||Jul 30, 2003||Apr 18, 2006||Fujitsu Limited||Contactor, a method of manufacturing the contactor and a device and method of testing electronic component using the contactor|
|US7043831||Apr 30, 2001||May 16, 2006||Micron Technology, Inc.||Method for fabricating a test interconnect for bumped semiconductor components by forming recesses and cantilevered leads on a substrate|
|US7101193 *||Oct 3, 2005||Sep 5, 2006||International Business Machines Corporation||Structure for controlled shock and vibration of electrical interconnects|
|US7107674 *||Jul 19, 2004||Sep 19, 2006||Silverbrook Research Pty Ltd||Method for manufacturing a chip carrier|
|US7118385||Sep 22, 2005||Oct 10, 2006||International Business Machines Corporation||Apparatus for implementing a self-centering land grid array socket|
|US7161370||Feb 1, 2005||Jan 9, 2007||Fujitsu Limited||Semiconductor testing device|
|US7317322||Oct 5, 2005||Jan 8, 2008||Micron Technology, Inc.||Interconnect for bumped semiconductor components|
|US7368818||Oct 26, 2005||May 6, 2008||Tessera, Inc.||Methods of making microelectronic assemblies including compliant interfaces|
|US7408260||Jul 14, 2006||Aug 5, 2008||Tessera, Inc.||Microelectronic assemblies having compliant layers|
|US7462939 *||Oct 20, 2005||Dec 9, 2008||Honeywell International Inc.||Interposer for compliant interfacial coupling|
|US7462941 *||Sep 27, 2005||Dec 9, 2008||Telairity Semiconductor, Inc.||Power grid layout techniques on integrated circuits|
|US7659481 *||Oct 4, 2005||Feb 9, 2010||Kabushiki Kaisha Toshiba||Printed wiring board and information processing device incorporating the board|
|US7659739||Sep 14, 2006||Feb 9, 2010||Micro Porbe, Inc.||Knee probe having reduced thickness section for control of scrub motion|
|US7671610||Oct 19, 2007||Mar 2, 2010||Microprobe, Inc.||Vertical guided probe array providing sideways scrub motion|
|US7719378||Jan 22, 2008||May 18, 2010||Qualcomm Incorporated||Flexible interconnect cable for an electronic assembly|
|US7733101||Jun 9, 2006||Jun 8, 2010||Microprobe, Inc.||Knee probe having increased scrub motion|
|US7749886||Dec 20, 2006||Jul 6, 2010||Tessera, Inc.||Microelectronic assemblies having compliancy and methods therefor|
|US7759949||Jun 29, 2006||Jul 20, 2010||Microprobe, Inc.||Probes with self-cleaning blunt skates for contacting conductive pads|
|US7762843||Jul 27, 2010||Fci Americas Technology, Inc.||Shieldless, high-speed, low-cross-talk electrical connector|
|US7786740||Oct 11, 2006||Aug 31, 2010||Astria Semiconductor Holdings, Inc.||Probe cards employing probes having retaining portions for potting in a potting region|
|US7837505||Nov 23, 2010||Fci Americas Technology Llc||Electrical connector system with jogged contact tails|
|US7872344||Jun 23, 2006||Jan 18, 2011||Tessera, Inc.||Microelectronic assemblies having compliant layers|
|US7906733 *||May 21, 2008||Mar 15, 2011||Canon Kabushiki Kaisha||Electronic circuit device|
|US7939934||Dec 22, 2005||May 10, 2011||Tessera, Inc.||Microelectronic packages and methods therefor|
|US7944224||Jan 8, 2010||May 17, 2011||Microprobe, Inc.||Low profile probe having improved mechanical scrub and reduced contact inductance|
|US7952377||May 31, 2011||Microprobe, Inc.||Vertical probe array arranged to provide space transformation|
|US7960272||Jun 11, 2007||Jun 14, 2011||Megica Corporation||Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging|
|US7967647 *||Dec 16, 2010||Jun 28, 2011||Fci Americas Technology Llc||Orthogonal header|
|US7999379||Feb 23, 2006||Aug 16, 2011||Tessera, Inc.||Microelectronic assemblies having compliancy|
|US8039973 *||Jan 30, 2007||Oct 18, 2011||Valeo Etudes Electroniques||Electronic module having a multi-layer conductor for reducing its resistivity and a method of assembling such a module|
|US8044746||Oct 25, 2011||Qualcomm Incorporated||Flexible interconnect cable with first and second signal traces disposed between first and second ground traces so as to provide different line width and line spacing configurations|
|US8057267||Feb 26, 2008||Nov 15, 2011||Fci Americas Technology Llc||Orthogonal header|
|US8096832||Jul 26, 2010||Jan 17, 2012||Fci Americas Technology Llc||Shieldless, high-speed, low-cross-talk electrical connector|
|US8111080||Feb 3, 2010||Feb 7, 2012||Microprobe, Inc.||Knee probe having reduced thickness section for control of scrub motion|
|US8115308||May 21, 2010||Feb 14, 2012||Tessera, Inc.||Microelectronic assemblies having compliancy and methods therefor|
|US8137119||Jul 9, 2010||Mar 20, 2012||Fci Americas Technology Llc||Electrical connector system having a continuous ground at the mating interface thereof|
|US8203353||Jun 19, 2012||Microprobe, Inc.||Probes with offset arm and suspension structure|
|US8215965||Apr 24, 2009||Jul 10, 2012||Asahi Denka Kenkyusho Co., Ltd.||Female connector, male connector assembled to the same, and electric/electronic apparatus using them|
|US8230593||May 29, 2008||Jul 31, 2012||Microprobe, Inc.||Probe bonding method having improved control of bonding material|
|US8254155||Jan 20, 2012||Aug 28, 2012||Invensas Corporation||Stub minimization for multi-die wirebond assemblies with orthogonal windows|
|US8267721||Oct 20, 2010||Sep 18, 2012||Fci Americas Technology Llc||Electrical connector having ground plates and ground coupling bar|
|US8278764||Oct 2, 2012||Invensas Corporation||Stub minimization for multi-die wirebond assemblies with orthogonal windows|
|US8324923||May 31, 2011||Dec 4, 2012||Microprobe, Inc.||Vertical probe array arranged to provide space transformation|
|US8334588||Dec 18, 2012||Megica Corporation||Circuit component with conductive layer structure|
|US8338925||Dec 25, 2012||Tessera, Inc.||Microelectronic assemblies having compliant layers|
|US8345441||Dec 27, 2011||Jan 1, 2013||Invensas Corporation||Stub minimization for multi-die wirebond assemblies with parallel windows|
|US8382521||Dec 5, 2011||Feb 26, 2013||Fci Americas Technology Llc||Shieldless, high-speed, low-cross-talk electrical connector|
|US8405207||Apr 5, 2012||Mar 26, 2013||Invensas Corporation||Stub minimization for wirebond assemblies without windows|
|US8415963||Apr 9, 2013||Microprobe, Inc.||Low profile probe having improved mechanical scrub and reduced contact inductance|
|US8436457 *||May 7, 2013||Invensas Corporation||Stub minimization for multi-die wirebond assemblies with parallel windows|
|US8436477||May 7, 2013||Invensas Corporation||Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate|
|US8441111||Apr 5, 2012||May 14, 2013||Invensas Corporation||Stub minimization for multi-die wirebond assemblies with parallel windows|
|US8502390||Nov 29, 2011||Aug 6, 2013||Tessera, Inc.||De-skewed multi-die packages|
|US8513813||Apr 5, 2012||Aug 20, 2013||Invensas Corporation||Stub minimization using duplicate sets of terminals for wirebond assemblies without windows|
|US8513817||Jan 9, 2012||Aug 20, 2013||Invensas Corporation||Memory module in a package|
|US8525327||Apr 4, 2012||Sep 3, 2013||Invensas Corporation||Stub minimization for assemblies without wirebonds to package substrate|
|US8540525||Dec 9, 2009||Sep 24, 2013||Molex Incorporated||Resonance modifying connector|
|US8545240||Nov 13, 2009||Oct 1, 2013||Molex Incorporated||Connector with terminals forming differential pairs|
|US8558386||Oct 13, 2009||Oct 15, 2013||Tessera, Inc.||Methods of making compliant semiconductor chip packages|
|US8610260||Apr 4, 2012||Dec 17, 2013||Invensas Corporation||Stub minimization for assemblies without wirebonds to package substrate|
|US8616919||Nov 3, 2010||Dec 31, 2013||Fci Americas Technology Llc||Attachment system for electrical connector|
|US8629545||Apr 4, 2012||Jan 14, 2014||Invensas Corporation||Stub minimization for assemblies without wirebonds to package substrate|
|US8651881||Aug 22, 2013||Feb 18, 2014||Molex Incorporated||Resonance modifying connector|
|US8653646||Apr 5, 2012||Feb 18, 2014||Invensas Corporation||Stub minimization using duplicate sets of terminals for wirebond assemblies without windows|
|US8659139||Apr 4, 2012||Feb 25, 2014||Invensas Corporation||Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate|
|US8659140||Apr 4, 2012||Feb 25, 2014||Invensas Corporation||Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate|
|US8659141||Apr 5, 2012||Feb 25, 2014||Invensas Corporation||Stub minimization using duplicate sets of terminals for wirebond assemblies without windows|
|US8659142||Apr 5, 2012||Feb 25, 2014||Invensas Corporation||Stub minimization for wirebond assemblies without windows|
|US8659143||Apr 5, 2012||Feb 25, 2014||Invensas Corporation||Stub minimization for wirebond assemblies without windows|
|US8670261||Apr 9, 2013||Mar 11, 2014||Invensas Corporation||Stub minimization using duplicate sets of signal terminals|
|US8678860||Feb 19, 2013||Mar 25, 2014||Fci Americas Technology Llc||Shieldless, high-speed, low-cross-talk electrical connector|
|US8723546||Mar 2, 2010||May 13, 2014||Microprobe, Inc.||Vertical guided layered probe|
|US8759973||Dec 22, 2011||Jun 24, 2014||Tessera, Inc.||Microelectronic assemblies having compliancy and methods therefor|
|US8759982||Jul 25, 2013||Jun 24, 2014||Tessera, Inc.||Deskewed multi-die packages|
|US8764464||Feb 26, 2009||Jul 1, 2014||Fci Americas Technology Llc||Cross talk reduction for high speed electrical connectors|
|US8787034||Mar 15, 2013||Jul 22, 2014||Invensas Corporation||Co-support system and microelectronic assembly|
|US8823165||Jan 9, 2012||Sep 2, 2014||Invensas Corporation||Memory module in a package|
|US8847696||Nov 30, 2010||Sep 30, 2014||Qualcomm Incorporated||Flexible interconnect cable having signal trace pairs and ground layer pairs disposed on opposite sides of a flexible dielectric|
|US8848391||Mar 15, 2013||Sep 30, 2014||Invensas Corporation||Co-support component and microelectronic assembly|
|US8848392||Mar 15, 2013||Sep 30, 2014||Invensas Corporation||Co-support module and microelectronic assembly|
|US8905651||Jan 28, 2013||Dec 9, 2014||Fci||Dismountable optical coupling device|
|US8907689||Aug 30, 2010||Dec 9, 2014||Microprobe, Inc.||Probe retention arrangement|
|US8917532||Oct 3, 2012||Dec 23, 2014||Invensas Corporation||Stub minimization with terminal grids offset from center of package|
|US8944831||Mar 15, 2013||Feb 3, 2015||Fci Americas Technology Llc||Electrical connector having ribbed ground plate with engagement members|
|US8981547||Apr 3, 2014||Mar 17, 2015||Invensas Corporation||Stub minimization for multi-die wirebond assemblies with parallel windows|
|US8988091||Sep 13, 2010||Mar 24, 2015||Microprobe, Inc.||Multiple contact probes|
|US8992237||Jan 17, 2014||Mar 31, 2015||Molex Incorporated||Resonance modifying connector|
|US9048583||Jan 31, 2013||Jun 2, 2015||Fci Americas Technology Llc||Electrical connector having ribbed ground plate|
|US9070423||Nov 8, 2013||Jun 30, 2015||Invensas Corporation||Single package dual channel memory with co-support|
|US9097740||Feb 9, 2010||Aug 4, 2015||Formfactor, Inc.||Layered probes with core|
|US9123555||Oct 25, 2013||Sep 1, 2015||Invensas Corporation||Co-support for XFD packaging|
|US9193001 *||Mar 12, 2012||Nov 24, 2015||Delta Electronics, Inc.||Welding jig and welding process for planar magnetic components|
|US9214455||Dec 22, 2014||Dec 15, 2015||Invensas Corporation||Stub minimization with terminal grids offset from center of package|
|US9224431||Mar 6, 2014||Dec 29, 2015||Invensas Corporation||Stub minimization using duplicate sets of signal terminals|
|US9257778||Mar 15, 2013||Feb 9, 2016||Fci Americas Technology||High speed electrical connector|
|US9274143||Dec 4, 2012||Mar 1, 2016||Formfactor, Inc.||Vertical probe array arranged to provide space transformation|
|US9277649||Oct 3, 2012||Mar 1, 2016||Fci Americas Technology Llc||Cross talk reduction for high-speed electrical connectors|
|US9281271||Feb 24, 2014||Mar 8, 2016||Invensas Corporation||Stub minimization using duplicate sets of signal terminals having modulo-x symmetry in assemblies without wirebonds to package substrate|
|US9281296||Jul 31, 2014||Mar 8, 2016||Invensas Corporation||Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design|
|US9287195||Feb 21, 2014||Mar 15, 2016||Invensas Corporation||Stub minimization using duplicate sets of terminals having modulo-x symmetry for wirebond assemblies without windows|
|US9287216||Aug 29, 2014||Mar 15, 2016||Invensas Corporation||Memory module in a package|
|US9293444||Aug 27, 2015||Mar 22, 2016||Invensas Corporation||Co-support for XFD packaging|
|US9310428||Dec 9, 2014||Apr 12, 2016||Formfactor, Inc.||Probe retention arrangement|
|US9316670||Mar 20, 2015||Apr 19, 2016||Formfactor, Inc.||Multiple contact probes|
|US9368477||Mar 15, 2013||Jun 14, 2016||Invensas Corporation||Co-support circuit panel and microelectronic packages|
|US9373565||Dec 16, 2013||Jun 21, 2016||Invensas Corporation||Stub minimization for assemblies without wirebonds to package substrate|
|US9377824||Apr 3, 2014||Jun 28, 2016||Invensas Corporation||Microelectronic assembly including memory packages connected to circuit panel, the memory packages having stub minimization for wirebond assemblies without windows|
|US9423824||Mar 16, 2015||Aug 23, 2016||Invensas Corporation||Stub minimization for multi-die wirebond assemblies with parallel windows|
|US9460758||Jun 29, 2015||Oct 4, 2016||Invensas Corporation||Single package dual channel memory with co-support|
|US9461410||Jul 24, 2014||Oct 4, 2016||Fci Americas Technology Llc||Electrical connector having ribbed ground plate|
|US20040070010 *||Jul 30, 2003||Apr 15, 2004||Fujitsu Limited||Contactor, a method of manufacturing the contactor and a device and method of testing electronic component using the contactor|
|US20040124866 *||Oct 16, 2003||Jul 1, 2004||Fujitsu Limited||Semiconductor testing device|
|US20040217461 *||Jun 7, 2004||Nov 4, 2004||Tessera, Inc.||Microelectronic adaptors, assemblies and methods|
|US20040222518 *||Feb 25, 2004||Nov 11, 2004||Tessera, Inc.||Ball grid array with bumps|
|US20040229481 *||May 12, 2003||Nov 18, 2004||International Business Machines Corporation||Method and apparatus for providing positive contact force in an electrical assembly|
|US20040255456 *||Jul 19, 2004||Dec 23, 2004||Silverbrook Research Pty Ltd||Method for manufacturing a chip carrier|
|US20050073334 *||Sep 18, 2003||Apr 7, 2005||Farnworth Warren M.||Contact For Semiconductor Components|
|US20050133900 *||Jan 31, 2005||Jun 23, 2005||Tessera, Inc.||Microelectronic assemblies with composite conductive elements|
|US20050162180 *||Feb 1, 2005||Jul 28, 2005||Fijitsu Limited||Semiconductor testing device|
|US20050167817 *||Jan 19, 2005||Aug 4, 2005||Tessera, Inc.||Microelectronic adaptors, assemblies and methods|
|US20060028222 *||Oct 5, 2005||Feb 9, 2006||Farnworth Warren M||Interconnect for bumped semiconductor components|
|US20060030197 *||Oct 3, 2005||Feb 9, 2006||International Business Machines Corporation||Structure for controlled shock and vibration of electrical interconnects|
|US20060049498 *||Oct 26, 2005||Mar 9, 2006||Tessera, Inc.||Methods of making microelectronic assemblies including compliant interfaces|
|US20060081984 *||Sep 27, 2005||Apr 20, 2006||Telairity Semiconductor, Inc.||Power grid layout techniques on integrated circuits|
|US20060082001 *||Oct 4, 2005||Apr 20, 2006||Kabushiki Kaisha Toshiba||Printed wiring board and information processing device incorporating the board|
|US20060194365 *||Feb 23, 2006||Aug 31, 2006||Tessera, Inc.||Microelectronic assemblies having compliancy|
|US20060215382 *||May 30, 2006||Sep 28, 2006||Silverbrook Research Pty Ltd||Integrated circuit carrier|
|US20060237836 *||Jun 23, 2006||Oct 26, 2006||Tessera, Inc.||Microelectronic assemblies having compliant layers|
|US20060261476 *||Jul 14, 2006||Nov 23, 2006||Tessera, Inc.||Microelectronic assemblies having compliant layers|
|US20070090506 *||Oct 20, 2005||Apr 26, 2007||Honeywell International Inc.||Interposer for compliant interfacial coupling|
|US20070152686 *||Jun 9, 2006||Jul 5, 2007||January Kister||Knee probe having increased scrub motion|
|US20070232053 *||Jun 11, 2007||Oct 4, 2007||Megica Corporation||Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging|
|US20080001612 *||Jun 29, 2006||Jan 3, 2008||January Kister||Probes with self-cleaning blunt skates for contacting conductive pads|
|US20080068035 *||Sep 14, 2006||Mar 20, 2008||Microprobe, Inc.||Knee probe having reduced thickness section for control of scrub motion|
|US20080088327 *||Oct 11, 2006||Apr 17, 2008||January Kister||Probe cards employing probes having retaining portions for potting in a potting region|
|US20080116988 *||Jan 22, 2008||May 22, 2008||Applied Micro Circuits Corporation||Flexible interconnect cable for an electronic assembly|
|US20080150121 *||Dec 20, 2006||Jun 26, 2008||Tessera Technologies Hungary Kft.||Microelectronic assemblies having compliancy and methods therefor|
|US20080158842 *||Dec 29, 2006||Jul 3, 2008||Texas Instruments Incorporated||Stress and collapse resistant interconnect for mounting an integrated circuit package to a substrate|
|US20080247145 *||Jun 17, 2008||Oct 9, 2008||Silverbrook Research Pty Ltd||Integrated circuit carrier arrangement with electrical connection islands|
|US20090102495 *||Oct 19, 2007||Apr 23, 2009||January Kister||Vertical guided probe array providing sideways scrub motion|
|US20090179336 *||Jan 30, 2007||Jul 16, 2009||Valeo Etudes Electroniques||Electronic Module and a Method of Assembling Such a Module|
|US20100035382 *||Feb 11, 2010||Tessera, Inc.||Methods of making compliant semiconductor chip packages|
|US20100048067 *||Feb 26, 2008||Feb 25, 2010||Johnescu Douglas M||Orthogonal header|
|US20100084177 *||May 21, 2008||Apr 8, 2010||Canon Kabushiki Kaisha||Electronic circuit device|
|US20100155941 *||Jan 20, 2010||Jun 24, 2010||Fujitsu Microelectronics Limited||Semiconductor device|
|US20100176832 *||Mar 2, 2010||Jul 15, 2010||Microprobe, Inc.||Vertical Guided Layered Probe|
|US20100201462 *||Apr 16, 2010||Aug 12, 2010||Qualcomm Incorporated||Flexible interconnect cable for an electronic assembly|
|US20100230812 *||May 21, 2010||Sep 16, 2010||Tessera, Inc.||Microelectronic Assemblies Having Compliancy and Methods Therefor|
|US20110039427 *||Apr 24, 2009||Feb 17, 2011||Asahi Denka Kenkyusho Co., Ltd.||Female connector, male connector assembled to the same, and electric/electronic apparatus using them|
|US20110095441 *||Dec 21, 2010||Apr 28, 2011||Tessera, Inc.||Microelectronic assemblies having compliant layers|
|US20110113625 *||Dec 16, 2010||May 19, 2011||Fci Americas Technology, Inc.||Orthogonal header|
|US20110121922 *||Nov 30, 2010||May 26, 2011||Qualcomm Incorporated||Flexible interconnect cable for an electronic assembly|
|US20110204522 *||Aug 25, 2011||Megica Corporation||Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging|
|US20120286816 *||Mar 19, 2012||Nov 15, 2012||Microprobe, Inc.||Probes with high current carrying capability and laser machining methods|
|US20130082042 *||Mar 12, 2012||Apr 4, 2013||Delta Electronics, Inc.||Welding jig and welding process for planar magnetic components|
|US20130082394 *||Apr 4, 2013||Invensas Corporation||Stub minimization for multi-die wirebond assemblies with parallel windows|
|USD718253||Apr 13, 2012||Nov 25, 2014||Fci Americas Technology Llc||Electrical cable connector|
|USD720698||Mar 15, 2013||Jan 6, 2015||Fci Americas Technology Llc||Electrical cable connector|
|USD727268||Apr 13, 2012||Apr 21, 2015||Fci Americas Technology Llc||Vertical electrical connector|
|USD727852||Apr 13, 2012||Apr 28, 2015||Fci Americas Technology Llc||Ground shield for a right angle electrical connector|
|USD733662||Aug 1, 2014||Jul 7, 2015||Fci Americas Technology Llc||Connector housing for electrical connector|
|USD745852||Jan 25, 2013||Dec 22, 2015||Fci Americas Technology Llc||Electrical connector|
|USD746236||Oct 9, 2014||Dec 29, 2015||Fci Americas Technology Llc||Electrical connector housing|
|USD748063||Oct 9, 2014||Jan 26, 2016||Fci Americas Technology Llc||Electrical ground shield|
|USD750025||Feb 12, 2015||Feb 23, 2016||Fci Americas Technology Llc||Vertical electrical connector|
|USD750030||Nov 3, 2014||Feb 23, 2016||Fci Americas Technology Llc||Electrical cable connector|
|USD751507||Jul 11, 2012||Mar 15, 2016||Fci Americas Technology Llc||Electrical connector|
|USD766832||Jul 9, 2015||Sep 20, 2016||Fci Americas Technology Llc||Electrical connector|
|USRE43503||Jul 10, 2012||Microprobe, Inc.||Probe skates for electrical testing of convex pad topologies|
|USRE44407||Dec 23, 2009||Aug 6, 2013||Formfactor, Inc.||Space transformers employing wire bonds for interconnections with fine pitch contacts|
|CN100550331C||Sep 26, 2001||Oct 14, 2009||日本先进装置株式会社||Spiral contactor manufacturing method|
|CN101622914B||Feb 26, 2008||Jul 13, 2011||Fci公司||Orthogonal header|
|CN101911393B||Apr 24, 2009||Apr 16, 2014||株式会社旭电化研究所||Female connector, male connector assembled thereto, and electric/electronic apparatus using the connectors|
|CN104340092A *||Aug 1, 2014||Feb 11, 2015||丰田纺织株式会社||Recliner|
|EP1191588A2 *||Aug 15, 2001||Mar 27, 2002||Yukihiro Hirai||A spiral contactor and manufacturing method therefor|
|WO2008083250A2 *||Dec 27, 2007||Jul 10, 2008||Texas Instruments Incorporated||Stress and collapse resistant interconnect for mounting an integrated circuit package to a substrate|
|WO2008083250A3 *||Dec 27, 2007||Aug 21, 2008||Leon Stiborek||Stress and collapse resistant interconnect for mounting an integrated circuit package to a substrate|
|WO2008106096A1 *||Feb 26, 2008||Sep 4, 2008||Fci||Orthogonal header|
|U.S. Classification||439/70, 228/180.1, 29/843, 361/774, 324/763.01, 324/755.07, 324/754.08|
|International Classification||H01R11/01, H01R33/76, H01L23/498, H01L23/48, H01R12/52, H05K3/40, H05K7/10, G01R31/28, H05K3/34, H01L23/32, H05K3/32|
|Cooperative Classification||H01L2224/45144, H01L2224/16225, H01L2224/73251, H01L2224/81385, H01L2224/81191, H01L2224/81901, H01L2224/16237, H01L2224/13111, Y02P70/613, H01L2924/15311, H01L2924/351, Y10T29/49149, H01R12/52, H01L2924/01076, H01L2924/01004, H05K2201/10257, H01L23/32, H05K2201/0397, H01L2924/30107, H01L2924/01322, H01L23/49827, H01L2924/01015, H01L2924/15173, H01L2924/01079, H01L2924/01074, H05K3/4092, H01L2924/01045, H05K2201/10378, H05K2201/049, H01L2924/01047, H01L2924/01078, H01L2924/01033, H01L2924/01039, H01L2924/14, H01L2924/01075, H05K2203/041, H05K7/1061, H05K3/3436, H01L2924/01005, H01L2924/3011, H01L2924/01006, H01L2924/01082, H01L2924/01013, H01L2924/01029, H05K3/326|
|European Classification||H01L23/498E, H01L24/72, H05K3/32C2, H05K7/10F2, H05K3/34C4B, H01L23/32, H01R9/09|
|Nov 25, 1997||AS||Assignment|
Owner name: TESSERA, INC., A CORP. OF DE, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FJELSTAD, JOSEPH;DISTEFANO, THOMAS H.;KARAVAKIS, KONSTANTINE;AND OTHERS;REEL/FRAME:008823/0138;SIGNING DATES FROM 19971114 TO 19971119
|Apr 10, 2001||CC||Certificate of correction|
|Dec 23, 2003||FPAY||Fee payment|
Year of fee payment: 4
|Jan 3, 2008||FPAY||Fee payment|
Year of fee payment: 8
|Jan 6, 2012||FPAY||Fee payment|
Year of fee payment: 12