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Publication numberUS6105124 A
Publication typeGrant
Application numberUS 08/672,100
Publication dateAug 15, 2000
Filing dateJun 27, 1996
Priority dateJan 26, 1996
Fee statusPaid
Publication number08672100, 672100, US 6105124 A, US 6105124A, US-A-6105124, US6105124 A, US6105124A
InventorsYaron Farber, Gad Sheaffer, Robert Valentine
Original AssigneeIntel Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method and apparatus for merging binary translated basic blocks of instructions
US 6105124 A
Abstract
A method for merging binary translated basic blocks of instructions. The method is for use in a computer system having in a memory a first set of instructions including blocks of instructions, and a translator for translating instructions executable on a source instruction set architecture into instructions executable on a target instruction set architecture. The method includes a first step of determining, by the translator, an order of execution from a first block of instructions to a second block of instructions. A second step of the method includes generating, by the translator, a hyperblock of instructions representing the first and second block of instructions translated and placed adjacent in a memory location in the order of execution.
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Claims(17)
What is claimed is:
1. A method for use in a computer system, the computer system having a translator for translating instructions executable in a source instruction set Architecture into instructions executable in a target instruction set Architecture, the method comprising the steps of:
a) the translator determining a probability of a first block of instructions following an order of execution to a second block of instructions, said probability consisting of a ratio of a taken counter and a used counter, said taken counter represents a number of times the first block of instructions follows the order of execution to the second block of instructions, and said used counter a number of times the first block of instructions has been executed; and
b) in response to the probability exceeding a predetermined threshold, the translator generating a hyperblock of instructions representing the first and second block of instructions translated, and combined in the order of execution.
2. The method of claim 1, wherein the step of generating the hyperblock further includes the step of:
c) replacing an address for the first block of instructions in an address table with an address of the hyperblock.
3. The method of claim 2, further includes the step of:
d) in response to the probability being below a second threshold, generating by the translator a hyperblock representing the first block of instructions translated and a third block of instructions translated placed adjacent in a memory location, wherein the first and third block of instructions are adjacent in the physical static sequence of the first set of instructions.
4. The method of claim 3, further includes the following steps prior to the step of determining the order of execution:
e) determining if the used counter exceeds a predetermined used-threshold;
f) in response to the used counter exceeding the predetermined used-threshold, determining by the translator the order of execution from the first block of instructions to the second block of instructions.
5. The method of claim 4, further includes the following steps prior to the step of determining if the used counter exceeds the predetermined used-threshold:
g) determining if a branch instruction of the first block of instructions is taken during a present execution of the first block of instructions;
h) in response to the branch instruction of the first block of instructions being taken, incrementing the taken counter.
6. The method of claim 5, wherein the used counter and the taken counter are accumulated by instructions included in the first block of instructions translated.
7. The method of claim 1, wherein the steps of the method are performed dynamically during an execution of the first set of instructions.
8. A machine-readable medium having stored thereon data representing a first set of instructions a translator for translating instructions executable on a source instruction set architecture into instructions executable on a target instruction set architecture, the second set of instruction which, when executed by a processor, cause the processor to perform the steps of:
a) the translator determining a probability of a first block of instructions following an order of execution to a second block of instructions, said probability consisting of a ratio of a taken counter and a used counter, said taken counter represents a number of times the first block of instructions follows the order of execution to the second block of instructions, and said used counter a number of times the first block of instructions has been executed; and
b) in response to the probability exceeding a predetermined threshold, the translator generating a hyperblock of instructions representing the first and second block of instructions translated, and combined in the order of execution.
9. The machine-readable medium of claim 8, wherein the step of generating the hyperblock further includes the step of:
c) replacing an address for the first block of instructions in an address table with an address of the hyperblock.
10. The machine-readable medium of claim 9, wherein said first set of instructions further includes additional instructions, which when executed by said processor, cause said processor to perform the additional step of:
d) in response to the probability being below a second threshold, generating by the translator a hyperblock representing the first block of instructions translated and a third block of instructions translated placed adjacent in a memory location, wherein the first and third block of instructions are adjacent in the physical static sequence of the first set of instructions.
11. The machine-readable medium of claim 10, wherein said first set of instructions further includes additional instructions, which when executed by said processor, cause said processor to perform the following steps prior to the step of determining the order of execution:
e) determining if the used counter exceeds a predetermined used-threshold;
f) in response to the used counter exceeding the predetermined used-threshold, determining by the translator the order of execution from the first block of instructions to the second block of instructions.
12. The machine-readable medium of claim 11, wherein said first set of instructions further includes additional instructions, which when executed by said processor, cause said processor to perform the following steps prior to the step of determining if the used counter exceeds the predetermined used-threshold:
g) determining if a branch instruction of the first block of instructions is taken during a present execution of the first block of instructions;
h) in response to the branch instruction of the first block of instructions being taken, incrementing the taken counter.
13. The machine-readable medium of claim 12, wherein the used counter and the taken counter are accumulated by instructions included in the first block of instructions translated.
14. The machine-readable medium of claim 13, wherein the steps are performed dynamically during an execution of the first set of instructions.
15. A translator to translate instructions executable in a source instruction set Architecture into instructions executable in a target instruction set Architecture, said translator comprising:
a first device to determine a probability of a first block of instructions following an order of execution to a second block of instructions, said probability consisting of a ratio of a taken counter and a used counter, said taken counter represents a number of times the first block of instructions follows the order of execution to the second block of instructions, and said used counter a number of times the first block of instructions has been executed; and
a second device to generate a hyperblock of instructions in response to the probablity exceeding a predetermined threshold, the hyperblock of instructions representing the first block of instructions translated and second block of instructions translated, and combined in the order of execution.
16. The translator of claim 15, wherein the generating of the hyperblock by said second device further includes replacing an address for the first block of instructions in an address table with an address of the hyperblock.
17. The translator of claim 16, wherein in response to the probability being below a second threshold, said translator generates a hyperblock representing the first block of instructions translated and a third block of instructions translated placed adjacent in a memory location, wherein the first and third block of instructions are adjacent in the physical static sequence of the first set of instructions.
Description
CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a Continuation-in-Part of application Ser. No. 08/592,761, Titled "Trace-Based Merging Of Code Blocks To Facilitate Code Optimization In Binary Translation", Filed Jan. 26, 1996, by Yaron Farber, Gad Sheaffer, and Robert Valentine, now abandoned.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

A method is described for merging several translated basic blocks of instructions into a hyperblock of instructions in an order of execution.

Referring to FIG. 1, a target instruction set computer architecture is shown implementing one embodiment of the present invention. Shown stored in the memory is the untranslated Source Program 110, consisting of several BB's executable on a source instruction set computer architecture. The BB's of the untranslated Source Program are to be translated by the Translator in order to be executed in the target instruction set computer architecture.

After the BB's of the Source Program are translated, the BB's are stored in the area of memory shown as the Translated Basic Blocks 160. The memory address for each translated BB is stored in the Translated Address Table 150.

In one embodiment, each translated BB has associated with it two counters (i.e. a used counter and a taken counter). The counters record the branch behavior patterns of the translated basic blocks of instructions in order to determine an "expected" order of execution based on input data presently being processed. In an alternative embodiment, the order of execution can be based on assuming all forward conditional branch instructions or all backward conditional branch instructions are taken.

The used counter represents the number of times a particular translated basic block of instructions has been executed during the present execution a computer program on the target computer. The taken counter represents the number of times the branch instruction of the translated BB has been taken during the present execution of the computer program. The counter for each translated BB is stored in the Counter Table 145 shown in the memory.

In one embodiment of the present invention, several translated basic blocks of instructions are merged into one basic block of instructions, in an order of execution, to form a hyperblock instructions. The hyperblock of instructions is then stored in an area of memory, such as the Translated Hyperblocks 190 memory area shown in FIG. 1.

Referring to FIGS. 2a and 2b, flow diagrams are shown illustrating the steps performed in one embodiment of the present invention to generate a hyperblock of instructions. In FIG. 2a, BB.sub.i, which hereinafter represents the current BB, has been translated and executed at least once on the target computer prior to block 202. Following the execution, in block 202 the used counter of BB.sub.i is incremented.

The counters are incremented by code in the respective translated BB (Increment & Select Code) which is appended to each BB during the binary translation of each BB. The Increment & Select Code includes instructions to load the respective counter from a Counter Table 145 in memory, increment it by 1, and store it back in memory. In alternative embodiments, the counters could be stored in memory in alternative data structures, such as a B-tree data structure.

Also, in an alternative embodiments, the Increment & Select Code could be represented by a procedure call to a separate procedure in the respective computer program or included in the Translator.

In conditional block 204, it is determined whether the conditional branch instruction of BB.sub.i as taken. If the branch instruction of BB.sub.i was taken, in block 206, BB.sub.j (which hereinafter represents the BB that follows BB.sub.i in the order of execution) is the BB addressed by the branch instruction of BB.sub.i. In block 208, BB.sub.i 's taken counter is incremented. Otherwise, if the branch instruction of BB.sub.i was not taken, in block 210, BB.sub.j is the next sequential block in the static sequence of the program.

In conditional block 212, it is determined by BB.sub.i 's Increment & Select Code, whether BB.sub.i 's used counter is greater than or equal to a predetermined used-threshold, also stored in the Increment & Select Code. If the used counter of BB.sub.i is equal to or exceeds the used-counter threshold, the present invention begins forming a hyperblock between BB.sub.i and the BB most likely to follow BB.sub.i in the order of execution (hereinafter represented as BB.sub.x).

In one embodiment, the used counter threshold is 100. The actual number of the used counter threshold can be different in alternative embodiments.

If BB.sub.i 's used counter is below the used-threshold, in block 240, the program will continue execution at BB.sub.j. If the instructions of the BB.sub.j have already undergone a binary translation, then the memory address for the translated BB.sub.j can be obtained from a Translated Address Table in memory 104. Otherwise, BB.sub.j is translated by the Translator and the address of the translated BB.sub.j is stored in the Translated Address Table.

If the used counter of BB.sub.i is equal to or exceeds the used counter threshold, in block 213 the translated addresses for BB.sub.i and BB.sub.j are sent to Translator. As illustrated in the flow diagram of FIG. 2b, the Translator begins forming a hyperblock of instructions by merging BB.sub.i and BB.sub.x (the BB most likely to follow BB.sub.i in the order of execution.)

In block 214, the Translator determines the probability (P) of the BB.sub.i 's branch instruction being taken by dividing BB.sub.i 's taken counter with BB.sub.i 's used counter. In conditional block 216, it is determined whether the branch instruction of BB.sub.i is strongly taken, strongly not taken, or something in between ("flaky"). The probability of BB.sub.i 's branch being taken is compared to a strongly taken threshold (TAKEN) and a strongly not taken threshold (NOT-TAKEN).

In one embodiment, the strongly taken threshold is 90% and the strongly not taken threshold is 10%. In alternative embodiments, the actual numbers of the strongly taken and strongly not taken thresholds can be different levels, including being represented as non-additive inverses. If both conditions in block 216 fail, the branch behavior of BB.sub.i is considered to be flaky, and the Translator is exited in block 236 to continue execution of the program at BB.sub.j in block 240.

Provided one of the conditions of block 216 is true (i.e., the branch is predicted to be strongly taken or strongly not taken), in block 218 the BB.sub.x is determined. If the probability of taking BB.sub.i 's branch instruction exceeds the strongly taken threshold, in block 220, BB.sub.x is the BB addressed by the conditional branch instruction of BB.sub.i. Otherwise, in block 222, BB.sub.x is the BB following BB.sub.i next in the static sequence of the Untranslated Program.

In block 224, BB.sub.i and BB.sub.x, are translated into instructions executable in the target instruction set computer architecture by the Translator. The Translator sequentially performs a binary translation of the instructions included in BB.sub.i and BB.sub.x. During the binary translation, each instruction is decoded by the Translator into an opcode and operands. The opcode indicates an operation to be performed by the instruction, and the operands are memory or register addresses of data to be operated on by the opcode.

The Translator further provides a separate sequence of micro-instructions in place of the untranslated instruction's opcode in order to emulate execution the untranslated instruction on the target system. The micro-instructions provided by the Translator are selected from the instruction set of the target computer system.

The Translator also translates the memory addresses of the untranslated instruction's operands to be compatible with the target computer system. For example, the memory addresses, which typically represent memory or register locations in the source computer system, may be added to an offset base memory address of the target computer system.

In alternative embodiments, if BB.sub.i and BB.sub.x were previously translated, memory addresses of the translated BB.sub.i and BB.sub.x could be retrieved from the Translated Address Table and used in place of retranslating the instructions.

In block 228, the Translator begins forming the hyperblock of instructions 182 by storing the translated instructions of BB.sub.i and BB.sub.x adjacent to each other, in the order of execution, in the Translated Hyperblocks memory location 190. For example, as shown in FIG. 1, BB.sub.1 and BB.sub.3 are stored adjacent to each other in the hyperblock 182. The Translated Hyperblocks memory location may alternatively be in a cache memory of a processor. The Increment & Select Code of BB.sub.i and BB.sub.x may be omitted from the hyperblock.

In block 230, the instructions within the hyperblock are scheduled to accommodate data and resource dependencies through standard optimization and scheduling procedures.

In block 232, the Translator replaces BB.sub.i s address in a Translated Address Table 150, with the address for the hyperblock 182. In one embodiment, each row of the Translated Address Table includes an identifier associated with a translated BB and a memory address corresponding to the translated BB (e.g. the hyperblock).

When processing the program, an identifier associated with a BB is issued from a processor to the Translated Address Table. The identifier from the processor is compared with each identifier in the table. When a match is found, the memory address corresponding to the translated BB is returned to the processor. Subsequently, the instructions stored at the memory address (e.g. the hyperblock) are fetched and issued to an execution unit of the processor and executed.

In block 234, the Translator continues at block 214. During the succeeding iteration, the probability of taking BB.sub.x 's branch instruction is determined in processing block 214. The method of the present invention will continue to build the hyperblock by performing the steps described in blocks 214 through 234.

Once a particular BB.sub.x fails both conditions of block 216, wherein the particular BB.sub.x branch behavior is found to be flaky, the Translator, in block 236, is exited and the address for BB.sub.j is returned so that in block 240 the execution of the computer program can be resumed at BB.sub.j.

The hyperblock, however, remains in memory to be executed the next time BB.sub.i is called during the present processing of the program. Regardless of whether the behavior of the branch instructions of the BBs merged to form the hyperblock is different from the expected order of execution, the hyperblock is retained for future execution.

While the method of the present invention has been described in connection with certain embodiments and examples, it should be understood that the broad concept embodied in the invention is not limited to these embodiments.

For instance, the present invention may be performed dynamically during the execution of a computer program, wherein the taken and used counters are used to generate an "expected" order of execution based on input data presently being processed. Alternatively, the present invention may be performed statically when the program is not being executed, wherein the order of execution can be based on assuming all forward conditional branch instructions or all backward conditional branch instructions are taken.

In addition, where it has been shown that the Translator, the Counter Table, the Translated Address Table, the Translated hyperblocks, the untranslated Source Program, and the Translated Basic Blocks are stored in memory, these items and instructions can also be stored on other computer-readable mediums, including magnetic and optical disks, which could be accessed via the disk drive shown in the computer system of FIG. 1. Alternatively, the Translator could be implemented in discrete hardware components such as large-scale integrated circuits (LSI's), application-specific integrated circuits (ASIC's) or in firmware such as electrically erasable programmable read-only memory (EEPROM's).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a computer system on which the present invention can be implemented.

FIG. 2a is a flow diagram of the steps performed in the method of the present invention.

FIG. 2b is a flow diagram of the steps performed in the method of the present invention, wherein the merging of translated basic blocks of instruction is performed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to computer systems, and in particular, the generation of fast, optimized code by merging binary translated basic blocks of instructions.

2. Description of Related Art

Each computer architecture includes its own unique instruction set. Computer program instructions that are compiled into executable code for a first source instruction set architecture, such as the Intel undergo a binary translation in order to be compatible with a different target instruction set architecture, such as a reduced instruction-set computer (RISC) or very long instruction word (VLIW) computer architecture.

The translation may be performed by a dynamic translator typically stored in memory. During dynamic translation, instructions are typically translated one basic block of instructions (BB) at a time, and stored in memory at an area allocated for storing translated BBs, such as the Translated Basic Blocks memory location 160, shown in the memory of FIG. 1. Each basic block of instructions includes a contiguous sequence of non-branch instructions (i.e. do not change order of executing instructions) which typically ends with a conditional branch instruction.

An untranslated computer program, such as the Source Program 110 of FIG. 1, consist of several BB's stored in a physical static sequence (e.g., BB.sub.1, BB.sub.2, BB.sub.3 . . . BB.sub.10). The order of executing the BB's can be different from the static sequence. The order of executing the BB's is determined by the behavior of the BB's branch instructions.

For example, if the branch instructions of BB.sub.1 and BB.sub.4 are the only branch instructions taken in the Source Program 110 (i.e. the branch instruction of BB.sub.3 is not taken), the order of execution is BB.sub.1 -BB.sub.3 -BB.sub.4 -BB.sub.10. In the order of Execution, BB.sub.1 and BB.sub.3, as well as BB.sub.4 and BB.sub.10, remain separated in the physical static sequence of the program.

After a BB has been translated, the translated BB is stored in memory. However, the translated BB's may not be stored in the order of the original static sequence of the untranslated Basic Blocks of instructions. Therefore, when executing a translated BB additional time maybe needed to locate the memory address of the translated BB.

In addition, after a BB has been translated, the instructions of the BB are typically rescheduled to accommodate resource and data dependencies among the instructions within the BB. The rescheduling becomes more effective as the number of instructions rescheduled increases. The rescheduling, however, is typically limited to the instructions within one BB, which typically only consist of five to ten instructions.

SUMMARY OF THE INVENTION

The present invention provides a method for use in a computer system. The computer system has in a memory a first set of instructions including blocks of instructions, and a translator for translating instructions executable on a source instruction set architecture into instructions executable on a target instruction set architecture. The method includes a first step of determining, by the translator, an order of execution from a first block of instructions to a second block of instructions. A second step of the method includes generating, by the translator, a hyperblock of instructions representing the first and second block of instructions translated and placed adjacent in a memory location in the order of execution.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6230258 *Aug 31, 1998May 8, 2001Matsushita Electric Industrial Co., Ltd.Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions
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Classifications
U.S. Classification712/208, 712/214, 714/E11.192, 714/E11.212, 717/138
International ClassificationG06F11/36, G06F9/45, G06F11/34
Cooperative ClassificationG06F2201/865, G06F11/3466, G06F8/445, G06F8/52, G06F2201/88
European ClassificationG06F8/445, G06F8/52, G06F11/34C
Legal Events
DateCodeEventDescription
Feb 8, 2012FPAYFee payment
Year of fee payment: 12
Feb 25, 2008REMIMaintenance fee reminder mailed
Feb 15, 2008FPAYFee payment
Year of fee payment: 8
Feb 16, 2004FPAYFee payment
Year of fee payment: 4
Mar 17, 1997ASAssignment
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SHEAFFER, GAD;REEL/FRAME:008411/0368
Effective date: 19961216
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FARBER, YARON;VALENTINE, ROBERT;REEL/FRAME:008411/0392
Effective date: 19970310