|Publication number||US6130574 A|
|Application number||US 09/360,946|
|Publication date||Oct 10, 2000|
|Filing date||Jul 26, 1999|
|Priority date||Jan 24, 1997|
|Publication number||09360946, 360946, US 6130574 A, US 6130574A, US-A-6130574, US6130574 A, US6130574A|
|Inventors||Martin Bloch, Christl Lauterbach|
|Original Assignee||Siemens Aktiengesellschaft|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (14), Non-Patent Citations (2), Referenced by (66), Classifications (10), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of copending International Application No. PCT/DE97/02154, filed Sep. 23, 1997, which designated the United States.
Field of the Invention
The invention relates to a circuit configuration for producing negative voltages, including a first transistor having a first connection connected to an input connection, a second connection connected to an output connection of the circuit configuration and a gate connection connected through a first capacitor to a first clock signal connection, a second transistor having a first connection connected to the gate connection of the first transistor, a second connection connected to the second connection of the first transistor and a gate connection connected to the first connection of the first transistor, and a second capacitor having a first connection connected to the second connection of the first transistor and a second connection connected to a second clock signal connection, the transistors being MOS transistors produced in at least one triple well.
Such a circuit configuration is known from German Patent DE 196 01 369 C1. In that publication, the transistors are implemented as n-channel transistors in a p-well. The p-well is in turn produced in a deep, insulating n-well which is disposed in a p-substrate.
In principle, the circuit configuration can also be implemented in that way by using p-MOS transistors in an n-substrate.
The deep n-well is connected to ground potential, like the p-substrate. If the p-well is then given a more negative bias than the most negative voltage either at the drain connection or at the source connection of the first transistor, then no leakage current can flow when the circuit is in the steady state, not even through the parasitic well-substrate bipolar transistors. Thus, for example, an npn transistor is formed by the n+ -drain region which acts as an emitter of the NMOS transistor, the p-well which forms the base, and the n-well which forms the collector. When the well potential is more positive than the drain region of the NMOS transistor, the parasitic npn transistor will be switched on and will impair the efficiency of the charge pump.
The principle of the known circuit configuration operating as a charge pump is based on the fact that charges from a capacitor which is connected to the drain connection of the first transistor are "pumped" to a capacitor which is connected to the source connection of that transistor, by a voltage being alternately applied to the respective other capacitor connections. When a number N of circuit configurations of that type are connected in series, and the input of the first circuit configuration and the other connection of the capacitor connected to the output are connected to the ground connection, an output voltage of |(N-1)UO | can theoretically be obtained, where UO is the voltage at the clock signal connections.
The charging process is a dynamic process in which the voltages at the source and drain connections of the first transistors of the circuit configuration are constantly changing, with the result that the parasitic bipolar transistor is regularly switched on.
In order to solve that problem, German Patent DE 196 01 369 C1 proposes connecting the wells in which the transistors are disposed to the respective source connections of the transistors since, in the steady state, the most negative voltage in each case is present there. However, that assumption is in fact only true for the steady final state of the charge pump circuit, which will never actually occur in practice since the charge pump is continually discharged by a load.
As soon as the known circuit is switched on the well will be at a potential which corresponds to the clock signal voltage and is higher than the drain connection, and the bipolar transistor will therefore switch on. The result will be a massive efficiency loss since the charge pump firstly does not achieve the theoretically possible maximum output voltage and secondly adopts the output voltage to be reached much more slowly.
It is accordingly an object of the invention to provide a circuit configuration for producing negative voltages, a charge pump having at least two circuit configurations and a method of operating a charge pump, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and in which the circuit configuration has a high level of efficiency.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for producing negative voltages, comprising at least one triple well; an input connection and an output connection of the circuit configuration; first and second clock signal connections; a first MOS transistor produced in the at least one triple well and having a first connection connected to the input connection, a second connection connected to the output connection, and a gate connection; a first capacitor connected between the gate connection of the first transistor and the first clock signal connection; a second MOS transistor produced in the at least one triple well and having a first connection connected to the gate connection of the first transistor, a second connection connected to the second connection of the first transistor, and a gate connection connected to the first connection of the first transistor; a second capacitor having a first connection connected to the second connection of the first transistor and a second connection connected to the second clock signal connection; and a third transistor having a first connection connected to the second connection of the first transistor, a second connection connected to the well containing the transistors, and a gate connection connected to the first connection of the first transistor.
In the circuit configuration according to the invention and the charge pump formed from a plurality of circuit configurations of this type, a third transistor is provided which connects the well to the source connection of the first (charging) transistor only when the potential at the source connection is more negative than the potential at the drain connection of the first transistor. In this case the well capacitor which is produced by the pn depletion layer between the two wells is charged up to the source potential and keeps the well at this potential for a sufficient time, even when the third transistor is switched off again, because the drain connection potential of the first transistor is more negative than the source connection potential of this transistor.
In accordance with another feature of the invention, there is provided a fourth transistor which connects the well to the drain connection of the first transistor when the drain connection potential is more negative than the source connection potential of the first transistor. In this embodiment, the well capacitor is therefore always charged to the more negative potential, with the result that no steady states can occur in which the well is more positive than one of the connections of the first transistor and consequently a parasitic bipolar transistor is switched on.
In accordance with a further feature of the invention, there is provided a capacitor disposed between the drain connection of the first transistor and the well. Like the well capacitor, this capacitor is charged up to the source connection potential during the switched-on phase of the third capacitor and is connected in series with the well capacitor in the off phase of the third transistor. As a result, the voltage across the well capacitor is shifted to more negative values when the drain connection potential drops. The well is therefore more negative than would be possible purely by charging through the source connection of the first transistor.
With the objects of the invention in view, there is also provided a charge pump for generating negative voltages, comprising at least two of the circuit configurations connected in series, the circuit configurations including a first circuit configuration, and the input connection of the first circuit configuration connected to ground potential.
The charge pump is created by connecting a plurality of circuit configurations according to the invention in series, so that voltages of -12 V or even -20 V can be produced. Such charge pumps are necessary for programming and/or erasing non-volatile memories, in particular flash-EPROM memories, using chip supply voltages of only 2.5 V.
With the objects of the invention in view, there is additionally provided a method of operating the charge pump, which comprises shifting clock signals at the clock signal connections of a respective one of the circuit configurations by half a clock period of clock signals of a preceding one of the circuit configurations.
In a charge pump of this type a first and a second clock signal are applied to odd-numbered circuit configurations, and third and fourth clock signals are applied to even-numbered circuit configurations. The latter clock signals have the same waveform as the first and second clock signals, but are shifted by half a period.
In accordance with a concomitant mode of the invention, the clock signals at the second clock signal connection of the circuit configurations have a duty ratio of more than 0.5, so that the second and fourth clock signals overlap. As a result of this, the first transistors are precharged, which leads to an increase in efficiency.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for producing negative voltages, a charge pump having at least two circuit configurations and a method of operating a charge pump, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
FIG. 1 is a detailed schematic diagram of a circuit configuration according to the invention;
FIG. 2 is a fragmentary, diagrammatic, cross-sectional view illustrating the way in which a circuit configuration of this type is produced in a p-substrate using triple-well technology;
FIG. 3 is a circuit diagram of a first embodiment of a charge pump;
FIG. 4 is a circuit diagram of a second embodiment of a charge pump;
FIG. 5 is a circuit diagram of a third embodiment of a charge pump; and
FIG. 6 is a graph showing a time profile of clock signals.
Referring now to the figures of the drawings in detail and first, particularly, to FIG. 1 thereof, there is seen a circuit configuration according to the invention, that can be regarded as one stage of a multi-stage charge pump for producing a negative voltage. In the circuit configuration, a first NMOS transistor Tx2 is connected between an input connection E and an output connection A.
As is shown in FIG. 2, the first transistor Tx2 is produced in a p-well which is in turn disposed in a deep, insulating n-well. This deep n-well is produced in a p-substrate. Both the n-well and the p-substrate are connected to ground.
A gate connection of the first transistor Tx2 is connected through a first capacitor Cb2 to a first clock signal connection, to which a first clock signal F1 can be applied. A source connection of the first transistor Tx2 is connected to a first connection of a second capacitor Cp2. The second capacitor Cp2 has a second connection that is connected to a second clock signal connection, to which a second clock signal F2 can be applied.
The input connection E of the circuit configuration can be connected to an output connection of another, identical circuit configuration, as is shown in detail in FIG. 3 and indicated in FIG. 1 by a second capacitor Cp1 of the other circuit configuration. FIG. 3 also shows third and fourth clock signals F3 and F4 which are respectively applied to third and fourth clock signal connections.
As is shown in FIG. 6, the second and fourth clock signals F2 and F4 have the same time profile, but are shifted by half a clock period with respect to one another. As a result of this alternate application of a positive voltage to the second and fourth clock signal connections, charges from the second capacitor Cp1 of the further or preceding circuit configuration in a chain of circuit configurations according to FIG. 3 are pumped through the first transistor Tx2 to the second capacitor Cp2 of the following circuit configuration shown in FIG. 1. During the pumping phase, the first clock signal F1, having a time profile which is also shown in FIG. 6, brings the gate connection of this transistor to a potential which is positive with respect to the source connection of the first transistor Tx2, with the result that the latter is switched on. Advantageously, the clock signals F2 and F4 overlap somewhat, so that the first transistor is precharged before it is switched on by the first clock signal F1.
As a result of charges being pumped to the second capacitor Cp2, the latter is charged up and the output connection A as well as the source connection of the first transistor Tx2 that is connected to the output connection A become negative after the second clock signal F2 has been switched off. The source connection would therefore be more negative than the gate connection of the first transistor Tx2, with the result that the latter would not be switched off and the second capacitor Cp2 would be able to discharge again. For this reason, a second transistor Ty2 is connected between the gate connection and the source connection of the first transistor Tx2. A gate connection of this second transistor Ty2 is connected to a drain connection of the first transistor Tx2. This second transistor Ty2 also raises the gate connection of the first transistor Tx2 to the potential of the source connection of the first transistor Tx2, with the result that the latter is switched off.
The first capacitor Cb2 is provided to prevent the second capacitor Cp2 from discharging through the second transistor Ty2 and the first clock signal connection.
According to the invention, a third NMOS transistor Tz2 is connected between the source connection of the first transistor Tx2 and a connection of a well Kw in which the transistor Tz2 is produced. A gate connection of this NMOS transistor Tz2 is likewise connected to the drain connection of the first transistor Tx2.
As can be seen from FIG. 2, the second and the third transistors Ty2 and Tz2 are also disposed in the p-well in which the first transistor Tx2 is produced. As is indicated by dashed lines, they can also be produced in their own wells. However, the wells are advantageously connected to one another by lines.
Through the use of the third transistor Tz2, the well Kw which is represented in FIG. 1 by a node is kept at a negative potential. As a result, a pn junction between the p-well and the n-well is polarized in the reverse direction and no leakage current can flow. In addition, a well-well junction capacitor Cw is charged through the third transistor Tz2, with the result that the p-well is kept at the negative potential even when the third transistor Tz2 is switched off.
In addition, FIG. 2 shows a parasitic npn transistor Tp which is formed by the n+ -drain region of the first transistor Tx2, the p-well and the n-well. This parasitic transistor Tp is also indicated in FIG. 1. It can clearly be seen that this transistor would be switched on and would lead to a leakage current if the p-well were more positive than the drain connection of the first transistor Tx2. However, this is effectively prevented by the third transistor according to the invention.
As was already mentioned, a plurality of circuit configurations of this type according to the invention can be connected in series in order to produce not simply a negative voltage, but a negative voltage which is high in comparison with the supply voltage, as is necessary, for example, for programming and erasing flash-EPROM memories.
In FIG. 3, a number N of circuit configurations of this type according to FIG. 1 are connected in series. The first transistors are designated by reference symbols Tx1 to TxN. The other circuit components are numbered in an equivalent manner. The second capacitor CpN of the nth circuit configuration does not have a clock signal voltage applied to it since it is intended to tap off the negative high voltage at this point. A voltage of (N-1)·UO can be produced by using a charge pump of this type, which is formed of N pump stages as is shown in FIG. 3, if the input of the first pump stage is connected to ground and UO is the level of the clock signals. The clock signals F1-F4 in this case have the time profiles shown in FIG. 6. The clock signals F3 and F4 have the same time profile as the clock signals F1 and F2, but are shifted by half a clock period.
The clock signals F3 and P4 are applied to the odd-numbered pump stages of the charge pump according to FIG. 3 and the clock signals F1 and F2 are applied to the even-numbered pump stages.
FIG. 4 shows another embodiment of the invention. In the circuit configurations of the charge pump shown therein, fourth NMOS transistors Tza1-TzaN are disposed between the drain connections of the first transistors Tx1-TxN and the wells. Gate connections of the fourth transistors Tza1-TzaN are respectively connected to the source connections of the first transistors Tx1-TxN. The third transistors are designated therein by reference symbols Tzb1-TzbN.
The fourth transistors Tza1-TzaN ensure that, even if there is a lower potential at the drain connections of the first transistors Tx1-TxN than at the source connections of the latter, this lowest potential is switched through to the wells and the wells are therefore always at the lowest of the two potentials.
FIG. 5 shows an advantageous development of the circuit configuration according to FIG. 1 and of the charge pump according to FIG. 3, in which a third capacitor C3, instead of the fourth transistors Tza1-TzaN, is connected between the drain connections of the first transistors Tx1-TxN and the wells Kw. The third capacitors C3, together with the well-well capacitors Cw (which are not shown explicitly in FIG. 5), lead to a further drop in the well potential.
The charge pumps according to the invention which are shown in FIGS. 3 to 5 are characterized by a high level of efficiency, so that output voltages of -20 V can be achieved even with a small supply voltage of approximately 2.5 V.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5335200 *||Jan 5, 1993||Aug 2, 1994||Texas Instruments Incorporated||High voltage negative charge pump with low voltage CMOS transistors|
|US5422586 *||Sep 10, 1993||Jun 6, 1995||Intel Corporation||Apparatus for a two phase bootstrap charge pump|
|US5489870 *||Mar 17, 1994||Feb 6, 1996||Sony Corporation||Voltage booster circuit|
|US5589793 *||Sep 29, 1993||Dec 31, 1996||Sgs-Thomson Microelectronics S.A.||Voltage booster circuit of the charge-pump type with bootstrapped oscillator|
|US5612921 *||Feb 15, 1996||Mar 18, 1997||Advanced Micro Devices, Inc.||Low supply voltage negative charge pump|
|US5625544 *||Apr 25, 1996||Apr 29, 1997||Programmable Microelectronics Corp.||Charge pump|
|US5767733 *||Sep 20, 1996||Jun 16, 1998||Integrated Device Technology, Inc.||Biasing circuit for reducing body effect in a bi-directional field effect transistor|
|US5818758 *||Dec 31, 1996||Oct 6, 1998||Intel Corporation||Zero voltage drop negative switch for dual well processes|
|US5821805 *||Jun 27, 1997||Oct 13, 1998||Nec Corporation||Charge pump circuit having different threshold biases of the transistors|
|DE19601369C1 *||Jan 16, 1996||Apr 10, 1997||Siemens Ag||Voltage multiplier or providing negative high voltage|
|EP0319063A2 *||Nov 14, 1988||Jun 7, 1989||Philips Electronics N.V.||Voltage multiplier circuit and rectifier element|
|EP0349495A2 *||Jun 16, 1989||Jan 3, 1990||SGS-THOMSON MICROELECTRONICS S.r.l.||CMOS voltage multiplier|
|EP0616329A2 *||Mar 17, 1994||Sep 21, 1994||Sony Corporation||Voltage booster circuit|
|EP0678970A2 *||Apr 20, 1995||Oct 25, 1995||Nippon Steel Corporation||Semiconductor booster circuit|
|1||"A 5-V-Only Operation 0.6-μm Flash EEPROM with Row Decoder Scheme in Triple-Well Structure" (Umezawa et al.), 8107 IEEE Journal of Solid-State Circuits 27, No. 11, Nov. 1992.|
|2||*||A 5 V Only Operation 0.6 m Flash EEPROM with Row Decoder Scheme in Triple Well Structure (Umezawa et al.), 8107 IEEE Journal of Solid State Circuits 27, No. 11, Nov. 1992.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6285240 *||Jan 14, 1999||Sep 4, 2001||Macronix International Co., Ltd.||Low threshold MOS two phase negative charge pump|
|US6353356 *||Aug 30, 1999||Mar 5, 2002||Micron Technology, Inc.||High voltage charge pump circuits|
|US6570435 *||Nov 3, 2000||May 27, 2003||Texas Instruments Incorporated||Integrated circuit with current limited charge pump and method|
|US6642773 *||Aug 9, 2002||Nov 4, 2003||Ememory Technology Inc.||Charge pump circuit without body effects|
|US6677806 *||May 9, 2002||Jan 13, 2004||Infineon Technologies Ag||Charge pump for generating high voltages for semiconductor circuits|
|US6696883 *||Sep 20, 2000||Feb 24, 2004||Cypress Semiconductor Corp.||Negative bias charge pump|
|US6724239 *||May 28, 2002||Apr 20, 2004||Analog Devices, Inc.||Voltage boost circuit and low supply voltage sampling switch circuit using same|
|US6781897||Aug 1, 2002||Aug 24, 2004||Infineon Technologies Flash Ltd.||Defects detection|
|US6798269 *||Jan 6, 2003||Sep 28, 2004||Stmicroelectronics S.R.L.||Bootstrap circuit in DC/DC static converters|
|US6842383||Jan 30, 2003||Jan 11, 2005||Saifun Semiconductors Ltd.||Method and circuit for operating a memory cell using a single charge pump|
|US6885244||Mar 24, 2003||Apr 26, 2005||Saifun Semiconductors Ltd.||Operational amplifier with fast rise time|
|US6888400 *||Jul 17, 2003||May 3, 2005||Ememory Technology Inc.||Charge pump circuit without body effects|
|US6906966||Jun 16, 2003||Jun 14, 2005||Saifun Semiconductors Ltd.||Fast discharge for program and verification|
|US6914791||Jun 24, 2003||Jul 5, 2005||Halo Lsi, Inc.||High efficiency triple well charge pump circuit|
|US6952129 *||Jan 12, 2004||Oct 4, 2005||Ememory Technology Inc.||Four-phase dual pumping circuit|
|US6954101 *||Sep 22, 2003||Oct 11, 2005||Kabushiki Kaisha Toshiba||Potential detector and semiconductor integrated circuit|
|US7046076||Mar 26, 2004||May 16, 2006||Atmel Corporation||High efficiency, low cost, charge pump circuit|
|US7084697 *||Jun 28, 2004||Aug 1, 2006||Nec Electronics Corporation||Charge pump circuit capable of completely cutting off parasitic transistors|
|US7135911||Sep 13, 2005||Nov 14, 2006||Kabushiki Kaisha Toshiba||Potential detector and semiconductor integrated circuit|
|US7148739 *||Dec 19, 2002||Dec 12, 2006||Saifun Semiconductors Ltd.||Charge pump element with body effect cancellation for early charge pump stages|
|US7176728||Feb 10, 2004||Feb 13, 2007||Saifun Semiconductors Ltd||High voltage low power driver|
|US7187595||Jun 8, 2004||Mar 6, 2007||Saifun Semiconductors Ltd.||Replenishment for internal voltage|
|US7190212||Jun 8, 2004||Mar 13, 2007||Saifun Semiconductors Ltd||Power-up and BGREF circuitry|
|US7224206 *||Feb 24, 2005||May 29, 2007||Stmicroelectronics S.R.L.||Charge-pump with improved biasing of the body regions of the pass-transistors|
|US7256438||Jun 8, 2004||Aug 14, 2007||Saifun Semiconductors Ltd||MOS capacitor with reduced parasitic capacitance|
|US7301388 *||Dec 22, 2004||Nov 27, 2007||Mosel Vitelic Corporation||Charge pump with ensured pumping capability|
|US7307466||Nov 9, 2006||Dec 11, 2007||Kabushiki Kaisha Toshiba||Potential detector and semiconductor integrated circuit|
|US7477093||Dec 31, 2006||Jan 13, 2009||Sandisk 3D Llc||Multiple polarity reversible charge pump circuit|
|US7495500||Dec 31, 2006||Feb 24, 2009||Sandisk 3D Llc||Method for using a multiple polarity reversible charge pump circuit|
|US7652522||Sep 5, 2006||Jan 26, 2010||Atmel Corporation||High efficiency low cost bi-directional charge pump circuit for very low voltage applications|
|US7652930||Apr 3, 2005||Jan 26, 2010||Saifun Semiconductors Ltd.||Method, circuit and system for erasing one or more non-volatile memory cells|
|US7668017||Aug 17, 2005||Feb 23, 2010||Saifun Semiconductors Ltd.||Method of erasing non-volatile memory cells|
|US7675782||Oct 17, 2006||Mar 9, 2010||Saifun Semiconductors Ltd.||Method, system and circuit for programming a non-volatile memory array|
|US7692961||Aug 2, 2006||Apr 6, 2010||Saifun Semiconductors Ltd.||Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection|
|US7696812||Jan 12, 2009||Apr 13, 2010||Sandisk 3D Llc||Cooperative charge pump circuit and method|
|US7701779||Sep 11, 2006||Apr 20, 2010||Sajfun Semiconductors Ltd.||Method for programming a reference cell|
|US7738304||Oct 11, 2005||Jun 15, 2010||Saifun Semiconductors Ltd.||Multiple use memory chip|
|US7743230||Feb 12, 2007||Jun 22, 2010||Saifun Semiconductors Ltd.||Memory array programming circuit and a method for using the circuit|
|US7760554||Aug 2, 2006||Jul 20, 2010||Saifun Semiconductors Ltd.||NROM non-volatile memory and mode of operation|
|US7786512||Jul 18, 2006||Aug 31, 2010||Saifun Semiconductors Ltd.||Dense non-volatile memory array and method of fabrication|
|US7808818||Dec 28, 2006||Oct 5, 2010||Saifun Semiconductors Ltd.||Secondary injection for NROM|
|US7855591||Jun 7, 2006||Dec 21, 2010||Atmel Corporation||Method and system for providing a charge pump very low voltage applications|
|US7964459 *||Dec 10, 2009||Jun 21, 2011||Spansion Israel Ltd.||Non-volatile memory structure and method of fabrication|
|US8339102||Nov 15, 2004||Dec 25, 2012||Spansion Israel Ltd||System and method for regulating loading on an integrated circuit power supply|
|US8344857 *||Nov 30, 2011||Jan 1, 2013||Impinj, Inc.||RFID tags with synchronous power rectifier|
|US8981836 *||Aug 6, 2013||Mar 17, 2015||Infineon Technologies Ag||Charge pumps with improved latchup characteristics|
|US9000524 *||Apr 6, 2011||Apr 7, 2015||Taiwan Semiconductor Manufacturing Company, Ltd.||Method and apparatus for modeling multi-terminal MOS device for LVS and PDK|
|US20040119525 *||Dec 19, 2002||Jun 24, 2004||Shor Joseph S.||Charge pump element with body effect cancellation for early charge pump stages|
|US20040151032 *||Jan 30, 2003||Aug 5, 2004||Yan Polansky||High speed and low noise output buffer|
|US20040222841 *||Jul 17, 2003||Nov 11, 2004||Hong-Chin Lin||Charge pump circuit without body effects|
|US20040233771 *||Jul 1, 2004||Nov 25, 2004||Shor Joseph S.||Stack element circuit|
|US20050017792 *||Jun 28, 2004||Jan 27, 2005||Nec Electronics Corporation||Charge pump circuit capable of completely cutting off parasitic transistors|
|US20050088220 *||Aug 24, 2004||Apr 28, 2005||Hahn Wook-Ghee||Charge pump circuit having high charge transfer efficiency|
|US20050122757 *||Dec 3, 2003||Jun 9, 2005||Moore John T.||Memory architecture and method of manufacture and operation thereof|
|US20050151580 *||Jan 12, 2004||Jul 14, 2005||Hong-Chin Lin||Four-phase dual pumping circuit|
|US20050174152 *||Feb 10, 2004||Aug 11, 2005||Alexander Kushnarenko||High voltage low power driver|
|US20050174709 *||Nov 15, 2004||Aug 11, 2005||Alexander Kushnarenko||Method and apparatus for adjusting a load|
|US20050200399 *||Feb 24, 2005||Sep 15, 2005||Stmicroelectronics S.R.L.||Charge-pump with improved biasing of the body regions of the pass-transistors|
|US20050212586 *||Mar 26, 2004||Sep 29, 2005||Jean-Michel Daga||High efficiency, low cost, charge pump circuit|
|US20050269619 *||Jun 8, 2004||Dec 8, 2005||Shor Joseph S||MOS capacitor with reduced parasitic capacitance|
|US20050270089 *||Jun 8, 2004||Dec 8, 2005||Shor Joseph S||Power-up and BGREF circuitry|
|US20060006926 *||Sep 13, 2005||Jan 12, 2006||Kabushiki Kaisha Toshiba||Potential detector and semiconductor integrated circuit|
|US20120256271 *||Apr 6, 2011||Oct 11, 2012||Taiwan Semiconductor Manufacturing Company, Ltd.||Method and Apparatus for Modeling Multi-terminal MOS Device for LVS and PDK|
|US20130321045 *||Aug 6, 2013||Dec 5, 2013||Infineon Technologies Ag||Charge pumps with improved latchup characteristics|
|CN101459377B||Dec 14, 2007||Sep 28, 2011||鸿富锦精密工业（深圳）有限公司||Circuit for generating negative voltage|
|WO2008030728A2 *||Aug 27, 2007||Mar 13, 2008||Atmel Corp||High efficiency low cost bi-directional charge pump circuit for very low voltage applications|
|U.S. Classification||327/536, 327/537|
|International Classification||G11C16/30, H02M3/07|
|Cooperative Classification||H02M3/073, H02M2003/078, G11C16/30, H02M2003/075|
|European Classification||G11C16/30, H02M3/07S|
|Jul 27, 2000||AS||Assignment|
|Mar 22, 2004||FPAY||Fee payment|
Year of fee payment: 4
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|May 31, 2011||AS||Assignment|
Owner name: INFINEON TECHNOLOGIES AG, GERMANY
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Effective date: 19990331
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