|Publication number||US6169320 B1|
|Application number||US 09/012,083|
|Publication date||Jan 2, 2001|
|Filing date||Jan 22, 1998|
|Priority date||Jan 22, 1998|
|Also published as||EP0932189A2, EP0932189A3, EP1975989A2, EP1975989A3, US6258652|
|Publication number||012083, 09012083, US 6169320 B1, US 6169320B1, US-B1-6169320, US6169320 B1, US6169320B1|
|Inventors||William F. Stacey|
|Original Assignee||Raytheon Company|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Referenced by (25), Classifications (13), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates generally to inductor structures and manufacturing methods and more particularly to spiral inductors adapted for use in monolithic microwave integrated circuits.
As is known in the art, active devices, such as transistors, and passive devices, such as resistors, capacitors and inductors, have been formed on a common single crystal substrate, such as gallium arsenide (GaAs), as a microwave monolithic integrated circuit. One technique used to form the inductor has been to: first form the active devices in the gallium arsenide, deposit a passivation layer of silicon nitride over the processed gallium arsenide, and pattern a layer of photoresist deposited over the silicon nitride layer with a spiral shaped window formed therein. Next, a sequence of titanium followed by gold is deposited over the photoresist layer and through the spiral shaped window onto the exposed portions of the silicon nitride. The photoresist layer is then removed, i.e., “lifted-off”, leaving a spiral shaped inductor on the silicon nitride passivation layer.
While such technique has been useful in many application, the inductor has a relatively low impedance resulting in a relatively narrow bandwidth device.
In accordance with one feature of the invention, an inductor structure is provided. The inductor has a dielectric body. A spiral shaped pedestal is disposed in one surface of the body. A ground plane conductor is disposed over an opposite surface of the body. A spiral shaped conductor is disposed over the spiral shaped dielectric pedestal.
With such structure, a portion of the electric field in the conductor passes through air having a relatively low dielectric constant thereby increasing the impedance and bandwidth of the inductor.
In accordance with another feature of the invention a method is provided for making an inductor structure. The method includes the steps of: providing a dielectric body; patterning a metalization layer disposed over the dielectric body into a spiral shaped electrical conductor; etching surface portions of the dielectric body exposed by the patterned metalization layer providing a pedestal structure disposed under the patterned metalization layer.
In a preferred embodiment, after the metalization layer has been patterned, a third photoresist layer is deposited over the formed surface. A window is formed in the third photoresist layer over the patterned metalization layer. Exposed portions of the passivation layer are removed. Exposed portions of the dielectric body are removed using a dry, vertically directional etch to produce an inductive structure.
These and other features of the invention, as well as the invention itself, will become more readily apparent from the following detailed description when read together with the following drawings, in which:
FIG. 1 is a plan view of a substrate having a patterned photolithograph layer disposed over the surface of the substrate at one stage in the fabrication of an inductor in accordance with the invention;
FIGS. 1A and 1B are diagrammatical cross-section elevation views taken along lines 1A—1A and 1B—1B in FIG. 1;
FIG. 2 is a plan view of the substrate having a different photolithograph layer disposed over the surface of the substrate at another stage in the fabrication of an inductor in accordance with the invention;
FIGS. 2A and 2B are diagrammatical cross-section elevation views taken along lines 2A—2A and 2B—2B in FIG. 2;
FIG. 3 is a plan view of the substrate having the different photolithograph layer patterned at still another stage in the fabrication of an inductor in accordance with the invention;
FIGS. 3A and 3B are diagrammatical cross-section elevation views taken along lines 3A—3A and 3B—3B in FIG. 3;
FIG. 4 is a plan view of the substrate having a metalization layer disposed over the patterned different photolithograph layer at yet another stage in the fabrication of an inductor in accordance with the invention;
FIGS. 4A, 4B and 4C are diagrammatical cross-section elevation views taken along lines 4A—4A, 4B—4B and 4C—4C in FIG. 4;
FIG. 5 is a plan view of the substrate having a patterned metalization layer at another stage in the fabrication of an inductor in accordance with the invention;
FIGS. 5A, 5B and 5C are diagrammatical cross-section elevation views taken along lines 5A—5A, 5B—5B and 5C—5C in FIG. 5;
FIG. 5D is a perspective partially broken away sketch of a portion of the structure of FIG. 5, such portion being enclosed by a circle labelled 5D—5D in FIG. 5;
FIG. 6 is a plan view of the inductor in the invention;
FIGS. 6A, 6B and 6C are diagrammatical cross-section elevation views taken along lines 6A—6A, 6B—6B and 6C—6C in FIG. 6;
FIG. 6D is a perspective partially broken away sketch of the inductor in accordance with the invention, such portion being enclosed by a circle labelled 6D—6D in FIG. 6.
Referring now to FIGS. 1, 1A and 1B, a single crystal substrate 10, here semi-insulating gallium arsenide is shown having a doped layer 12 of gallium arsenide epitaxially grown over the upper surface o the substrate 10. In one region, not shown, of the epitaxial layer 12 may be formed active devices, such as field effect transistors, while an inductor structure 100 (FIGS. 6, 6A, 69, 6C and 6D) is formed in a manner to be described in the region shown.
An insulating, or passivation, layer, here typically silicon nitride 14, is formed over the surface of the epaxial layer 12, as shown. Next, a first photoresist layer 16, here polymethylglutarimide (PMGI), is formed over the passivation layer 14. The first photoresist layer 16 is selectively masked with unmasked portions being exposed to deep ultra-violent light in a conventional manner to form, after development, a segmented spiral shaped pattern as shown more clearly in FIG. 1.
Next, and referring to FIGS. 2, 2A, and 2B, a second photoresist layer 18, here Novolac, is deposited over the patterned first photoresist layer 16 and over portions of the passivation layer 16 exposed by the patterned first photoresist layer 16. The second photoresist layer 18 is masked and exposed to a less deep ultra-violet light to pattern it with a spiral shaped window disposed over and in vertical alignment with the segmented first photoresist layer 16, as shown in FIGS. 3, 3A and 3B. As will be shown, the window formed in the second photoresist layer is in the same shape as the spiral shaped inductor being formed. Further, an electrical contact pad will be formed in the central region 22 of the inductor and a window is thus formed in the second photoresist layer 18 in the shape of the contact pad.
Next, a metalization layer 24, here a composite lower layer of titanium followed by a thicker layer of gold, is formed over the second photoresist 18 and through the window formed therein onto the patterned first photoresist layer 16 and onto the exposed portions of the passivation layer 14, as shown in FIGS. 4, 4A, 4B and 4C.
Next, the second photoresist layer 18, together with the portions of the metalization layer 24 disposed thereon are removed (i.e., “lifted-off”) with acetone leaving a spiral shaped metalization layer, as shown in FIGS. 5, 5A, 5B, 5C and 5D.
Next, the first photoresist layer 16 is removed here using n-methyl pyrolidinone, as shown in FIGS. 6, 6A, 6B, 6C and 6D to provide air-bridged segments 29 which pass over air 31, as shown.
Next, a third photoresist layer not shown, here Novolac, is spun over the formed surface. Next, a window is formed in the third photoresist layer over the patterned metalization layer 24. Next, the exposed portions of the passivation layer 14 are removed, here using a dry etch, here a plasma etch using nitrogen tri-fluoride. Next, exposed portions of the single crystal body 10 are etched here using a dry, vertically directional etch of tetrachloride or boron tri-chloride, for example, to provide the structure shown in FIGS. 6, 6A, 6B, 6C and 6D.
Next, a ground plane conductor 30 is disposed on the bottom surface of the substrate 10 to provide the inductor structure 100 shown in FIGS. 6, 6A, 6B, 6C and 6D.
Thus, with such method an inductor structure is formed in the single crystal body with a spiral shaped pedestal disposed in the upper surface of the body. The body is a dielectric body having a ground plane conductor disposed over a lower surface and a spiral shaped conductor disposed over the spiral shaped pedestal. Portions of the conductor are separated from underlying portions of the pedestal by air and laterally adjacent portions of the conductor are separated by air.
Other embodiments are within the spirit and scope of the appended claims. For example, the dielectric may be material other than semiconductor material.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4729510 *||Nov 14, 1984||Mar 8, 1988||Itt Corporation||Coaxial shielded helical delay line and process|
|US5095357 *||Aug 14, 1990||Mar 10, 1992||Mitsubishi Denki Kabushiki Kaisha||Inductive structures for semiconductor integrated circuits|
|US5372967 *||May 2, 1994||Dec 13, 1994||Motorola, Inc.||Method for fabricating a vertical trench inductor|
|US5410179 *||Apr 5, 1990||Apr 25, 1995||Martin Marietta Corporation||Microwave component having tailored operating characteristics and method of tailoring|
|US5652157 *||Feb 28, 1996||Jul 29, 1997||Nippon Telegraph And Telephone Corporation||Forming a gate electrode on a semiconductor substrate by using a T-shaped dummy gate|
|US5719073 *||Sep 27, 1994||Feb 17, 1998||Cornell Research Foundation, Inc.||Microstructures and single mask, single-crystal process for fabrication thereof|
|US5773870 *||Sep 10, 1996||Jun 30, 1998||National Science Council||Membrane type integrated inductor and the process thereof|
|US6002161 *||Nov 26, 1996||Dec 14, 1999||Nec Corporation||Semiconductor device having inductor element made of first conductive layer of spiral configuration electrically connected to second conductive layer of insular configuration|
|US6008102 *||Apr 9, 1998||Dec 28, 1999||Motorola, Inc.||Method of forming a three-dimensional integrated inductor|
|JPH0621533A||Title not available|
|JPS61144052A||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6542379 *||Jul 15, 1999||Apr 1, 2003||International Business Machines Corporation||Circuitry with integrated passive components and method for producing|
|US6727571 *||Nov 8, 2002||Apr 27, 2004||Murata Manufacturing Co., Ltd.||Inductor and method for adjusting the inductance thereof|
|US6765455||Nov 9, 2000||Jul 20, 2004||Merrimac Industries, Inc.||Multi-layered spiral couplers on a fluropolymer composite substrate|
|US6774743||Apr 1, 2002||Aug 10, 2004||Merrimac Industries, Inc.||Multi-layered spiral couplers on a fluropolymer composite substrate|
|US6791158 *||Aug 3, 2001||Sep 14, 2004||Stmicroelectronics S.A.||Integrated inductor|
|US6908825 *||Nov 14, 2002||Jun 21, 2005||Institute Of Microelectronics||Method of making an integrated circuit inductor wherein a plurality of apertures are formed beneath an inductive loop|
|US7087976 *||Feb 9, 2004||Aug 8, 2006||Intel Corporation||Inductors for integrated circuits|
|US7127808||May 6, 2004||Oct 31, 2006||Merrimac Industries, Inc.||Spiral couplers manufactured by etching and fusion bonding|
|US7148553||Aug 1, 2001||Dec 12, 2006||Davies Robert B||Semiconductor device with inductive component and method of making|
|US7319377 *||May 28, 2004||Jan 15, 2008||Megica Corporation||Method for making high-performance RF integrated circuits|
|US7327010||Mar 27, 2006||Feb 5, 2008||Intel Corporation||Inductors for integrated circuits|
|US7960269||Jul 24, 2006||Jun 14, 2011||Megica Corporation||Method for forming a double embossing structure|
|US7973629||Oct 31, 2007||Jul 5, 2011||Megica Corporation||Method for making high-performance RF integrated circuits|
|US8384508||Feb 26, 2013||Megica Corporation||Method for making high-performance RF integrated circuits|
|US9230726||Feb 20, 2015||Jan 5, 2016||Crane Electronics, Inc.||Transformer-based power converters with 3D printed microchannel heat sink|
|US20030071325 *||Nov 14, 2002||Apr 17, 2003||Shuming Xu||Method of making an integrated circuit inductor|
|US20030178694 *||Aug 3, 2001||Sep 25, 2003||Frederic Lemaire||Integrated inductor|
|US20040157370 *||Feb 9, 2004||Aug 12, 2004||Intel Corporation||Inductors for integrated circuits, integrated circuit components, and integrated circuit packages|
|US20040207482 *||May 6, 2004||Oct 21, 2004||Merrimac Industries, Inc.||Spiral couplers|
|US20040217840 *||May 28, 2004||Nov 4, 2004||Megic Corporation||Method for making high-performance RF integrated circuits|
|US20060163695 *||Mar 27, 2006||Jul 27, 2006||Intel Corporation||Inductors for integrated circuits|
|US20070045855 *||Jul 24, 2006||Mar 1, 2007||Megica Corporation||Method for forming a double embossing structure|
|US20110175195 *||Jul 21, 2011||Megica Corporation||Method for making high-performance rf integrated circuits|
|US20110215469 *||Sep 8, 2011||Megica Corporation||Method for forming a double embossing structure|
|WO2001071809A1 *||Mar 9, 2001||Sep 27, 2001||Robert Bruce Davies||A die attachment surface having pedestals for receiving components and method of using the attachment|
|U.S. Classification||257/531, 257/E21.022, 257/E21.581, 336/200|
|International Classification||H01L21/02, H01L21/768, H01F17/00|
|Cooperative Classification||H01F17/0006, H01L21/7682, H01L28/10|
|European Classification||H01L28/10, H01L21/768B6, H01F17/00A|
|Jan 22, 1998||AS||Assignment|
Owner name: RAYTHEON COMPANY, MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STACEY, WILLIAM F.;REEL/FRAME:009004/0241
Effective date: 19980115
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