|Publication number||US6208195 B1|
|Application number||US 08/934,322|
|Publication date||Mar 27, 2001|
|Filing date||Mar 17, 1992|
|Priority date||Mar 18, 1991|
|Publication number||08934322, 934322, PCT/1992/2168, PCT/US/1992/002168, PCT/US/1992/02168, PCT/US/92/002168, PCT/US/92/02168, PCT/US1992/002168, PCT/US1992/02168, PCT/US1992002168, PCT/US199202168, PCT/US92/002168, PCT/US92/02168, PCT/US92002168, PCT/US9202168, US 6208195 B1, US 6208195B1, US-B1-6208195, US6208195 B1, US6208195B1|
|Inventors||David C. Wyland|
|Original Assignee||Integrated Device Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (109), Non-Patent Citations (53), Referenced by (12), Classifications (15), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of application Ser. No. 08/563,139, filed Nov. 27, 1995, now abandoned which is a continuation of application Ser. No. 08/119,156, filed May 6, 1994, now abandoned, which is a National Phase application of PCT/US92/02168, filed Mar. 17, 1992, which is a continuation-in-part of application Ser. No. 07/672,050, filed Mar. 18, 1991, now abandoned.
This invention relates in general to signal switches and in particular, to a fast transmission gate switch, particularly useful for switching digital logic signals.
With the advent of very large-scale integrated circuits, the size of devices manufactured has been shrinking and the speed of the devices has continually increased. Most of the efforts, however, have been directed to designs where many circuits and the connections between them are made in the same medium such as a silicon chip. Since all the circuit components being fabricated are done in the same medium, devices may be made smaller by improved techniques such as improved lithography. By reducing the sizes of the devices and the lengths of the connections between them, the speed of the devices is increased due to a decrease in the inductances, resistances and capacitances of individual devices and of the connections between them.
Board level designs have not kept pace with the above-described development in very large-scale integrated circuits. Printed circuit board designs frequently have large capacitances which slow down signal propagation. Thus if two high speed logic chips are connected through a slower device, the overall speed of the system is determined by the slowest component, namely, the slow connecting device. Passive switching devices such as transmission gates have been used in printed circuit board level designs for switching signals between digital logic devices. The slow speed of this type of switches determines the speed of signal transmission even though the two logic devices may operate at much higher speeds. It is therefore desirable to provide a stand-alone switching device which is much faster than the conventional passive transmission gate.
In one type of improved switching circuits that is frequently used, instead of a passive switch, an active device such as a logic buffer is used. While a buffer used as a switch causes a delay that is less than that caused by the conventional passive transmission gate switch, the delay caused by such buffers may nevertheless be excessive and undesirable for some high speed applications. It is thus desirable to provide a high speed switch that causes less delay than the above described switches.
This invention is directed towards a stand-alone switch for switching signals between two nodes, where the two nodes are connected to conductors such as conducting traces on a printed circuit board, so that a signal propagating from one node to the other will experience an external capacitance Cb. The switch comprises two input/output pins and a switching pin, and a first transistor having a control terminal and a first and a second input/output terminal. Each input/output terminal of the transistor is connected to one of the nodes through an input/output pin for passing signals between the nodes through the transistor when the transistor is turned on and disconnecting the two nodes when the transistor is turned off. The switch further comprises means responsive to a switching signal at the switching pin for applying a control signal to the control terminal of the transistor for turning it on or off. The delay of signals passing through the switch is at least equal to the RC delay, which is the product of the resistance Ri of the transistor between the two input/output pins and the sum of the internal capacitance Ci of the switch and the external (e.g., bus) capacitance Cb. The values of Ri and Ci are such that, for a given value of Cb, Ri(Ci+Cb) is less than the delay through a typical buffer, e.g. 6.5 nanoseconds. Hence, replacing the conventional buffer by the switch of this invention will reduce delay in signal propagation between the two nodes.
In the preferred embodiment, the applying means and the capacitance between the two input/output pins and the control terminal when the transistor is turned on are such that time required for the switching signal to turn on or off the transistor through the applying means is less than the time to turn on or off a typical buffer, e.g. 7 nanoseconds.
FIG. 1 is a schematic circuit diagram of a passive transmission gate switch and of a driver and receiver illustrating a conventional design of the switch.
FIG. 2 is a schematic view of an active switch device using an enabled buffer and of a driver and receiver to illustrate another conventional design.
FIG. 3 is a perspective view of a MOS transistor useful for illustrating the invention.
FIG. 4 is a cross-sectional view of the transistor of FIG. 3.
FIG. 5A is a schematic circuit diagram of a transmission gate switch and of a driver and receiver to illustrate the preferred embodiment of the invention.
FIG. 5B is a partially cross-sectional view and partially schematic view of the transmission gate switch of FIG. 5A.
FIG. 5C is a schematic circuit diagram illustrating in more detail one embodiment of the driver 104 of FIG. 5B.
FIG. 5D is a schematic view of the switch of FIG. 5B, illustrating in more detail the capacitances of the switch.
FIG. 5E is a conceptual circuit diagram illustrating the RC delay experienced by a signal propagating from node A to node B to illustrate the invention.
FIG. 6 is a schematic circuit diagram of a transmission gate switch and of a driver and receiver to illustrate an alternative embodiment of the invention.
FIGS. 7 and 8 are schematic circuit diagrams of two different transmission gate switches to illustrate additional alternative embodiments of the invention.
FIG. 9 is a schematic view of a bus switch for switching signals between two sets of bus lines to illustrate applications of the invention.
FIG. 10 is a schematic circuit diagram of a bus exchange switch to illustrate applications of the invention.
FIGS. 11A, 11B are schematic circuit diagrams illustrating the operation of the circuit in FIGS. 5A-5D.
FIG. 12A is a block diagram of a computer system illustrating the applications of the invention.
FIG. 12B is a timing diagram illustrating the operation of the system in FIG. 12A.
FIG. 1 is a schematic circuit diagram of a conventional transmission gate switch 20 connected to the output of a driver 22 and the input of a receiver 24 at nodes A, B respectively. The signal to be switched appears at the output of driver 22. When switch 20 connects nodes A and B, such signal is transmitted to node B and appears at the input of receiver 24. Driver 22 and receiver 24 may each be part of another circuit chip package mounted on a printed circuit board where switch 20 is connected by conductive traces 22 through nodes A, B to these chip packages.
Switch 20 has resistance R so that the switch may be represented conceptually as a resistor 26 in series with a pure switch 28 as shown in FIG. 1. A signal propagating between nodes A and B will experience capacitive effects of traces 32 connecting switch 20 and receiver 24, of the receiver 24 and switch 20. Switch 20 is typically employed in the form of an electronic package with pins connected to nodes A, B. As defined on pages 705, 706 of Modern Microelectronic Circuit Design, IC Applications, Fabrication Technology, Vol. 2, by staff of Research and Education Association, Dr. Folgiel, Director, Research and Education Association, New York, N.Y. 1981, the parasitic capacitance of an electronic device package with leads or pins can be of two types, inter-lead capacitance and capacitance from lead-to-ground. Switch 20 has three leads, one connected to driver 22, the other connected to receiver 24 by traces 32 on a printed circuit board, and a third lead for the switch enable signal. There will be inter-lead capacitances between the three leads of switch 20, and there will also be capacitances between the three leads of switch 20 and ground.
The above described inter-lead and lead-to-ground capacitances of package 20, those introduced by traces 32 and other board level connections are represented conceptually by capacitor 30 connected between node B and ground and labeled “parasitic capacitance” in FIG. 1. Since this parasitic capacitance represented by the capacitor is inherent in the switch, capacitor 30 is shown in dotted lines. Obviously, the inter-lead capacitances as well as the lead-to-ground capacitances of switch 20 would depend on the size, geometry, material and the exact configuration of the package 20, its leads, and of traces 32 and other board level connections. The total internal capacitance of switch 20 is given by the total capacitive effect of the parasitic capacitance of capacitor 30, and the capacitance of other portions of switch 20, the value of which will depend on the structure of the switch. Therefore, the total capacitance seen by a signal propagating between nodes A and B is given by the effects of the internal capacitance of switch 20, the capacitance of receiver 24, and the capacitance of traces 32 connecting switch 20 to receiver 24. Thus the delay of the signal propagating from node A to node B is caused by two RC delays: (1) the product of the resistance R of resistor 26 and the capacitance of trace 32 connecting switch 20 and receiver and of receiver 24, and (2) the product of the resistance R of resistor 26 and the internal capacitance 30. The second (2) product will depend on the specific structure of switch 20, and will be omitted for now, since the first product alone makes switch 20 unsuitable for use in high speed switching between logic devices, as will be clear from the discussion below.
In typical printed circuit board designs for computer and logic applications, a typical capacitance of the bus (e.g., that of trace 32, of receiver 24 and other associated circuitry whose capacitance effects will be felt at node B) downstream from switch 20 is about 50 pF. Therefore, if switch 20 has a large resistance value, the RC time constant resulting from such resistance and the typical bus capacitance of 50 pF will be large, resulting in a significant signal delay when the signal propagates from A to B. The propagation delay introduced by the switch is therefore at least equal to the value of the RC time constant. A standard transmission gate switch is the CMOS 4016 integrated circuit. The typical resistance values of existing transmission gate switches such as the 4016 are in the range of 250-1,000 ohms. This type of switch would therefore introduce at least a delay of the order of 12-50 nanoseconds, assuming a 50 pF bus capacitance. Such delay is unacceptable for switching high speed signals required in many computer and logic applications. For this reason, the 4016 type switch is more commonly used in analog circuits and seldom in board level computer or digital logic designs. For the latter applications, active logic devices such as industry standard 74F244 buffers have been used such as shown in FIG. 2. To simplify the discussion, identical components and the figures of this application are identified by the same numerals.
As shown in FIGS. 1 and 2, transmission gate switch 20 has been replaced by a logic buffer 40 in FIG. 2. Driver 22 and receiver 24 may be part of computer or logic chip packages mounted on a printed circuit board and connected to buffer 40 by conductive traces 32 on the board. Buffer 40 is also in the form of a package having inter-lead and lead-to-ground parasitic capacitance, whose values may be different from those of switch 20; for this reason, such parasitic capacitances of buffer 40 are represented by capacitor 30′, also shown in dotted lines. Buffer 40, however, introduces a delay of its own because of the inherent speed limitations of active logic. The 74F244 buffer driving a 50 pF load introduces a delay of about 6.5 nanoseconds. Thus while using a logic buffer 40 to replace switch 20 does reduce the delay in signal transmission, it is difficult to further reduce the delay introduced by the buffer itself. It is therefore desirable to provide an improved switching device where the above-described difficulties are alleviated.
This invention is based on the observation that, by employing a transistor having low inherent resistance and internal capacitance, the signal delay of the switch can be further reduced to a value below that of the active buffer in FIG. 2.
FIG. 3 is a perspective view of a MOS transistor useful for illustrating the invention. FIG. 4 is a cross-sectional view of the transistor of FIG. 3. As shown in FIGS. 3 and 4, the channel length of a MOS type transistor is the distance L between the source and drain regions of the transistor while the channel width is the dimension W of the transistor in the direction where the cross-sectional configuration of the transistor does not change. Another common definition of the channel length is the width of the gate that overlaps the active region of the transistor between the source and drain. Another common definition of the channel width is the length of the gate overlapping the active region of the transistor between the source and drain.
FIG. 5A is a schematic circuit diagram of a transmission gate switch and of a driver and receiver to illustrate the preferred embodiment of the invention. As shown in FIG. 5A, the transmission gate 100 includes a N-channel MOS transistor 102 and a driver or gate 104 for controlling the gate of transistor 102 in response to an external signal from node C. The channel length of transistor 102 is preferably less than 1.5 microns, and in some applications preferably less than 1 micron. The channel width of transistor 102 is preferably more than 1,000 microns and in some instances preferably 1,200 microns or more. In reference to FIGS. 3 and 4, by reducing the channel length, the resistance of the resistor is reduced since current carriers have a shorter distance to travel in order to conduct current between nodes A, B. By using a transistor with large channel width compared to the transistors in the 4016 type gate, the resistance of transistor 102 is further reduced in comparison. With the above-described design for transistor 102, it is found that the inherent resistance of transmission gate switch 100 between nodes A, B when the transistor 102 is turned on, (on-resistance) can be reduced to a value of less than 50 ohms may be suitable. Applicant has discovered that in some designs, the resistance of switch 100 when transistor 102 is turned on may be reduced to a value of less than 5 ohms. Shorter channel lengths also result in reduced capacitance of transistor 102. The internal capacitance of the switch 100 and its effect on signal delay will be discussed in more detail below in reference to FIGS. 5B-5E.
FIG. 5B illustrates in more detail the structure of transmission gate switch 100 of FIG. 5A. In FIG. 5B, a partial cross-sectional view of a portion of transistor 102 is shown. Transistor 102 includes a gate 112, drain 114, source 116, and substrate 118 where the gate is separated from the drain and source and substrate by an insulating layer 120. Drain 114 is connected through a conductor 122 through a package body (not shown) of switch 100 to an input/output pin (shown symbolically) at 124. Similarly, source 116 is connected through a conductor 126 through the package body (not shown) to input/output pin 128. Pin 124 is connected to node A of FIG. 5A through trace 32 and pin 128 is connected to node B by means of another trace 32. The output of driver 104 is connected to gate 112 through node 130. The driver receives the switching signal from node C through pin 132. In reference to FIGS. 5A, 5B, the inter-lead parasitic capacitance of switch 100 would be the capacitances between the pins 124, 128, 132 and the lead-to-ground parasitic capacitances of switch 100 would be the capacitances of pins 124, 128, 132 to ground. In addition to experiencing such capacitances, a signal passing between pins 124, 128 will also experience the effects of the capacitances between gate 124 on the one hand and the drain 114 and source 116 on the other, as well as capacitances between drain 114, source 116, and substrate 118, referred to as the capacitance of the transistor. The internal capacitance of the switch 100 is given by the total capacitive effects of the capacitance of the transistor and the parasitic capacitance of the switch consisting of the inter-lead and lead-to-ground capacitances and represented by capacitor 30″ in FIG. 5A.
The most important components of the above-enumerated capacitances are the lead-to-ground capacitances and the gate to drain and source capacitances. For many commonly used packages, total capacitive effects of the inter-lead and lead-to-ground capacitances are of the order of 8 or 10 pF experienced by signals transmitted through the leads of the package. In one implementation of transistor 102, the gate to drain and source capacitances amount to about 1 or 2 pF and each of the lead-to-ground capacitances of pins 124, 128, 132 amount to about 4 pF. As indicated in the 1991 Data Book, page 5-24, by Quality Semiconductor, Inc., assignee of the present application, the on internal capacitance of a switch having characteristics similar to that of switch 100 is about 10 pF and its off capacitance is about 6 pF. Thus when transistor 102 is turned off, the internal capacitance seen at either pin 124 or 128 will be the gate to drain and source capacitance and the lead-to-ground capacitance of that particular pin. Whereas if the transistor 102 is on, the internal capacitance seen at either pin would also include the lead-to-ground capacitance of the other pin as well. For this reason, the internal capacitance of switch 100 seen at either pin 124 or 128 will be higher when the transistor is on compared to that seen when the transistor is off. Typically, substrate 118 is connected to ground and node 130 at the output of driver 104 is at a stable DC potential when the transistor is not being turned on or off.
FIG. 5C is a schematic circuit diagram illustrating one embodiment of driver 104. As shown in FIG. 5C, driver 104 is an inverter comprising a P-channel transistor 142 and an N-channel transistor 144 connected in parallel between switching pin 132 (switching pin of switch 100) and node 130. As also indicated in FIG. 5C, the two transistors are connected to a power rail VCC and ground as usual. While the driver 104 is shown as an inverter, it will be understood that other driver or gate configurations may be used, such as NOR- or NAND-gates. Since the parasitic capacitance for switch 100 may be different from those of switches 20 and 40, the capacitor in FIG. 5A is labeled 30″ to show that is may be different from those of switches 20 and 40.
FIG. 5D is a schematic view of switch 100 illustrating in more detail some of the more significant capacitances in the switch. Thus, the lead-to-ground capacitance of lead 124 is illustrated by capacitor 162 shown in phantom, and the lead-to-ground capacitance of lead 128 is illustrated by capacitor 164 shown in phantom. The gate to drain and gate to source capacitances are shown in phantom as capacitors 166, 168.
In the implementation indicated above and in the 1991 Data Book of Quality Semiconductor, Inc., the capacitance of switch 100 when the transistor is on is about 10 pF. Hence, the propagation delay caused by the resistance and internal capacitance of the switch, assuming a resistance value between pins 124 and 128 of about 5 ohms, is about 0.05 nanoseconds. If the bus capacitance is 50 pF, then the RC delay caused by the switch resistance of about 5 ohms and bus capacitance of 50 pF is about 0.25 nanoseconds, so that the total delay seen by a signal propagating through the switch to reach the receiver is about 0.3 nanoseconds, well below the 6.5 nanoseconds delay caused by the typical conventional buffer.
FIG. 5E is a conceptual circuit diagram illustrating the RC delay experienced by a signal propagating from node A to node B. Thus, in reference to FIG. 5E, the resistance of transistor 102 is Ri, the internal capacitance of the switch is Ci and the bus capacitance is Cb, where the resistor and the two capacitors are shown in phantom since they represent the respective resistance and capacitances of the switch and bus and are not real circuit elements. Then the total RC delay caused by the switch as seen by a signal propagating from node A to node B is given by Ri (C1+Cb). As long as this total delay Ri(Ci+Cb) caused by the switch 100 is less the typical delay caused by the buffer of 6.5 nanoseconds for a 74F244 buffer driving a 50 pF load, it is advantageous to replace the buffer by the switch of this invention. Thus, for any given bus capacitance Cb, Ri and Ci are chosen so that the total delay Ri (Ci+Cb) caused by the switch 100 is less the typical delay caused by the buffer.
The above-described transmission gate switch 100 may be used advantageously to replace active logic devices such as 74F244, 74F245 for switching high speed digital logic signals in a board level design. The replacement of the active device with device 100 will greatly reduce the propagation delay, logic noise (e.g., “ground bounce” noise) and power dissipation associated with the active device replaced. Please see the “Application Note AN-01” of the 1991 Data Book of Quality Semiconductor, Inc. Switch 100 is also inherently bi-directional. Other embodiments of the switch described below in reference to FIGS. 5-8 also have similar advantages.
Switch 100 may be modified by replacing transistor 102 by a P-channel transistor where the polarity of the signal for controlling the gate of the transistor has been adjusted if necessary to accommodate a P-channel device. Where the P-channel device also has the above-described channel lengths and widths, switch 100 may be constructed to have a on-resistance of not more than 10 ohms.
The gate of transistor 102 is controlled by the output of a driver 104 which may include a pair of P-channel and N-channel resistors connected in parallel between node C and the gate of transistor 102. In order to increase the speed of switching, the pair of transistors in driver 104 would preferably each have a channel length of 1.5 microns or less and channel widths greater than 200 microns. Where a driver 104 and transistor 102 are fabricated as a stand-alone integrated circuit device 100 using the same fabrication technology, the transistors in device 100 may be grown so that all the transistors in the device have short channel lengths. Where device 100 is fabricated as an integrated circuit, it can be made in the form of a package having five pins for connection to nodes A, B, C, and to power and ground.
FIG. 6 is a schematic circuit diagram of a transmission gate switch and of a driver and receiver to illustrate an alternative embodiment of the invention. As shown in FIG. 6, switch 150 includes a pair of N-channel transistor 102 and a P-channel transistor 152 connected in parallel between nodes A, B. The gate of transistor 102 is controlled by a driver 104 as in FIG. 5 and the gate of transistor 152 is controlled by the output of driver 154 whose input is connected to the output of driver 104. Where both transistors 102, 152 have the channel lengths and widths as those described above for transistor 102, the on-resistance of switch 150 would be 10 ohms or less.
FIGS. 7 and 8 are schematic circuit diagrams of two different transmission gate switches to illustrate additional alternative embodiments of the invention. Bipolar transistors typically have on-resistances of less than 10 ohms so that they may be used instead of MOS transistor 102. Such configuration is illustrated in switch 200 of FIG. 7. While a npn transistor 202 is employed in switch 200, it will be understood that a pnp type transistor may be used instead and is within the scope of the invention. As shown in FIG. 7, the base of transistor 202 is controlled by the output of a driver 204 through resistor 206. Driver 204 may be one of the 7400 TTL series of logic gates, such as the 74F04 gate.
In FIG. 8, a back to back connection of two npn transistors 202 and 252 are shown for switch 250, although 2 pnp transistors may be used instead. It is known that for a bipolar transistor, unlike a MOS transistor, the current flowing between the collector and emitter is greater in one direction than the other. By placing two transistors 202, 252 in two parallel paths and connected to nodes A, B so that each node is connected to a collector of one transistor and the emitter of the other transistor (anti-parallel arrangement), currents will flow through the path of lesser resistance in each direction so that the amount of current that needs to be pumped through the switch is reduced.
FIG. 9 is a schematic circuit diagram of a CMOS bus switch device employing the invention for switching the signals between two sets of bus lines. Quality Semiconductor, Inc. of Santa Clara, Calif., assignee of the present application, has employed the present invention for bus switches such as one shown in FIG. 9 in product 74FCT3384. As shown in FIG. 9, switch device 500 is a high speed TTL bus connect device. When enabled, the bus switch device directly connects two buses with the connection resistance of less than 5 ohms. The five lines A0, A1, A2, A3, A4 in bus A are each connected through a transistor 102 to the bus lines B0, B1, B2, B3, B4 respectively. The five transistors 102 connecting A0-A4 to B0-B4 have their gates controlled by the output of driver 104′. Similarly, the five lines A5-A9 in bus A are connected to the respective one of the five bus lines B5-B9 in bus B through transistors 102 whose gates are controlled by the outputs of a driver 104″. Thus switch device 500 includes ten switches 102 arranged as two banks of five and controlled by two different drivers. This allows switch device 500 to be used as a 10-bit switch or as a 5-bit, 2-to-1 multiplexer. This is accomplished by electrically connecting the pairs of lines B0-B5, B1-B6, B2-B7, B3-B8 and B4-B9. In such event, when the output of driver 104′ is high, the signals present on lines A0-A4 will be transmitted to the B bus whereas if the output of driver 104″ is high, the signals present on lines A5-A9 will be transmitted to the B bus instead to accomplish the 2-to-1 multiplexer function. When the output of one of the two drivers is low, the transistors driven by the driver will be turned off and the respective bus lines connected by such transistors are disconnected from one another. The above-described function is summarized in the Function Table below.
Device 500 includes in essence ten switches, where each switch includes an N-channel MOS transistor driven by a CMOS gate. When the switch is enabled, the gate of the N-channel transistor is at Vcc (+5 volts) and the device is on. These devices have an on resistance of less than 5 ohms for voltages near ground and will drive in excess of 64 mA each. The resistance rises somewhat as the I/O voltage rises from a TTL low of 0.0 volts to a TTL high of 2.4 volts. In this region the A and B pins are solidly connected, and the bus switch is specified in the same manner as a TTL device over this range. As the I/O voltage rises to approximately 4.0 volts, the transistor turns off. This corresponds to a typical TTL high of 3.5 to 4.0 volts.
FIG. 10 is a schematic circuit diagram of a CMOS bus exchange switch 600 in another product 74FCT3383. Switch 600 comprises two banks of ten switches arranged to gate through or exchange two banks of five signals. This allows switch 600 to be used as a 10-bit switch or as a 5-bit, two-way bus exchange device. Switch 600 is particularly useful for exchange and routing operations such as byte swap, crossbar matrices, and RAM sharing. The functions of switch 600 are summarized in the Table below.
The bus switch provides a path for a driving device to drive capacitance to ground and to drive capacitance up from ground. This is shown in FIGS. 11A, 11B. When the A (or B) input is driven to a TTL low of 0.0 volts, the N-channel transistor is fully on and the B (or A) output will follow it. Likewise, when the A (or B) input is driven from a TTL low of 0.0 volts to a TTL high, the capacitor side of the N-channel switch is at 0.0 volts, the switch is fully on and the B (or A) output will follow it through threshold and beyond. This means that the rise and fall time characteristics and waveforms of the B (or A) output will be determined by the TTL driver, not the bus switch. The switch introduces insignificant propagation delay.
When the bus switch is disabled, the N-channel transistor gate is at 0.0 volts, and the transistor is off. By the nature of the N-channel transistor design, the A and B pins are fully isolated when the transistor is off. Leakage and capacitance is to the chip substrate (i.e., ground) rather than between input and output. This minimizes feedthrough in the off state. Because only an N-channel transistor is used, either A or B pin(s) can be taken to Vcc and above, and the device can be powered down without loading either bus.
FIG. 12A shows bus switches (labeled 3384) 100 a, 100 b of the type in FIG. 9 used to allow the memory for a DSP slave processor 802 to be accessed by the host processor 804. Each switch may include one or more switch devices of the type similar to switch 100 of FIG. 5A; for this reason, they are labeled 100 a, 100 b. A 33 mHz TMS320C30 system is shown with a 16K×32 SRAM 806 as its program and data storage memory. The SRAM is connected to the DSP CPU by 3384 devices 100 a through bus 808. The SRAM is connected to the CPU 804 through devices 100 b and bus 810. Each of the switches 100 a, 100 b is driven by a driver (not shown) such as driver 104 of FIG. 5A.
When switches 100 a are turned on and switches 100 b are turned off, the DSP 802 is connected to SRAM 806. If it is desired for the CPU 804 to be connected to SRAM 806 instead, it is necessary to turn off switches 100 b and turn on switches 100 b. At a typical clock cycle of 30 nanoseconds for CPU and DSP operations, the turning on and off times of switches 100 a, 100 b cannot be more than several nanoseconds. Therefore, it will be desirable for drivers 104 driving transistors 102 in switches 100 a, 100 b to be such that the transistors 102 can be turned on and off within several nanoseconds. In order to turn each of the transistors 102 on or off, the gate of the transistor must be driven from logic low to logic high, or vice versa. The speed at which this will happen depends on the drive capability of drivers 104 as well as the gate to drain and source capacitances of the transistors 102.
Thus, even though mechanical relays have low on resistance, the turn on and turn off times of mechanical relays are in the millisecond range and are generally not acceptable for switching bus signals for computers or logic devices. Solid state switches constructed using MOS power transistors also have low on resistances. However, these devices have very large gate to source and drain capacitances and are generally of less than several nanoseconds. The above-described fast transmission gate switches of this invention have both low on resistance and internal capacitances as well as fast turning on and off times. Where the transistors in the drivers 104 (and of drivers 104′, 104″) have channel lengths of 1.5 microns or less and channel widths of 200 microns or more, and the gate to drain and source capacitances of transistor 102 are of the order of 1 or 2 pF, transistor 102 can be turned on or off upon the application of a switching signal to node C in a just a few nanoseconds, in any event less than 7 nanoseconds. This is comparable to the turning on and off times of standard 74F244 buffers.
As indicated above, the preferred embodiment of switches of this invention reduces the signal delay between the logic devices to less than 1 nanosecond and therefore permits full speed operation of the CPU 804 and DSP 802. This saves 10 ns over using conventional fast buffers and transceivers, i.e., 5 ns for a 244 address buffer to the SRAM and 5 ns for a 245 address transceiver from the SRAM, as shown in the timing diagrams in FIG. 12B. This allows using SRAMs with 35 ns Taa (access time) instead of 25 ns. Between calculations, the 3384 devices 100 a, 100 b disconnect the SRAM from the DSP CPU and connect it to the host CPU, allowing the host to write data in before the DSP calculation and read data out after.
While the invention is described above in reference to preferred embodiments, it will be understood that various modificaitons may be made without departing from the scope of the invention, which is limited only by the appended claims.
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|GB2260618A||Title not available|
|JP2158171A||Title not available|
|JP2196434A||Title not available|
|JP6215922A||Title not available|
|JP6230378A||Title not available|
|JP59115616A||Title not available|
|JPH0228939A||Title not available|
|JPH0290628A||Title not available|
|JPH0338839A||Title not available|
|JPH0346272A||Title not available|
|JPH0348428A||Title not available|
|JPH0572290A||Title not available|
|JPH02158171A||Title not available|
|JPH02196434A||Title not available|
|JPS6215922A||Title not available|
|JPS6230378A||Title not available|
|JPS6442863A||Title not available|
|JPS6457672A||Title not available|
|JPS59115616A||Title not available|
|SU1550617A2||Title not available|
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|50||VLSI Technology Workshop on Key Technologies for 0.5 mum Manufacturing, IC Feature Size Trend, 1991, pp. cover sheet and 62, National Semiconductor CMOS Databook cover.|
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|U.S. Classification||327/434, 327/478, 327/374, 327/482|
|International Classification||H03K17/687, H03K17/041, H03K17/693|
|Cooperative Classification||H03K17/04113, H03K17/693, H03K17/6872, H03K17/04106|
|European Classification||H03K17/693, H03K17/041B, H03K17/041D, H03K17/687B2|
|Sep 27, 2004||FPAY||Fee payment|
Year of fee payment: 4
|Sep 29, 2008||FPAY||Fee payment|
Year of fee payment: 8
|Oct 6, 2008||REMI||Maintenance fee reminder mailed|
|Nov 5, 2012||REMI||Maintenance fee reminder mailed|
|Mar 27, 2013||LAPS||Lapse for failure to pay maintenance fees|
|May 14, 2013||FP||Expired due to failure to pay maintenance fee|
Effective date: 20130327