|Publication number||US6219733 B1|
|Application number||US 09/140,372|
|Publication date||Apr 17, 2001|
|Filing date||Aug 26, 1998|
|Priority date||Aug 26, 1998|
|Publication number||09140372, 140372, US 6219733 B1, US 6219733B1, US-B1-6219733, US6219733 B1, US6219733B1|
|Inventors||William Dale Appel, Gricell Co, Franklin Mark Liu|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (9), Classifications (9), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates i n general to data processing systems, and in particular, to transmission lines within integrated circuit technologies.
The construction of a computer system has evolved to a modular architecture, where various subsystems are implemented on daughterboards, which are connected to the motherboard. The motherboard is the main circuit board containing the primary components of the computer system. This board often contains the processor, main memory, support circuitry, and a bus controller and connector. Daughterboards, including expansion memory, input/output, and multiprocessor boards, may attach to the motherboard via a plurality of bus connectors.
Considerable effort has been made to speed up the various integrated circuits, which make up a computer system. However, as integrated circuit technologies shrink and their performance increases, the printed circuit board becomes the gating and most significant single factor limiting the speeds by which signals are transmitted on the bus lines connecting the various integrated circuits. The cycle budget for a synchronous bus can be broken into three contributing factors. One, is driving and receiving integrated circuit delays with respect to the system clock. Another is the system clock skew. The third contributor is the card net delay, which is the time required to propagate signals over the transmission lines within the network of bus lines connecting the various integrated circuits. However, improvements in the card net delay have been few.
The net delay is principally dictated by the printed circuit board (“PCB”) technology, the topology of the net, and the rise and fall times of the driver circuitry. The fastest possible net is a point-to-point net. The delay of such a point-to-point net is the propagation speed of the board times the net link, plus the delay lost to a slowing of the rise and fall times due to the capacitive load introduced by the receiver. Additionally, a point-to-point solution results in the need for added buffering and additional control logic, which results in a more expensive solution. Furthermore, additional cycles are needed to implement such point-to-point nets.
Multidrop nets are more common in higher volume, lower cost systems, and are prevalent on data buses. Such nets have loads that are bidirectional. The main challenge on multidrop nets is to lay them out and route them such that the signal reflections do not significantly distort waveforms in the critical threshold regions of the receiving devices. A second challenge is arriving at a topology that optimizes all the scenarios such that delays due to reflections are minimized.
Once the integrated circuit technologies, clock distribution and mechanical requirements have been established, the card designer is left with limited possibilities in routing the net so as to not only assure that they run reliably but also optimized for speed. The normal cost of reliability of the net is additional delay.
The present invention addresses the foregoing problems by optimizing a reflection profile of a data net. A reflection profile is the addition of reflections added to the originally received waveform that produces the observed waveform shape at the receiver. The optimization of the waveform profile is the reduction or movement of reflections in order to clean up threshold regions and speed up the worst case net delay scenario. Such a scenario is the waveform profile at each receiver when one of the drivers owns the bus.
In an embodiment of the present invention, a bus cable is connected between two daughter cards (daughterboards) mounted on a system board (motherboard) so as to provide a complete loop when the integrated circuits on the daughter cards are also connected to an integrated circuit on the motherboard. An advantage of the present invention is that no modifications need to be made to the motherboard. Instead, the daughter cards are replaced with upgraded daughter cards having the connections from the integrated circuits to the connectors, which are then connected with the bus cable. This can be accomplished with a cable connected at the top of the daughter cards, thus eliminating any need to modify or replace the motherboard, which can be considerably more troublesome and expensive.
One advantage with this implementation is that the motherboard need not be replaced when the user upgrades to a system whereby multiple daughter cards are now needed. Instead, merely the daughter cards are replaced with the daughter cards modified in accordance with the present invention, which are then connected using the bus cable.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates a prior art configuration;
FIG. 2 illustrates a circuit diagram in accordance with the prior art;
FIG. 3 illustrates a circuit diagram in accordance with an embodiment of the present invention;
FIG. 4 illustrates the present invention; and
FIG. 5 illustrates a data processing system configured in accordance with the present invention.
In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits have been shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning timing considerations and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art.
Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
FIG. 1 illustrates a prior art configuration wherein system board (motherboard) 100 within a computer system (not shown) has first and second CPU connectors 106 and 104, respectively, connected by data net 107 to memory controller 105. Mounted within connector 106 is CPU card 101 having CPU1 102 and CPU2 103 connected to each other and to data net 107 through connector 106. Not shown is a second CPU card, which would be mounted within second CPU connector 104, and having a plurality of CPU chips mounted thereon and connected to data net 107.
FIG. 2 illustrates how the various components within FIG. 1 are connected. Node 1 represents CPU2 103, node 2 represents CPU1 102, and node 3 is as illustrated in FIG. 1, and represents a connection from data net 107 to both of the CPU cards through connectors 104 and 106. Node 4 represents memory controller 105, and nodes 5 and 6 represent the CPU chips mounted on the second CPU card (not shown) mounted within connector 104.
There are three major problems with this topology. These three problems occur when any one of the processors drives the bus. Problem one is when CPU2 103 drives CPU1 102 and receives a negative reflection from node 3 that occurs within the threshold region.
Some background information will now be provided. A transmission line, such as data net 107, will have a character impedance Z0 and is a function of the unit inductance and unit capacitance of the line. A reflection represents the amount of signal reflected by a discontinuity on the transmission line. Whenever a signal encounters an impedance other than Z0, part (or all) of the signal is reflected. If the impedance is greater than Z0, then the reflection will be the same phase as the original signal. If the impedance is less than Z0, the reflection will be phase-reversed. Whenever a transmission line is split into branches or trees, the branching point (which in this example is node 3) becomes a low impedance point since the Z0 of the branches are in parallel. The resultant impedance of the branch node is equal to the equivalent impedance of parallel real resistors of value Z0. Or, if a line splits into N branches, a traveling wave will experience a local impedance of Z0/N at the branch point. This is always much lower than Z0 and always produces a negative reflection. If this negative reflection is allowed to propagate unchecked, it can create slope reversals and false triggering.
A negative reflection that occurs in the threshold region can cause delays in the switching of the receiver circuits within a particular chip located on the net.
Problem two is when CPU2 103 drives and the memory controller 105 at node 4 receives. Memory controller 105 receives the initial wave and it bounces back to node 3, which bounces back a negative reflection back towards node 4. The third problem is that of delay. When CPU2 103 drives a signal, CPU1 102 must wait for the signal to travel all the way to the CPU at node 6 and back to switch completely. This amounts to almost a 2X net delay.
The first threshold reflection problem can be resolved by adding some losses in the form of resistors 202 and 203 so as to smooth the reflection and in turn clean up the signal in the threshold region. The value can be tuned according to actual hardware and simulation results. This, however, adds delay to the net 107, so it is desirable to minimize the resistor values and still maintain clean threshold regions.
Referring to FIGS. 3 and 4, the present invention utilizes a cable connector 301 on top of daughter cards 304 and 305 to interconnect the data lines across the two cards. This forms a loop with a stub between nodes 3 and 4. The stub is the part of the net 107 on the system board 100 that goes to the memory controller 105.
Problems two and three noted above are addressed with this loop implementation. First, the negative reflection seen at the memory controller 105 caused by the low impedance seen at node 3 of the net 107 is cancelled by the waveform traveling from the driving processor over the cable arriving at the same time as the reflection signal, which cancels the reflection effect.
Additionally, the processor closest to the driving processor does not have to wait for the signal to turn back from the other processor card for it to switch. It now switches when the signal travels all the way around the loop which is effectively shorter than the 2X delay provided for by the implementation shown in FIG. 2.
This loop concept can also be applied with some sort of connection directly across the two CPUs, given a left and right CPU card. This would minimize the loop length and improve the electrical performance.
As can be seen, the present invention does not result in any modifications needed to system board 100. Instead, new daughter cards 304 and 305 with their chips (e.g., chips 403 and 404) and resistor values 306 and 307 are sent to the user to replace the original cards (e.g., card 101) to be mounted in the same connectors 104 and 106. Connectors 302 and 303 at the top of the daughter cards 304 and 305, respectively, are connected to the transmission line network. Bus cable 301 is then connected across connectors 302 and 303.
Please note that the present invention is not limited to connections between CPU chips on CPU cards and a memory controller on a system board. Any circuits (i.e., drops) connected within a network can take advantage of the novelty of the present invention.
Referring next to FIG. 5, there is illustrated a block diagram of a computer system 513 that can take advantage of the implementations of the present invention. Some of the components illustrated in FIG. 5 can be located on the system board, while other components can be located on the attached daughter boards.
A representative hardware environment for practicing the present invention is depicted in FIG. 5, which illustrates a typical hardware configuration of workstation 513 in accordance with the subject invention having central processing unit (CPU) 510, such as a conventional microprocessor, and a number of other units interconnected via system bus 512. Workstation 513 includes random access memory (RAM) 514, read only memory (ROM) 516, and input/output (I/O) adapter 518 for connecting peripheral devices such as disk units 520 and tape drives 540 to bus 512, user interface adapter 522 for connecting keyboard 524, mouse 526, and/or other user interface devices such as a touch screen device (not shown) to bus 512, communication adapter 534 for connecting workstation 513 to a data processing network, and display adapter 536 for connecting bus 512 to display device 538. CPU 510 may include other circuitry not shown herein, which will include circuitry commonly found within a microprocessor, e.g., execution unit, bus interface unit, arithmetic logic unit, etc.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3751591 *||Jun 20, 1972||Aug 7, 1973||Ibm||Zero skew clock distribution system|
|US4467436||Oct 26, 1981||Aug 21, 1984||United States Robots, Inc.||Robot arm controller with common bus memory|
|US5146587 *||Dec 30, 1988||Sep 8, 1992||Pitney Bowes Inc.||System with simultaneous storage of multilingual error messages in plural loop connected processors for transmission automatic translation and message display|
|US5182798 *||Dec 30, 1988||Jan 26, 1993||Pitney Bowes Inc.||Multiple material processing system start-up|
|US5185866 *||Dec 30, 1988||Feb 9, 1993||Pitney Bowes Inc.||Dual mode communication among plurality of processors using three distinct data channels each having different function and operations|
|US5438297||Dec 30, 1992||Aug 1, 1995||Intel Corporation||Electrical trace having a closed loop configuration|
|US5450603||Dec 18, 1992||Sep 12, 1995||Xerox Corporation||SIMD architecture with transfer register or value source circuitry connected to bus|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6509811 *||Feb 28, 2001||Jan 21, 2003||International Business Machines Corporation||Method for reducing the effects of signal reflections in a data communications network|
|US6963941 *||May 31, 2000||Nov 8, 2005||Micron Technology, Inc.||High speed bus topology for expandable systems|
|US7151675||Aug 13, 2003||Dec 19, 2006||Mitsubishi Denki Kabushiki Kaisha||Printed-circuit board for high-speed communication|
|US7285975 *||Jun 16, 2004||Oct 23, 2007||Samsung Electronics Co., Ltd.||Termination providing apparatus mounted on memory module or socket and memory system using the apparatus|
|US20040257109 *||Jun 16, 2004||Dec 23, 2004||Samsung Electronics Co., Ltd.||Termination providing apparatus mounted on memory module or socket and memory system using the apparatus|
|US20050174747 *||Aug 13, 2003||Aug 11, 2005||Mitsubishi Denki Kabushiki Kaisha||Printed-circuit board for high-speed communication|
|DE10237994B4 *||Aug 14, 2002||Jun 14, 2006||Samsung Electronics Co., Ltd., Suwon||Systemplatine mit Steuereinheit und Verbindern|
|EP1458225A2 *||Dec 11, 2003||Sep 15, 2004||Mitsubishi Denki Kabushiki Kaisha||Printed-circuit board for high-speed communication|
|EP1458225A3 *||Dec 11, 2003||Oct 26, 2005||Mitsubishi Denki Kabushiki Kaisha||Printed-circuit board for high-speed communication|
|U.S. Classification||710/301, 709/232|
|International Classification||G06F13/40, H05K1/14|
|Cooperative Classification||G06F13/4072, H05K1/148, H05K1/14|
|European Classification||G06F13/40E2B, H05K1/14|
|Aug 26, 1998||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:APPEL, WILLIAM D.;CO, GRICELL;LIU, FRANKLIN M.;REEL/FRAME:009446/0607;SIGNING DATES FROM 19980820 TO 19980825
|Dec 18, 2001||CC||Certificate of correction|
|Sep 22, 2004||FPAY||Fee payment|
Year of fee payment: 4
|Oct 27, 2008||REMI||Maintenance fee reminder mailed|
|Apr 17, 2009||LAPS||Lapse for failure to pay maintenance fees|
|Jun 9, 2009||FP||Expired due to failure to pay maintenance fee|
Effective date: 20090417