|Publication number||US6221562 B1|
|Application number||US 09/192,137|
|Publication date||Apr 24, 2001|
|Filing date||Nov 13, 1998|
|Priority date||Nov 13, 1998|
|Publication number||09192137, 192137, US 6221562 B1, US 6221562B1, US-B1-6221562, US6221562 B1, US6221562B1|
|Inventors||Diane C. Boyd, Toshiharu Furukawa, Steven J. Holmes, William H. Ma, Paul A. Rabidoux, David V. Horak|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (12), Referenced by (96), Classifications (17), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
U.S. patent applications Ser. No. 08/715,287, now U.S. Pat. No. 6,114,082, entitled “Frequency Doubling Hybrid Photoresist”, filed Sep. 16, 1996, and Ser. No. 09/170,756, entitled “Optimization of Space Width for Hybrid Photoresist”, filed Oct. 13, 1998, are assigned to the same assignee hereof and contain subject matter related, in certain respect, to the subject matter of the present application. The above-identified patent applications are incorporated herein by reference.
1. Technical Field of the Invention
This invention pertains to semiconductor IC processing. In particular, this invention provides a method for achieving small line width control over semiconductor dimensions, thereby achieving greater feature density during IC manufacturing.
2. Background Art
It is an object of the present invention to convert a photoresist space pattern into a photoresist line pattern. An example of this is the use of a hybrid photoresist space image for gate conductor applications. A subtractive etch is currently used to form the gate, which requires a photoresist line rather than a photoresist space. In order to form the gate conductor from the hybrid space, the space must be converted to a line.
Previously used processes etched the photoresist space into a hard mask, then filled the hard mask with another material, such as silicon oxide. The oxide film is then polished, and the nitride hard mask stripped. The polished oxide can then be used to mask the gate conductor etch.
By means of our invention, we can take the sub-critical high-resolution space of a hybrid photoresist and turn it into a line. The line, formed in the manner of the present invention, can be used to mask a subtractive etch process on the substrate. The preferred application for this process at the present time is for conventional gate structure formation, in which a small channel length and high channel uniformity would provide a large beneficial gain.
Our solution is to apply a spun-on-glass oxide film over the photoresist. The spun-on-glass can be of the conventional spin-on type, or it can also be of the new plasma deposited type. The plasma deposition might be more reliable from the point of view of repeatability of applied thickness over time, and reduced defects due to shelf-life degradation of conventional spun-on-glass. This spun-on-glass material is desirable for this application because it fills very narrow openings well, leaving a minimal amount of material on the top of the topography. It can also be cured to a solid at relatively low temperatures of 150-170° C., which is compatible with avoiding photoresist degradation. After curing at these temperatures, the surface oxide can be etched, and the photoresist stripped, to leave an oxide line in place of the photoresist space. The oxide mask can then be used to etch the substrate, such as a gate conductor feature.
A gate structure formed in this manner is uniquely characteristic of a hybrid photoresist. It has a unique resolution and uniformity relative to conventional gate structures, since it does not have the normal image size distribution due to expose variation and mask variation present in conventional structures. It also provides unique image placement advantages, as the expose variation and mask variations typically present problems for image placement.
The present solution also eliminates an etch step, a polish step, and the nitride strip required in the hard mask process mentioned above. Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.
FIGS. 1A-D illustrate the process of the present invention.
FIG. 2 illustrates an example cross section of the desired final structure prior to conventional device processing.
The purpose of the present invention is to advantageously turn a photoresist space into a photoresist line. A preferred photoresist for use with the present invention includes IBM's hybrid photoresist, which resist is described in the filed applications identified above and incorporated herein by reference. Commonly available conventional photoresists are also operable for the present invention, and the methods for their use are described below in the section entitled “Conventional Photoresist”. This section will focus on the present inventive method implementing the preferred hybrid photoresist.
With a hybrid photoresist, which prints two spaces in photoresist for each reticle feature, one at each edge of the reticle opening, rather than one space for each reticle feature, the space can be printed at a fraction of the size that can normally be printed with conventional positive or negative tone photoresists. In the example of FIG. 1A, the dimension 107 can be effectively formed using hybrid photoresist at about 0.06 to 0.16 microns (drawings are not to scale). One of the desirable aspects of this hybrid photoresist process is that the width of the high resolution photoresist space is largely independent of expose dose and reticle width (since the hybrid prints the edge of the aerial image as a space, and the edge does not change substantially as expose dose or reticle size are altered, within appropriate limits), which also leads to improved uniformity of feature dimensions. The high resolution feature of the hybrid photoresist cannot generally be printed as a line. By means of our invention, we can take the sub-critical high-resolution space of a hybrid photoresist and turn it into a line. The line, formed in the manner of the present invention, can be used to mask a subtractive etch process on the substrate. The preferred application for this process at the present time is for conventional gate structure formation, in which a small channel length and high channel uniformity would provide a large beneficial gain. However, the present invention could be applied to any device features.
FIGS. 1A-D show an example method of implementing the present invention. FIG. 1A shows a patterned layer of photoresist 102, which can be applied to a substrate layer 101 (formed on a gate dielectric layer 106) by spinning the substrate at several thousand RPM depending on photoresist viscosity, to a depth approximately from about 0.3 to 0.6 microns, as a typical example. The method of depositing the photoresist is not crucial to the invention, hence, other photoresist techniques such as dry film deposition can be used. The desired feature dimension 107 (and/or 108) has been established as a space, using common techniques, which will be converted into a line.
After the photoresist is applied, exposed, and developed, to the achieve the pattern of FIG. 1A, it may be hardened and stabilized via various techniques, such as baking or UV exposure, but this hardening step is not required to implement the present invention. Referring to FIG. 1B, glass 103 is applied next via a similar processes as the photoresist. Typical spun-on glass material include various low molecular weight materials containing polymer, silicon, oxygen, and hydrocarbon species. Typically, the SOG is applied as an aqueous solvent, but can be alcohol solvent based. The glass layer is applied by spinning, then it is baked (typical temperature about 150° C. or so) for cross-linking and stabilizing the SOG and, at the same time, avoiding decomposition of the photoresist (which would begin at about 200° C. or higher).
In a deposition process, the silicon dioxide is formed from methylsilane and hydrogen peroxide. This is a well known process described and sold by Trikon Technologies, Inc., Lindenhurst, N.Y.; Arlington, Tex.; and Santa Clara, Calif.. This deposition actually occurs at very low temperatures, 0° C. After deposition, the film is cured by heating at 100-150° C. This type of temperature range is compatible with photoresist (provided the photoresist has been UV hardened). For some photoresists, a 150° C. bake is not a problem, such as for the negative tone pattern we describe in conjunction with the phase edge expose (under “Conventional Photoresist”). For other photoresists, a hardening step needs to be included, which can include a high energy, blanket UV expose in combination with a bake, usually ramped from 100° C. to 200° C. The Trikon material is desirable because it fills spaces very well, leaving very little material on top of the photoresist. An acceptable process would fill features spaces without voids and leave a substantially planar top surface. Hence, a spun-on-glass technique is preferred. SOG fills narrow openings very well due to its advantageous viscosity, leaves a minimal amount of material on top of the previously applied photoresist, is compatible with resist processes, bakes at low temperatures, and doesn't attack resist materials. The depth of SOG over the photoresist areas must be less than the depth of SOG in the spaces so that when SOG is etched the photoresist areas are exposed and SOG remains in the spaces. If the spaces become too large the thickness of SOG in the center of the spaces might become shallow enough such that a subsequent SOG etch will expose the substrate layer underneath.
Referring to FIG. 1C, etching 104 the SOG leaves exposed photoresist features while leaving SOG in the spaces between photoresist. Usable etching processes include plasma RIE and chlorine or fluorine etchants. A timed etching step here, or an end point detect scheme would achieve sufficiently good results. The SOG etch step is complete when the SOG is cleared from the tops of the photoresist regions. Sputtering effects of a plasma etch may tend to round newly exposed corners of the photoresist as the SOG layer becomes recessed below the top of the photoresist layer (not shown). Etch processes consistent with oxide etching would also be sufficient for this SOG etching step. Further etching parameters are typically described and included with commonly available etching tools. An end point detect scheme might detect changes in the presence of carbon gases, or fluorine or chlorine content change in the plasma, for example.
Referring to FIG. 1D, the photoresist is stripped using conventional photoresist strip processes leaving the patterned SOG on the surface of the substrate layer which will serve as a substrate etch mask. Off the shelf standard oxygen plasma strip, or ozone strip photoresist tools would be useful for this step. Standard, commonly available strip tools maintain correct process temperatures and include end point detection features. Thus, by the method described above, the photoresist spaces 107 and 108 have been converted to SOG lines 105.
Referring to FIG. 2, a substrate etchant is used having a sufficient poly/oxide etch ratio to bore into the substrate to a desired depth while leaving sufficient SOG on the substrate surface for protection in desired areas. In the present example, a directional etch is used to remove the substrate material down to the gate dielectric layer 106. Chlorinated or brominated compounds can be used to directionally etch the substrate material leaving the narrow dimensioned SOG on its surface with a corresponding narrow substrate region beneath it. After removing the narrow SOG portion on top, the narrow substrate region can be used to form a gate conductor for a transistor device.
At this point, shown in FIG. 2, using the narrow dimensioned poly 201 and/or 202 as gate regions, conventional device processing may be undertaken, such as source/drain implants, spacer formation, etc. Such conventional fabrication methods are well known and will not be described further.
An alternative operable method for carrying out the present invention includes using commonly available photoresists. The steps are similar to that of the hybrid photoresist method described above and can be followed for conventional photoresists by one skilled in the art. The image reversal process of the present invention effectively reverses the tone of the photoresist pattern, so for a conventional positive or negative photoresist, one would choose to print in the opposite tone relative to that which is desired to be etched into the substrate. If positive tone photoresist is used with 193 nm wavelength radiation, for example, and there is no available comparable negative tone photoresist, it may be necessary to use such a process to image a negative form in 193 nm. For line width control purposes, such as a gate conductor application, if only positive tone photoresist was available, you could use this method to turn it into a negative tone and get better isolated line width control. Examples of suitable photoresists include APEX, UVIIHS, and UV6 brands from Shipley Company, located in Marlborough, Mass., or IBM's UV2 photoresist. Reticle techniques such as phase-shift lithography or phase-edge expose processes can be used with negative photoresist to achieve narrowly spaced feature widths.
Following the steps as described above for the hybrid photoresist process, in the example of FIG. 1A, dimensions 107 and/or 108 are formed in conventional positive or negative tone resist. The photoresist is applied, as above, by spinning the substrate at several thousand RPM depending on photoresist viscosity, to a depth approximately from about 0.3 to 0.6 microns, as a typical example. The desired feature dimensions 107 and 108 have been established as spaces, using common expose and develop techniques, and will be converted into substrate lines.
Per FIG. 1B, glass is applied next via processes as described above. Per FIG. 1C, etching the SOG leaves exposed photoresist features while leaving SOG in the spaces between photoresist. Usable etching processes include plasma RIE and chlorine or fluorine etchants. Per FIG. 1D, the photoresist is stripped using conventional photoresist strip processes. Off the shelf standard oxygen plasma strip, or ozone strip photoresist tools would be useful for this step. Per FIG. 2, an etchant is used having a sufficient poly/oxide etch ratio to bore into the substrate to a desired depth while leaving sufficient SOG on the substrate surface for protection in desired areas. Chlorinated or brominated compounds can be used to directionally etch the substrate material leaving the narrow dimensioned SOG on its surface with a corresponding narrow substrate region beneath it. At this point, shown in FIG. 2, using the narrow dimensioned poly as a gate region, conventional processing may be undertaken.
The matter contained in the above description or shown in the accompanying drawings have been described for purposes of illustration and shall not be interpreted in a limiting sense. It will be appreciated that various modifications may be made in the above structure and method without departing from the scope of the invention described herein. Thus, changes and alternatives will now become apparent to those skilled in the art without departing from the spirit and scope of the invention as set forth in the following claims. Accordingly, the scope of protection of this invention is limited only by the following claims and their equivalents.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4774164 *||Apr 6, 1987||Sep 27, 1988||Tegal Corporation||Chrome mask etch|
|US5077236||Jul 2, 1990||Dec 31, 1991||Samsung Electronics Co., Ltd.||Method of making a pattern of tungsten interconnection|
|US5312512||Oct 23, 1992||May 17, 1994||Ncr Corporation||Global planarization using SOG and CMP|
|US5451543||Apr 25, 1994||Sep 19, 1995||Motorola, Inc.||Straight sidewall profile contact opening to underlying interconnect and method for making the same|
|US5543252||Apr 15, 1994||Aug 6, 1996||Kabushiki Kaisha Toshiba||Method for manufacturing exposure mask and the exposure mask|
|US5605783||Jan 6, 1995||Feb 25, 1997||Eastman Kodak Company||Pattern transfer techniques for fabrication of lenslet arrays for solid state imagers|
|US5618383||Mar 30, 1994||Apr 8, 1997||Texas Instruments Incorporated||Narrow lateral dimensioned microelectronic structures and method of forming the same|
|US5652182||Dec 29, 1995||Jul 29, 1997||Cypress Semiconductor Corporation||Disposable posts for self-aligned non-enclosed contacts|
|US5653851||Jul 5, 1994||Aug 5, 1997||Texas Instruments Incorporated||Method and apparatus for etching titanate with organic acid reagents|
|US6017810 *||Apr 30, 1998||Jan 25, 2000||International Business Machines Corporation||Process for fabricating field effect transistor with a self-aligned gate to device isolation|
|US6096458 *||Aug 5, 1998||Aug 1, 2000||International Business Machines Corporation||Methods for manufacturing photolithography masks utilizing interfering beams of radiation|
|JPH02214126A *||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6566280 *||Aug 26, 2002||May 20, 2003||Intel Corporation||Forming polymer features on a substrate|
|US6670106 *||Mar 6, 2001||Dec 30, 2003||Sharp Kabushiki Kaisha||Formation method of pattern|
|US6780736||Jun 20, 2003||Aug 24, 2004||International Business Machines Corporation||Method for image reversal of implant resist using a single photolithography exposure and structures formed thereby|
|US7682942 *||Sep 28, 2007||Mar 23, 2010||Sandisk 3D Llc||Method for reducing pillar structure dimensions of a semiconductor device|
|US7713818||Jun 30, 2008||May 11, 2010||Sandisk 3D, Llc||Double patterning method|
|US7759201||Jul 20, 2010||Sandisk 3D Llc||Method for fabricating pitch-doubling pillar structures|
|US7786015||Apr 28, 2008||Aug 31, 2010||Sandisk 3D Llc||Method for fabricating self-aligned complementary pillar structures and wiring|
|US7829269||Nov 9, 2010||Tokyo Electron Limited||Dual tone development with plural photo-acid generators in lithographic applications|
|US7879536 *||Dec 19, 2006||Feb 1, 2011||Korea Institute Of Machinery & Materials||Method for forming high-resolution pattern having desired thickness or high aspect ratio using dry film resist|
|US7935477 *||May 3, 2011||Taiwan Semiconductor Manufacturing Company, Ltd.||Double patterning strategy for contact hole and trench|
|US7943289||May 17, 2011||Globalfoundries Inc.||Inverse resist coating process|
|US7960090 *||Jun 14, 2011||Canon Kabushiki Kaisha||Pattern forming method, pattern formed thereby, mold, processing apparatus, and processing method|
|US7981592||Aug 6, 2008||Jul 19, 2011||Sandisk 3D Llc||Double patterning method|
|US8026178||Sep 27, 2011||Sandisk 3D Llc||Patterning method for high density pillar structures|
|US8048616||Nov 1, 2011||Taiwan Semiconductor Manufacturing Company, Ltd.||Double patterning strategy for contact hole and trench in photolithography|
|US8084186 *||Feb 10, 2009||Dec 27, 2011||Az Electronic Materials Usa Corp.||Hardmask process for forming a reverse tone image using polysilazane|
|US8129080||Sep 16, 2009||Mar 6, 2012||Tokyo Electron Limited||Variable resist protecting groups|
|US8138097||Sep 20, 2010||Mar 20, 2012||Kabushiki Kaisha Toshiba||Method for processing semiconductor structure and device based on the same|
|US8178286||Jun 8, 2011||May 15, 2012||Sandisk 3D Llc||Double patterning method|
|US8197996||Sep 16, 2009||Jun 12, 2012||Tokyo Electron Limited||Dual tone development processes|
|US8198016 *||Jun 12, 2012||Shin-Etsu Chemical Co., Ltd.||Patterning process|
|US8232198||Jul 31, 2012||International Business Machines Corporation||Self-aligned permanent on-chip interconnect structure formed by pitch splitting|
|US8241969||Aug 24, 2011||Aug 14, 2012||Sandisk 3D Llc||Patterning method for high density pillar structures|
|US8257911||Sep 4, 2012||Tokyo Electron Limited||Method of process optimization for dual tone development|
|US8329512||Dec 11, 2012||Sandisk 3D Llc||Patterning method for high density pillar structures|
|US8440569 *||Dec 7, 2007||May 14, 2013||Cadence Design Systems, Inc.||Method of eliminating a lithography operation|
|US8450052||May 28, 2013||Taiwan Semiconductor Manufacturing Company, Ltd.||Double patterning strategy for contact hole and trench in photolithography|
|US8501394||Jan 27, 2009||Aug 6, 2013||Az Electronic Materials Usa Corp.||Superfine-patterned mask, method for production thereof, and method employing the same for forming superfine-pattern|
|US8568964||Apr 27, 2009||Oct 29, 2013||Tokyo Electron Limited||Flood exposure process for dual tone development in lithographic applications|
|US8574810||Dec 11, 2009||Nov 5, 2013||Tokyo Electron Limited||Dual tone development with a photo-activated acid enhancement component in lithographic applications|
|US8758987 *||Sep 2, 2009||Jun 24, 2014||Micron Technology, Inc.||Methods of forming a reversed pattern in a substrate|
|US8795556||Apr 24, 2012||Aug 5, 2014||International Business Machines Corporation||Self-aligned permanent on-chip interconnect structure formed by pitch splitting|
|US8822137||Aug 3, 2011||Sep 2, 2014||International Business Machines Corporation||Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication|
|US8890318||Apr 15, 2011||Nov 18, 2014||International Business Machines Corporation||Middle of line structures|
|US8900988||Apr 15, 2011||Dec 2, 2014||International Business Machines Corporation||Method for forming self-aligned airgap interconnect structures|
|US9034765 *||Aug 1, 2013||May 19, 2015||Samsung Electronics Co., Ltd.||Methods of forming a semiconductor device|
|US9054160||Apr 15, 2011||Jun 9, 2015||International Business Machines Corporation||Interconnect structure and method for fabricating on-chip interconnect structures by image reversal|
|US9209039||Jun 24, 2014||Dec 8, 2015||Micron Technology, Inc.||Methods of forming a reversed pattern in a substrate, and related semiconductor device structures|
|US9209126||Sep 7, 2012||Dec 8, 2015||Globalfoundries Inc.||Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication|
|US9236298||May 20, 2015||Jan 12, 2016||Globalfoundries Inc.||Methods for fabrication interconnect structures with functional components and electrical conductive contact structures on a same level|
|US9245791||Jun 29, 2015||Jan 26, 2016||Globalfoundries Inc.||Method for fabricating a contact|
|US9299847||Jun 16, 2015||Mar 29, 2016||Globalfoundries Inc.||Printed transistor and fabrication method|
|US9343354||Aug 19, 2013||May 17, 2016||Globalfoundries Inc.||Middle of line structures and methods for fabrication|
|US20020155389 *||Oct 9, 2001||Oct 24, 2002||Bharath Rangarajan||Inverse resist coating process|
|US20040256698 *||Apr 27, 2004||Dec 23, 2004||International Business Machines Corporation||Method for image reversal of implant resist using a single photolithography exposure and structures formed thereby|
|US20040265745 *||May 6, 2004||Dec 30, 2004||Koutaro Sho||Pattern forming method|
|US20050014378 *||Jul 16, 2003||Jan 20, 2005||Goodner Michael D.||Substrate patterning integration|
|US20050164133 *||Mar 22, 2005||Jul 28, 2005||Advanced Micro Devices, Inc.||Inverse resist coating process|
|US20050214695 *||Mar 17, 2005||Sep 29, 2005||Hirokazu Kato||Pattern forming method and method for manufacturing semiconductor device|
|US20060051584 *||Apr 15, 2003||Mar 9, 2006||Florian Bieck||Process for producing a product having a structured surface|
|US20070259293 *||Dec 19, 2006||Nov 8, 2007||Korea Institute Of Machinery & Materials||Method for forming high-resolution pattern having desired thickness or high aspect ratio using dry film resist|
|US20080292976 *||May 21, 2008||Nov 27, 2008||Canon Kabushiki Kaisha||Pattern forming method, pattern formed thereby, mold, processing apparatus, and processing method|
|US20090087963 *||Sep 28, 2007||Apr 2, 2009||Sandisk Corporation||Method for reducing pillar structure dimensions of a semiconductor device|
|US20090142701 *||Nov 30, 2007||Jun 4, 2009||Taiwan Semiconductor Manufacturing Company, Ltd.||Double patterning strategy for contact hole and trench|
|US20090146322 *||Dec 7, 2007||Jun 11, 2009||Milind Weling||Method of eliminating a lithography operation|
|US20090155962 *||Dec 17, 2007||Jun 18, 2009||Sandisk 3D Llc||Method for fabricating pitch-doubling pillar structures|
|US20090233238 *||Mar 12, 2008||Sep 17, 2009||Taiwan Semiconductor Manufacturing Company, Ltd.||Double Patterning Strategy For Contact Hole and Trench in Photolithography|
|US20090246714 *||Mar 26, 2008||Oct 1, 2009||Thin Film Etching Method||Thin film etching method|
|US20090253080 *||Apr 2, 2008||Oct 8, 2009||Dammel Ralph R||Photoresist Image-Forming Process Using Double Patterning|
|US20090253081 *||Apr 2, 2008||Oct 8, 2009||David Abdallah||Process for Shrinking Dimensions Between Photoresist Pattern Comprising a Pattern Hardening Step|
|US20090258318 *||Aug 6, 2008||Oct 15, 2009||Sandisk 3D Llc||Double patterning method|
|US20090258501 *||Jun 30, 2008||Oct 15, 2009||Sandisk 3D Llc||Double patterning method|
|US20090269932 *||Oct 29, 2009||Sandisk 3D Llc||Method for fabricating self-aligned complimentary pillar structures and wiring|
|US20090286188 *||May 4, 2009||Nov 19, 2009||Shin-Etsu Chemical Co., Ltd.||Patterning process|
|US20100040838 *||Feb 18, 2010||Abdallah David J||Hardmask Process for Forming a Reverse Tone Image|
|US20100055624 *||Aug 26, 2008||Mar 4, 2010||Tokyo Electron Limited||Method of patterning a substrate using dual tone development|
|US20100055625 *||Mar 4, 2010||Tokyo Electron Limited||Method of process optimization for dual tone development|
|US20100058431 *||Mar 4, 2010||Mccorkendale Bruce||Agentless Enforcement of Application Management through Virtualized Block I/O Redirection|
|US20100075238 *||Sep 16, 2009||Mar 25, 2010||Tokyo Electron Limited||Variable Resist Protecting Groups|
|US20100119960 *||Sep 16, 2009||May 13, 2010||Tokyo Electron Limited||Dual Tone Development Processes|
|US20100183851 *||Jul 22, 2010||Yi Cao||Photoresist Image-forming Process Using Double Patterning|
|US20100203299 *||Aug 12, 2010||David Abdallah||Hardmask Process for Forming a Reverse Tone Image Using Polysilazane|
|US20100273099 *||Apr 27, 2009||Oct 28, 2010||Tokyo Electron Limited||Flood exposure process for dual tone development in lithographic applications|
|US20100273107 *||Oct 28, 2010||Tokyo Electron Limited||Dual tone development with a photo-activated acid enhancement component in lithographic applications|
|US20100273111 *||Oct 28, 2010||Tokyo Electron Limited||Dual tone development with plural photo-acid generators in lithographic applications|
|US20100308015 *||Jan 27, 2009||Dec 9, 2010||Yusuke Takano||Superfine-patterned mask, method for production thereof, and method employing the same for forming superfine-pattern|
|US20110052883 *||Sep 2, 2009||Mar 3, 2011||Micron Technology, Inc.||Methods of forming reversed patterns in a substrate and semiconductor structures formed during same|
|US20110171815 *||Jan 12, 2010||Jul 14, 2011||Sandisk 3D Llc||Patterning method for high density pillar structures|
|US20110236833 *||Sep 29, 2011||Sandisk 3D Llc||Double Patterning Method|
|US20140057440 *||Aug 1, 2013||Feb 27, 2014||Samsung Electronics Co., Ltd.||Methods of forming a semiconductor device|
|US20140353761 *||May 28, 2013||Dec 4, 2014||International Business Machines Corporation||Multi-orientation semiconductor devices employing directed self-assembly|
|CN101446760B||Oct 16, 2008||Jan 18, 2012||台湾积体电路制造股份有限公司||Double patterning strategy for contact hole and trench|
|CN101681095B||May 22, 2008||May 30, 2012||佳能株式会社||Pattern forming method|
|CN102308260B||Mar 30, 2009||Oct 23, 2013||Az电子材料美国公司||Hardmask process for forming reverse tone image using polysilazane|
|DE10222609A1 *||May 23, 2002||Nov 6, 2003||Schott Glas||Verfahren zur Herstellung strukturierter Schichten auf Substraten|
|DE10222609B4 *||May 23, 2002||Jul 10, 2008||Schott Ag||Verfahren zur Herstellung strukturierter Schichten auf Substraten und verfahrensgemäß beschichtetes Substrat|
|DE102004040798A1 *||Aug 23, 2004||Mar 9, 2006||Infineon Technologies Ag||Mask for a semiconductor structure formed by applying a moulding layer over the whole structure, structuring, applying a hard mask, planarising and removing the remaining moulded layer|
|WO2002037183A2 *||Oct 23, 2001||May 10, 2002||Advanced Micro Devices, Inc.||Inverse resist coating process|
|WO2002037183A3 *||Oct 23, 2001||Apr 17, 2003||Advanced Micro Devices Inc||Inverse resist coating process|
|WO2003086958A2 *||Apr 15, 2003||Oct 23, 2003||Schott Ag||Method for producing a product having a structured surface|
|WO2003086958A3 *||Apr 15, 2003||Feb 12, 2004||Schott Glas||Method for producing a product having a structured surface|
|WO2009045347A1 *||Sep 26, 2008||Apr 9, 2009||Sandisk 3D Llc||Method for reducing pillar structure dimensions of a semiconductor device|
|WO2009126491A1 *||Apr 1, 2009||Oct 15, 2009||Sandisk 3D Llc||Double patterning method|
|WO2010018430A1 *||Mar 30, 2009||Feb 18, 2010||Az Electronic Materials Usa Corp.||A hardmask process for forming a reverse tone image|
|WO2010092420A1 *||Mar 30, 2009||Aug 19, 2010||Az Electronic Materials Usa Corp.||A hardmask process for forming a reverse tone image using polysilazane|
|WO2013191939A1 *||Jun 10, 2013||Dec 27, 2013||3M Innovative Properties Company||Methods for patterning coatings|
|U.S. Classification||430/314, 257/E21.038, 430/323, 257/E21.027, 257/E21.314, 430/324|
|International Classification||H01L21/033, H01L21/027, G03F7/40, H01L21/3213|
|Cooperative Classification||G03F7/40, H01L21/32139, H01L21/0337, H01L21/0274|
|European Classification||H01L21/027B6B, H01L21/033F4, H01L21/3213D|
|Nov 13, 1998||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BOYD, DIANE C.;FURUKAWA, TOSHIHARU;HOLMES, STEVEN J.;ANDOTHERS;REEL/FRAME:009607/0597
Effective date: 19981113
|Sep 22, 2004||FPAY||Fee payment|
Year of fee payment: 4
|Nov 3, 2008||REMI||Maintenance fee reminder mailed|
|Apr 24, 2009||LAPS||Lapse for failure to pay maintenance fees|
|Jun 16, 2009||FP||Expired due to failure to pay maintenance fee|
Effective date: 20090424