|Publication number||US6232213 B1|
|Application number||US 08/910,500|
|Publication date||May 15, 2001|
|Filing date||Aug 4, 1997|
|Priority date||May 8, 1995|
|Also published as||US5677566, US7038315, US20010013645|
|Publication number||08910500, 910500, US 6232213 B1, US 6232213B1, US-B1-6232213, US6232213 B1, US6232213B1|
|Inventors||Jerrold L. King, Jerry M. Brooks|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Non-Patent Citations (6), Referenced by (17), Classifications (51), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of Application Ser. No. 08/436,522 filed May 8, 1995 now Pat. No. 5,677,566.
This invention relates generally to semiconductor chip packages and, more particularly, to a molded semiconductor chip package having external electrode bumps connected to discrete conductive leads that are in electrical contact with the bond pads on the chip.
In response to the demand for semiconductor chip packages having high lead counts and small footprints, ball grid array (BGA), “flip chip” and, more recently, “chip scale” packages have been developed. These packages are surface mounted to an external printed circuit board using an array of solder balls or similar electrode bumps, instead of metal leads. A BGA package utilizes a printed circuit board type substrate instead of a lead frame. In a typical BGA package, the semiconductor chip is mounted to the top surface of a substrate. The chip is wire bonded to electrical traces in the substrate. The chip is then overmolded with an encapsulating material. Solder balls are bonded to the electrical traces in the bottom surface of the substrate. The solder balls serve as the external electrodes for surface mounting on a printed circuit board.
Flip chip packages are similar to BGA packages, except that the solder balls are attached directly to the bond pads or electrical traces formed in the surface of the chip resulting in a more compact package. Due to the absence of an encapsulating material, flip chip packages are quite fragile and require careful assembly and handling techniques. Chip scale packages are being developed to combine the durability of the BGA packages and the small size of the flip chip packages. In a chip scale package, solder balls are attached to electrical traces in the surface of the chip or directly to the bond pads through openings in the encapsulating material. The electrical traces connect the solder balls, which form external electrodes bumps, to the bond pads in the chip. The chip scale package need only be slightly larger then the bare chip because the electrode bumps are formed on the surface of the chip.
It is desirable that the new smaller semiconductor chip packages be adapted for use in standard formats developed for larger chips. However, for both the flip chip and chip scale packages, in which the electrode bumps are attached directly to contacts on the surface of the chip, the electrode bump array must be reconfigured each time the chip is made smaller. Hence, the corresponding contacts on the printed circuit board to which the package is ultimately assembled (the chip “footprint”), must also be reconfigured. In addition, there remains a need for a semiconductor chip package that combines the small size of chip scale packages with the durability and economies of conventional lead frame assemblies and encapsulating techniques currently used to form molded plastic packages.
It is one object of the present invention to combine the small size of chip scale type packages with the durability and economies of conventional lead frame assemblies and encapsulating techniques.
It is another object of the invention to utilize an array of bump electrodes configured independent of the size of the semiconductor chip so that the package is compatible for use with standard formats developed for larger chips.
These and other objects and advantages are achieved by a semiconductor chip package that includes discrete conductive leads in electrical contact with bond pads on a semiconductor chip. This chip assembly is encapsulated within an encapsulating material such as a thermosetting epoxy resin. Electrode bumps are formed through openings in the encapsulating material to contact the conductive leads. The electrode bumps protrude from the encapsulating material for connection to an external circuit.
In one preferred embodiment of the invention, the package comprises a semiconductor chip having bond pads disposed thereon, the bond pads being accessible from an upper surface of the chip. Conductive leads, which extend over and are attached to the upper surface of the chip, are electrically connected to the bond pads. An encapsulating material covers at least a portion of the upper surface of the chip, the bond pads, and the leads. If desired, the entire assembly may be fully encapsulated. Alternatively, the conductive leads may extend out from the encapsulating material. Openings are formed in the encapsulating material to expose portions of the leads. Electrodes are formed through the openings in the encapsulating material and bonded to the exposed portions of the leads. These electrodes, typically solder balls, can then be surface mounted to a printed circuit board in the same way BGA and chip scale packages are mounted.
The conductive leads may be part of a conventional lead frame and the assembly encapsulated using equipment and techniques currently used to form molded plastic packages. The ends of the leads may extend out of the encapsulating material with or without forming to facilitate testing and burn-in. After testing, the leads may be severed flush with the encapsulating material or left extending from the package. Alternatively, the leads may be severed prior to encapsulation and the assembly fully encapsulated.
As noted, the semiconductor chip package of the present invention can be assembled using conventional molded plastic packaging techniques, equipment and materials. Further, because the electrode bumps are not connected directly to the bond pads or electrical traces in the semiconductor chip, the size of the package and the configuration of the electrode bump array can remain the same even as the chip is made smaller, thus allowing the package to be constructed to a standard format.
FIG. 1 is a cross section view of one embodiment of the invention wherein the encapsulating material covers the upper surface of the semiconductor chip and the conductive leads are positioned over the chip and extend outside the encapsulating material.
FIG. 2 is a cross section view of a second embodiment of the invention wherein the semiconductor chip is fully encapsulated and the conductive leads are positioned over the chip and severed flush with the edge of the encapsulating material.
FIG. 3 is a cross section view of a third embodiment of the invention wherein the semiconductor chip and conductive leads are fully encapsulated.
FIG. 4 is a perspective view of the embodiment of FIG. 1 wherein part of the encapsulating material has been cut away to show the upper surface of the semiconductor chip, the conductive leads and the solder balls.
FIG. 5 is a cross section view of a fourth embodiment of the invention wherein the conductive leads are positioned adjacent to the semiconductor chip.
FIGS. 6-8 are cross section views of the embodiment of FIG. 1 at various stages of fabrication.
The figures are not meant to be actual views of the various embodiments, but merely idealized representations used to depict the structure and manufacture of the invention.
FIG. 1 is a cross section view of a semiconductor chip package 10 constructed according to one of the preferred embodiments of the invention. FIG. 4 is a perspective view of the chip package of FIG. 1 wherein part of the encapsulating material has been removed. Referring to FIGS. 1 and 4, conductive leads 12, which comprise the inner portion of a conventional lead frame (not shown), are attached to a semiconductor chip 14 by a layer of adhesive material 16. Bond pads 18 are aligned along the central portion 20 of semiconductor chip 14. Bond pads 18 represent any of the various terminals commonly formed near the surface of a semiconductor chip through which electrical connections are made between active devices in the chip and external circuits.
The configuration of the chip package illustrated in FIGS. 1 and 4 is commonly referred to as a “lead over chip” (LOC) package because the conductive leads 12 extend over the semiconductor chip 14 and are bonded to the centrally located bond pads 18. Bond wires 22 connect conductive leads 12 to bond pads 18. The semiconductor chip assembly, which includes chip 14, bond pads 18 and inner end 13 of conductive leads 12, is encapsulated within an encapsulating material 26. External electrodes 28 are connected to conductive leads 12 through openings 30 formed in encapsulating material 26. External electrodes 28 may be positioned at desired locations along conductive leads 12. The conductive leads 12 are typically plated with a thin layer of metal suitable for wire bonding, such as gold, silver or palladium/nickel, at wire bond area 32 to improve the strength and conductivity of the bond between conductive leads 12 and bond wires 22. Similarly, conductive leads 12 may be plated with a thin layer of metal suitable for the solder connection, usually gold, palladium/nickel, or tin, at electrode bond area 34 to improve the strength and conductivity of the bond between conductive leads 12 and external electrodes 28. In this embodiment, the outer end 15 of conductive leads 12 extends out from the encapsulating material to facilitate chip testing using equipment and techniques presently used to test conventional external lead plastic packages. The external leads may be sheared after testing to provide a more compact package as shown in FIG. 2.
In an alternative embodiment of the invention, shown in FIG. 2, the semiconductor chip 14 is fully encapsulated and the conductive leads sheared flush with the encapsulated material. This embodiment utilizes the same components as the preferred embodiment and results in a stronger but thicker package. In a third embodiment, illustrated in FIG. 3, the ends of the conductive leads 12 that would otherwise extend outside the encapsulating material are sheared prior to encapsulation so that the entire assembly is encapsulated.
The invention may also be incorporated into a chip package wherein the bond pads are located along the periphery of the chip and wire bonded to adjacent leads. Referring to FIG. 5, semiconductor chip 14 is mounted on leadframe die paddle 40. Conductive leads 12 are wire bonded to bond pads 18 which are located along the periphery of chip 14. External electrodes 28 are connected to conductive leads 12 through openings 30 formed in encapsulating material 26.
The semiconductor chip package of the present invention can be formed using conventional molded plastic package lead frame assemblies and packaging processes and equipment. The invention is also advantageous over BGA and chip scale type packages because the electrode array can be configured and the package sized independent of the size of the semiconductor chip. The electrodes are connected to the conductive leads, not directly to the bond pads or wiring traces in the semiconductor chip as in known packages. Thus, the configuration of the electrodes as well as the size of the package can remain unchanged even as the chip size is reduced. Overall package dimensions can be controlled independent of chip size as necessary to accommodate standardized user requirements. Packaging equipment and processes need not be modified each time a reduction in chip size is achieved.
The fabrication of the package illustrated in FIGS. 1 and 4 will now be described with reference to FIGS. 6-8. Referring to FIG. 6, semiconductor chip 14, which can be any integrated circuit device, is attached to conductive leads 12. The active devices (not shown) within the chip are connected to centrally located bond pads 18. Generally, bond pads 18 are exposed through apertures in an insulating or passivation layer which forms the top surface of the chip. Conductive leads 12, which comprise the inner portion of a conventional lead frame (not shown), are positioned over the chip and extend to near the bond pads 18. Conductive leads 12 are attached the upper surface 17 of chip 14 by an adhesive layer 16 using conventional processes known in the art. For example, one known process for attaching a semiconductor chip to LOC leads is disclosed in U.S. Pat. No. 5,286,679, issued to Farnworth et al. on Feb. 15, 1994, incorporated herein by reference. Conductive leads 12 are usually prefabricated with plating of a thin layer of suitable metal at wire and electrode bond areas 32 and 34. Alternatively, conductive leads 12 may be plated after encapsulation and deflash (discussed below). Bond wires 22 are bonded to the bond pads 18 and the wire bond area 32 of the conductive leads 12 in a conventional manner well known in the art.
Referring to FIG. 7, the assembly is encapsulated within an encapsulating material 26, typically a thermosetting epoxy resin, in a conventional manner. The encapsulating material 26 is formed with openings 30 to expose conductive leads 12 at electrode bond area 34. Openings 30 are sized and shaped according to the size and shape of solder balls 38, which form the external electrodes. Openings 30 are shown hemispherically shaped to correspond to a spherical solder ball. It is to be understood, however, that openings 30 could be any size and shape that corresponds to the desired size and shape of the external electrode. Any resin residue that is present on the electrode bond area after encapsulation is removed by electrolytic or mechanical deflash processes well known in the art.
Referring to FIG. 8, solder balls 38 are bonded to electrode bond area 34 of conductive leads 12, which are exposed through openings 30. The solder balls may be attached, as is known in the art, by coating the solder balls or bond areas with flux, placing the balls on the electrode bond area 34 through opening 30 with conventional pick and place or shaker/hopper equipment, and reflowing the balls in place using an infrared or hot air reflow process. The excess flux is then removed with an appropriate cleaning agent. In this way, the solder balls are electrically and mechanically connected to the conductive leads to form the external electrodes. Other processes may also be used to form the external electrodes. For example, the electrodes may be “plated up” using conventional plating techniques rather than formed using solder balls as described above. The completed semiconductor chip package can then be assembled to a printed circuit board or the like using conventional surface mount processes and equipment.
There has been shown and described a novel semiconductor chip package that can be made only slightly larger than the chip using conventional leaded chip packaging processes and equipment and in which the array of bump electrodes can be sized and configured independent of the size of the chip. The particular embodiments shown in the drawings and described herein are for purposes of example and should not be construed to limit the invention as set forth in the appended claims. Those skilled in the art may now make numerous uses and modifications of the specific embodiments described without departing from the scope of the invention. The process steps described may in some instances be performed in a different order and/or equivalent structures and processes may be substituted for the various structures and processes described.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5136366||Nov 5, 1990||Aug 4, 1992||Motorola, Inc.||Overmolded semiconductor package with anchoring means|
|US5139969 *||Jul 1, 1991||Aug 18, 1992||Mitsubishi Denki Kabushiki Kaisha||Method of making resin molded semiconductor device|
|US5239198||Jul 2, 1992||Aug 24, 1993||Motorola, Inc.||Overmolded semiconductor device having solder ball and edge lead connective structure|
|US5289346||Feb 16, 1993||Feb 22, 1994||Microelectronics And Computer Technology Corporation||Peripheral to area adapter with protective bumper for an integrated circuit chip|
|US5293072||Apr 29, 1993||Mar 8, 1994||Fujitsu Limited||Semiconductor device having spherical terminals attached to the lead frame embedded within the package body|
|US5341564||May 10, 1993||Aug 30, 1994||Unisys Corporation||Method of fabricating integrated circuit module|
|US5355283||Apr 14, 1993||Oct 11, 1994||Amkor Electronics, Inc.||Ball grid array with via interconnection|
|US5362679||Jul 26, 1993||Nov 8, 1994||Vlsi Packaging Corporation||Plastic package with solder grid array|
|US5397921||Sep 3, 1993||Mar 14, 1995||Advanced Semiconductor Assembly Technology||Tab grid array|
|US5420460 *||Aug 5, 1993||May 30, 1995||Vlsi Technology, Inc.||Thin cavity down ball grid array package based on wirebond technology|
|US5442231||Sep 30, 1992||Aug 15, 1995||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device|
|US5442233||Dec 10, 1992||Aug 15, 1995||Hitachi, Ltd.||Packaged semiconductor device and a lead frame therefor, having a common potential lead with lead portions having dual functions of chip support and heat dissipation|
|US5519251||Oct 15, 1993||May 21, 1996||Fujitsu Limited||Semiconductor device and method of producing the same|
|US5804468 *||Nov 21, 1995||Sep 8, 1998||Fujitsu Limited||Process for manufacturing a packaged semiconductor having a divided leadframe stage|
|JPH04277636A||Title not available|
|1||"Mitsubishi Scales Down IC Packages", Electronic Engineering Times, Aug. 22, 1994, p. 13.|
|2||"Moto gets "Slice' with packaging", Feb. 28, 1994, Electronic Engineering Times, pp. ?, 100.|
|3||"Scandia Shrinks Size of BGA Packages", May 16, 1994, Electronic Engineering Times, p. 57.|
|4||"Moto gets ‘Slice’ with packaging", Feb. 28, 1994, Electronic Engineering Times, pp. ?, 100.|
|5||Shinko Technology Update, Dec. 12, 1994, p. 141.|
|6||TA 8.2: A 34 ns 256 Mb DRAM with Boosted Sense-Ground Scheme, 1994 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 140-141.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6929981||Sep 6, 2002||Aug 16, 2005||Advanpack Solutions Pte, Ltd.||Package design and method of manufacture for chip grid array|
|US6933179 *||Sep 12, 2000||Aug 23, 2005||Oki Electric Industry Co., Ltd.||Method of packaging semiconductor device|
|US7122401 *||Oct 5, 2001||Oct 17, 2006||Hyundai Electronics Industries Co., Ltd.||Area array type semiconductor package fabrication method|
|US7138298||Feb 10, 2005||Nov 21, 2006||Rohm Co., Ltd.||Semiconductor chip with external connecting terminal|
|US7227249 *||Dec 22, 2004||Jun 5, 2007||Bridge Semiconductor Corporation||Three-dimensional stacked semiconductor package with chips on opposite sides of lead|
|US7262490 *||Feb 10, 2005||Aug 28, 2007||Rohm Co., Ltd.||Semiconductor chip with external connecting terminal|
|US7339264||Feb 10, 2005||Mar 4, 2008||Rohm Co., Ltd.||Semiconductor chip with external connecting terminal|
|US7456496||May 12, 2005||Nov 25, 2008||Advanpack Solutions Pte Ltd||Package design and method of manufacture for chip grid array|
|US7781873 *||Apr 28, 2003||Aug 24, 2010||Kingston Technology Corporation||Encapsulated leadframe semiconductor package for random access memory integrated circuits|
|US20040212053 *||Apr 28, 2003||Oct 28, 2004||Koh Wei H.||Semiconductor package for random access memory integrated circuits|
|US20050146032 *||Feb 10, 2005||Jul 7, 2005||Kazutaka Shibata||Semiconductor chip with external connecting terminal|
|US20050146055 *||Feb 10, 2005||Jul 7, 2005||Kazutaka Shibata||Semiconductor device and method of producing the same|
|US20050146056 *||Feb 10, 2005||Jul 7, 2005||Kazutaka Shibata||Semiconductor chip external connecting terminal|
|US20050205987 *||May 12, 2005||Sep 22, 2005||Advanpack Solutions Pte. Ltd.||Package design and method of manufacture for chip grid array|
|US20050287716 *||Aug 31, 2005||Dec 29, 2005||Micron Technology, Inc.||Electronic device package|
|US20060012025 *||Sep 20, 2005||Jan 19, 2006||Yamaha Corporation||Semiconductor device and manufacturing method therefor|
|EP1659627A1 *||Nov 23, 2004||May 24, 2006||Optimum Care International Tech. Inc.||chip scale package|
|U.S. Classification||438/613, 257/E23.032, 257/E23.039, 438/108|
|International Classification||H01L23/31, H01L23/495|
|Cooperative Classification||H01L2924/18165, H01L2224/06136, H01L2924/14, H01L2924/01033, H01L2224/0401, H01L2924/15311, H01L2224/48091, H01L23/49517, H01L24/48, H01L2224/48247, H01L2224/05655, H01L2224/05639, H01L2224/73215, H01L2224/85439, H01L2924/00014, H01L2224/05155, H01L2924/01046, H01L2224/05644, H01L2924/01079, H01L2924/01082, H01L2224/85444, H01L2924/01028, H01L2924/0105, H01L23/4952, H01L23/4951, H01L2224/85399, H01L2924/01005, H01L2924/01006, H01L2224/85464, H01L2924/01078, H01L2924/01047, H01L2924/014, H01L23/3114, H01L2224/48465, H01L2924/01013, H01L2224/48227, H01L2224/32225, H01L2224/4824, H01L2224/05664, H01L2224/4826|
|European Classification||H01L24/48, H01L23/495C2, H01L23/31H1, H01L23/495C, H01L23/495A4|
|Sep 22, 2004||FPAY||Fee payment|
Year of fee payment: 4
|Oct 17, 2008||FPAY||Fee payment|
Year of fee payment: 8
|Dec 16, 2011||AS||Assignment|
Owner name: NANYA, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON;REEL/FRAME:027396/0123
Effective date: 20111214
|Oct 2, 2012||FPAY||Fee payment|
Year of fee payment: 12