|Publication number||US6239367 B1|
|Application number||US 09/241,340|
|Publication date||May 29, 2001|
|Filing date||Feb 1, 1999|
|Priority date||Jan 29, 1999|
|Publication number||09241340, 241340, US 6239367 B1, US 6239367B1, US-B1-6239367, US6239367 B1, US6239367B1|
|Inventors||Min-Chih Hsuan, Cheng-Te Lin|
|Original Assignee||United Microelectronics Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (91), Classifications (31), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The invention relates to a semiconductor packaging structure, and more particularly, to a multi-chip chip scale package (CSP).
2. Description of the Related Art
As the technology of semiconductor fabrication grows more and more advanced, the relevant techniques have to be further developed to coordinate the requirements of the semiconductor devices. The fabrication process of a semiconductor device typically includes three stages. In the first stage, an epitaxy technique is used for the formation of a semiconductor substrate. Semiconductor devices such as metal-oxide semiconductor (MOS) and multilevel interconnection are fabricated on the substrate in the second stage. The third stage is the packaging process. It is now a leading trend for fabricating a device or an electronic product with a thin, light, and small dimension, that is, with a higher integration for semiconductor devices. In terms of packages, many techniques such as chip scale package, multi-chip module (MCM) have been developed to obtain a high integration. The development of the fabrication technique with a line width of 0.18 μm has evoked a great interest and intensive research to further decrease the package volume. It is thus one of the very important package techniques to arrange more than one chip into a single package. In a multi-chip package, chips of processor, memory, including dynamic random access memory (DRAM) and flash memory, and logic circuit can be packed together in a single package to reduce the fabrication cost and the packaging volume. Furthermore, the signal transmission path is shortened to enhance the efficiency. The multi-chip IC packaging technology may also be applied to a multi-chip system with variable functions and operation frequencies, for example,
1. A system comprises memory chips, microprocessors, resistors, capacitors, and inductors.
2. A system comprises memory chips (DRAM), logic circuit chips, and memory chips (Flash memory),
3. A system comprises analog chips, logic circuit chips, memory chips (including DRAM, SRAM, Flash memory), resistor, capacitor, and inductor.
In FIG. 1, a conventional multi-chip module is shown. A multi-level printed circuit board (PCB) is typically applied as a substrate of the to the carrier of a multi-chip module. More than one chip 12 are adhered on the substrate 10 by insulation glue 14. The bonding pads on the chip 12 are electrically connected with the terminals on the substrate 10 by conductive wires 16. In addition to wire bonding, the connection between the chip 12 and the substrate 10 can also be established by flip chip or controlled collapse chip connection (C4) with the formation of a bump. A resin 18 is used to seal the chip 12, and the electrical connection between the whole package and a printed circuit board can be achieved by ball grid array (BGA) which use solder balls 20 to connect the terminals on the printed circuit board. The drawback of this conventional multi-chip module is that a large surface is occupied since chips are packaged on the same side of a surface. Therefore the surface are of the package is large, and the signal path between chips is long. In addition, though the volume of the package can be reduced by using flip chip technique to achieve the connection between the chip and the carrier, a known good die (KGD) method has to be used for testing. A low yield and a high cost are thus resulted.
To further shrink the volume of a package, a face to face multi-chip package is disclosed in U.S. Pat. No. 5,331,235. In FIG. 2, this multi-chip package comprises two chips 30 and 32 disposed face to face by way of tape automatic bonding (TAB). FIG. 2 illustrates inner lead bonding (ILB), whereby two chips 30, 32 having bumps 34, 36 are electrically connected to the film carrier 38. FIG. 2 further illustrates outer lead bonding (OLB), whereby the chips 30, 32 are connected to a lead frame 40. A solder ball 42 is formed between the chips 30, 32. The chips 30, 32, the film carrier 38 and the lead frame 40 are then molded resin 44. This multi-chip package uses tape automatic bonding technique. The electrical connection between chips and printed circuit board is achieved by the installation of a lead frame or other carriers. The signal transmission path is lengthened. In addition, a large thickness and surface area are resulted by using the molding material (resin) of package. The applicability is reduced, and the heat dissipation is not effective. Moreover, this kind of package can not applied to high frequency products.
The invention provides a multi-chip chip scale package with a reduced thickness and surface area. More than one chip can be packaged on one carrier. The surface area is substantially the same or slightly bigger than the largest chip being packaged therein. The multi-chip chip scale package has a shortened signal transmission path to enhance the performance of the chips.
The above multi-chip chip scale package has an enhanced performance of heat dissipation. The heat dissipation can be performed by ways of metal plate or printed circuit on a printed circuit board, or alternatively, by an additional heat dissipation apparatus.
Furthermore, the test of chip package can be performed during package process without using known-good die method. Circuit components can be disposed on a carrier and packaged with the chip package to widen the field of application.
To achieve the above-mentioned objects and advantages, a multi-chip chip scale package is provided. A film carrier is used to carry multiple chips. Using flip chip technique, these chips are disposed face-to-face on two sides of the film carrier. Each of the chips has a bump connecting to the film carrier. An insulation material is filled in between the chips, while the other side of each of the chips is bared. Accordingly, the thickness of the package is reduced, and the performance of heat dissipation is enhanced. Moreover, conductive wires are formed on the film carrier to directly connect an external signal. The signal transmission path is shortened without going through an additional carrier.
While arranging the multi-chip chip scale package on a printed circuit board, the chip may have a side directly connected to a printed circuit or metal plate on the printed circuit board to provide advantageous heat dissipation. An additional heat dissipation apparatus may also be installed on a surface of the other chip in the far end of the printed circuit board. The heat dissipation effect is thus further enhanced. In addition, at least one locating hole is formed on the insulation film and filled by the insulation material, so that the chip can be connected to the film carrier more stably. Moreover, circuit components such as in inductor can be disposed on the film carrier to electrically connect the chip. Both the chips and the circuit components can be packaged on the same film carrier. Therefore, the field of application of this package is widened. As a consequence, an improved packaging quality and an enhanced reliability are obtained.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
FIG. 1 shows a conventional multi-chip module package;
FIG. 2 is a cross sectional view showing a conventional face-to-face multi-chip module package;
FIG. 3 is a cross sectional view showing a multi-chip chip scale package in a preferred embodiment according to the invention;
FIG. 4 shows a film carrier used in a preferred embodiment according to the invention; and
FIG. 5 is a cross sectional view of applying a multi-chip chip scale package in the invention to a printed circuit board.
During the process of packages, several stages are typically included:
1) Selection of carriers: types of chips have to be selected according to specific requirement, for example, lead frame, film carrier, or printed circuit board. The film carriers are commonly used for the technique of tape automatic bonding (TAB);
2) Electrical connections between chips and carriers: currently, techniques such as wire bonding, film automatic bonding, and flip chip or controlled collapse chip connection (C4) have been developed and widely used; and
3) Package and device sealing: chips and carriers are covered or sealed by resin, ceramic or other packaging material to protect the devices on the chips and the connections between the chips and the carriers.
In FIG. 3, a cross sectional view of a multi-chip chip-scale package is shown. In the invention, multiple chips 50, 52, 54 and 56 with various sizes are packed into one package with a size substantially the same as the total volume of these chips 50 to 56. Chips 50 to 56 may include DRAM, ROM, LOGIC or ANALOG circuits, or other devices. Regarding to the selection of carrier, a film carrier 58 is chosen in this embodiment. As shown in the figure, the film carrier 58 comprises an insulation film 60 and conductive wires 62 on the insulation film 60. Since the conductive wires 62 of film carrier 58 have a thinner and narrower dimension compared to conductive wires used in other kinds of carriers, this kind of package can be applied in high frequency device.
The technique of flip chip (or C4) is applied to achieve electrical connection between the chip 50 to 56 and the film carrier 58. By the flip chip technique used in the invention, the thickness of the package can be reduced, and the signal transmission path can be shortened. The chips 50 to 56 may comprise several devices on surfaces 64, 66, 68 and 70 thereof, respectively. Bonding pads (not shown) may be formed on the surfaces 64 to 70, while bumps 72 are formed on these bonding pads. The chips 50 to 56 are disposed with face to face on opposite sides of the film carrier 58. Via the bumps 72 and the conductive wires 62, the chips 50 to 56 are electrically connected. In addition to the conductive wires 62, circuit components 74 such as a resistor, capacitor, inductor, can also be formed on the insulation film 60 and connected with the chips 50 to 66 by means of the conductive wires 62. Thus, the package is more applicable in various fields such as communication equipment, computing system, or even as a system in one.
In the part of package and device sealing, an insulation material 76 such as epoxy is used and filled between the chips 50 to 56. It is worth mentioning that the insulation material 76 is filled between the surfaces 64 to 70 of the chips 50 to 56 only to protect devices on the surfaces 64 and 70. Whereas, the other sides 78, 80, 82 and 84 of the chips 50 to 56 are exposed to reduce the package dimension and to provide a heat dissipation path.
Since the conductive wires 62 of the film carrier 58 are used to achieve signal transmission from the chips 50 to 56 and the circuit components 74 to an external device or system without an additional carrier, the signal transmission path is thus reduced. As shown in the figure, the conductive wires 62 are then bent and configured to form the curve or shape as specifically required. The forming process of the conductive wires 62 and the subsequent surface mount technique (SMT) between the conductive wires 62 and a printed circuit board are prior techniques which are not to be introduced here.
FIG. 4, is a top view of the film carrier 58 as shown in FIG. 3 before the chips 50 to 56 are disposed on the film carrier 58. The film carrier 58 comprises an insulation film 60 and conductive wires 62, for example, copper wires, arranged on the insulation film 60. Typically, film carrier 58 are in a strip shape and flexible before being packaged. In automatic production, the insulation film 60 has leading holes 86 at two ends thereof to enable the conveyance of film carrier 58. The insulation film 60 may further comprise a corner supported ring 88 with corner parts connected with the main body of the insulation film 60. The corner supported ring 88 is beset by the insulation film 60 and connected with the main body of the insulation film 60 through the corner of the corner supported ring 88. As a consequence, the conductive wires 62 can be arranged on the corner supported ring 88 to improve the stability. The corner supported ring 88 may be taped on the conductive wires 62 or be formed integrally with the insulation film 60. To enhance the fixture of the insulation material 76, locating holes 90 in a shape, for example, a cross shape, round shape, rectangular shape, or other geometric shape, are formed on the corner supported ring. A dash-line frame 92 as shown in FIG. 4 is the region where the chips 50 to 56 are disposed. After the chips 50 to 56 are disposed on the insulation film 60 and the subsequent package process is performed, the conductive wires 62 and the insulation film 60 are cut along the dash-line to form a package including chips 50 to 56 as shown in FIG. 3. In FIG. 4, while the insulation material 76 is filled between the chips 50 to 56 within a range as shown as the dash-line frame 92, the locating holes 90 (as shown in FIG. 4) are filled with the insulation 76. As a consequence, the fixture of the insulation material 76 is improved, and the fixing effect between the chips 50 to 56 and the film carrier 58 is enhanced.
Moreover, the circuit components 74 can be disposed on the film carrier 58 and connected with the chips 50 to 56 via the conductive wires 62. Thus, the package may be applied into various fields with different functions and range of frequencies. For example, the package may be applied to communication equipment, computing system, or even a system in one chip. In the example as shown in FIG. 4, the chips 50, 52, 54 are arranged abreast on the film carrier 58. It is appreciated that people skilled in the art may arrange multiple chips in various sizes on a film carrier in different allocation. The multiple chips may also be arranged on a film carrier by assembling circuit components.
FIG. 5 shows the application of a multi-chip chip scale package on a printed circuit board. A printed circuit board 100 typically comprises a substrate 102 and printed circuits 104 and 106. The substrate 102 is, for example, a multi-level printed circuit board formed by lamination. The material of the printed circuits 104 and 106 includes, for example, copper foil. In the invention, the printed circuit board 100 electrically connects with the conductive wires 62 of the film carrier 58 directly. Thus, the signal transmission path is shorter compared to the prior technique which achieve the connection between the conductive wires of the film carrier and the printed circuit board 100 by, for example, surface mount technique. In the invention, the insulation material 76 is filled in between the surfaces 64 to 70 of chips 50 to 56 to leave the surfaces 78 to 84 exposed or bared. While disposing the package of the chip 50 to 56 onto the printed circuit board 100, as shown in the figure, the bared surface 84 of the chip 56 is directly in contact with the printed circuit 106. While the printed circuit 106 is connected with the ground on the printed circuit 106 to enlarge the surface area, the heat dissipation effect is improved because of the increased surface area. In addition, a heat dissipating apparatus 108 such as a heat sink or a heat spreader may be installed over the surface 78, 80, 82 of the chips 50, 52, 54 at a far side of the printed circuit 100 to provide a heat dissipation path for the chip 50, 52, 54.
It is to be noted that using the film carrier, a test of the chip package can be performed during packaging process without employing the conventional known-good die method. Thus, the cost can be reduced.
In summary, the advantages of the invention includes at least:
1) The thickness and surface area are reduced by the application of multi-chip chip scale package. The size of the package is only slightly larger than the chip dimension.
2) The conductive wires of the film carrier directly electrically connect to the chip for signal transmission, so that the signal transmission path between the chip and the printed circuit board is shortened, the performance of the chip is thus enhanced.
3) The invention adapts the bared-chip package, so that the performance of heat dissipation is enhanced. The heat can be dissipated by ways of the printed circuit on the printed circuit board, metal plate, or additional heat dissipation apparatus.
4) The package test can be performed directly to the chip while being packaged without performing the process of known-good die.
5) The formation of locating holes improves the fixture of insulation material filled in between the chip and the film carrier, so that the chip can be disposed on the film carrier more stably.
6) circuit components can be arranged on the film carrier of the package directly. By way of the conductive wires, both the electrical connection and the signal transmission thereof can be achieved. Thus, this kind of package can be applied in various fields of invention.
Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5285352 *||Jul 15, 1992||Feb 8, 1994||Motorola, Inc.||Pad array semiconductor device with thermal conductor and process for making the same|
|US5331235 *||Apr 10, 1992||Jul 19, 1994||Goldstar Electron Co., Ltd.||Multi-chip semiconductor package|
|US5681777 *||Mar 29, 1996||Oct 28, 1997||Lsi Logic Corporation||Process for manufacturing a multi-layer tab tape semiconductor device|
|US5910685 *||Dec 3, 1997||Jun 8, 1999||Hitachi Ltd.||Semiconductor memory module having double-sided stacked memory chip layout|
|US5945741 *||Mar 5, 1997||Aug 31, 1999||Sony Corporation||Semiconductor chip housing having a reinforcing plate|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6320757 *||Jul 12, 2000||Nov 20, 2001||Advanced Semiconductor Engineering, Inc.||Electronic package|
|US6627979 *||Jun 12, 2002||Sep 30, 2003||Dongbu Electronics Co., Ltd.||Semiconductor package and fabrication method of the same|
|US6710454 *||Feb 16, 2000||Mar 23, 2004||Micron Technology, Inc.||Adhesive layer for an electronic apparatus having multiple semiconductor devices|
|US6825553||Sep 5, 2003||Nov 30, 2004||Micron Technology, Inc.||Multichip wafer level packages and computing systems incorporating same|
|US6870248 *||Jun 7, 2000||Mar 22, 2005||Rohm Co., Ltd.||Semiconductor chip with external connecting terminal|
|US6958537 *||Aug 4, 2004||Oct 25, 2005||Micron Technology, Inc.||Multiple chip semiconductor package|
|US6964881||Aug 27, 2002||Nov 15, 2005||Micron Technology, Inc.||Multi-chip wafer level system packages and methods of forming same|
|US6987031||Aug 27, 2002||Jan 17, 2006||Micron Technology, Inc.||Multiple chip semiconductor package and method of fabricating same|
|US7019410 *||Dec 21, 1999||Mar 28, 2006||Micron Technology, Inc.||Die attach material for TBGA or flexible circuitry|
|US7053414 *||Apr 12, 2004||May 30, 2006||Lite-On Technology Corporation||Optical semiconductor component to prevent electric leakage and provide different driving voltages|
|US7087992||Nov 30, 2004||Aug 8, 2006||Micron Technology, Inc.||Multichip wafer level packages and computing systems incorporating same|
|US7109063||Dec 3, 2004||Sep 19, 2006||Micron Technology, Inc.||Semiconductor substrate for build-up packages|
|US7135780||Feb 12, 2003||Nov 14, 2006||Micron Technology, Inc.||Semiconductor substrate for build-up packages|
|US7138298||Feb 10, 2005||Nov 21, 2006||Rohm Co., Ltd.||Semiconductor chip with external connecting terminal|
|US7173330||Jun 30, 2005||Feb 6, 2007||Micron Technology, Inc.||Multiple chip semiconductor package|
|US7202554 *||Aug 19, 2004||Apr 10, 2007||Amkor Technology, Inc.||Semiconductor package and its manufacturing method|
|US7205646 *||Apr 22, 2003||Apr 17, 2007||Megica Corporation||Electronic device and chip package|
|US7260284 *||Jun 13, 2005||Aug 21, 2007||Fuji Xerox Co., Ltd.||Semiconductor integrated circuit and semiconductor integrated circuit arrangement device and process|
|US7262490||Feb 10, 2005||Aug 28, 2007||Rohm Co., Ltd.||Semiconductor chip with external connecting terminal|
|US7339264||Feb 10, 2005||Mar 4, 2008||Rohm Co., Ltd.||Semiconductor chip with external connecting terminal|
|US7485562||Jan 3, 2005||Feb 3, 2009||Micron Technology, Inc.||Method of making multichip wafer level packages and computing systems incorporating same|
|US7553697||Nov 9, 2006||Jun 30, 2009||Micron Technology, Inc.||Multiple chip semiconductor package|
|US7582956 *||Mar 29, 2007||Sep 1, 2009||Fairchild Semiconductor Corporation||Flip chip in leaded molded package and method of manufacture thereof|
|US7622333 *||Aug 4, 2006||Nov 24, 2009||Stats Chippac Ltd.||Integrated circuit package system for package stacking and manufacturing method thereof|
|US7635611||Oct 3, 2006||Dec 22, 2009||Micron Technology, Inc.||Semiconductor substrate for build-up packages|
|US7645638 *||Aug 4, 2006||Jan 12, 2010||Stats Chippac Ltd.||Stackable multi-chip package system with support structure|
|US7646102||Jul 27, 2006||Jan 12, 2010||Micron Technology, Inc.||Wafer level pre-packaged flip chip systems|
|US7683467||Dec 7, 2006||Mar 23, 2010||Stats Chippac Ltd.||Integrated circuit package system employing structural support|
|US7687893||Dec 27, 2006||Mar 30, 2010||Amkor Technology, Inc.||Semiconductor package having leadframe with exposed anchor pads|
|US7687899||Aug 7, 2007||Mar 30, 2010||Amkor Technology, Inc.||Dual laminate package structure with embedded elements|
|US7692286||Aug 5, 2008||Apr 6, 2010||Amkor Technology, Inc.||Two-sided fan-out wafer escape package|
|US7714431||Nov 28, 2006||May 11, 2010||Amkor Technology, Inc.||Electronic component package comprising fan-out and fan-in traces|
|US7723210||Jun 6, 2007||May 25, 2010||Amkor Technology, Inc.||Direct-write wafer level chip scale package|
|US7723852||Jan 21, 2008||May 25, 2010||Amkor Technology, Inc.||Stacked semiconductor package and method of making same|
|US7732899||Feb 4, 2009||Jun 8, 2010||Amkor Technology, Inc.||Etch singulated semiconductor package|
|US7759783||Dec 7, 2006||Jul 20, 2010||Stats Chippac Ltd.||Integrated circuit package system employing thin profile techniques|
|US7768135||Aug 3, 2010||Amkor Technology, Inc.||Semiconductor package with fast power-up cycle and method of making same|
|US7777351||Oct 1, 2007||Aug 17, 2010||Amkor Technology, Inc.||Thin stacked interposer package|
|US7808084||May 6, 2008||Oct 5, 2010||Amkor Technology, Inc.||Semiconductor package with half-etched locking features|
|US7808112||Jul 27, 2006||Oct 5, 2010||Micron Technology, Inc.||Wafer level pre-packaged flip chip system|
|US7812447||Jul 26, 2006||Oct 12, 2010||Micron Technology, Inc.||Wafer level pre-packaged flip chip|
|US7829990||Jan 18, 2007||Nov 9, 2010||Amkor Technology, Inc.||Stackable semiconductor package including laminate interposer|
|US7847386||Nov 5, 2007||Dec 7, 2010||Amkor Technology, Inc.||Reduced size stacked semiconductor package and method of making the same|
|US7847392||Sep 30, 2008||Dec 7, 2010||Amkor Technology, Inc.||Semiconductor device including leadframe with increased I/O|
|US7872343||Feb 3, 2010||Jan 18, 2011||Amkor Technology, Inc.||Dual laminate package structure with embedded elements|
|US7875963||Nov 21, 2008||Jan 25, 2011||Amkor Technology, Inc.||Semiconductor device including leadframe having power bars and increased I/O|
|US7902660||May 24, 2006||Mar 8, 2011||Amkor Technology, Inc.||Substrate for semiconductor device and manufacturing method thereof|
|US7906855||Apr 12, 2010||Mar 15, 2011||Amkor Technology, Inc.||Stacked semiconductor package and method of making same|
|US7915738 *||Nov 9, 2009||Mar 29, 2011||Stats Chippac Ltd.||Stackable multi-chip package system with support structure|
|US7919873||Apr 5, 2011||Megica Corporation||Structure of high performance combo chip and processing method|
|US7928542||Mar 6, 2009||Apr 19, 2011||Amkor Technology, Inc.||Lead frame for semiconductor package|
|US7932595||Mar 19, 2010||Apr 26, 2011||Amkor Technology, Inc.||Electronic component package comprising fan-out traces|
|US7943422||Jul 26, 2006||May 17, 2011||Micron Technology, Inc.||Wafer level pre-packaged flip chip|
|US7956453||Jan 16, 2008||Jun 7, 2011||Amkor Technology, Inc.||Semiconductor package with patterning layer and method of making same|
|US7960212||Jun 14, 2011||Megica Corporation||Structure of high performance combo chip and processing method|
|US7960842||Nov 12, 2008||Jun 14, 2011||Megica Corporation||Structure of high performance combo chip and processing method|
|US8067272||Oct 14, 2009||Nov 29, 2011||Stats Chippac Ltd.||Integrated circuit package system for package stacking and manufacturing method thereof|
|US8084868||Jun 18, 2010||Dec 27, 2011||Amkor Technology, Inc.||Semiconductor package with fast power-up cycle and method of making same|
|US8089159||Oct 3, 2007||Jan 3, 2012||Amkor Technology, Inc.||Semiconductor package with increased I/O density and method of making the same|
|US8097952 *||Jan 26, 2010||Jan 17, 2012||Richtek Technology Corp.||Electronic package structure having conductive strip and method|
|US8119455||Mar 18, 2011||Feb 21, 2012||Amkor Technology, Inc.||Wafer level package fabrication method|
|US8124446||Aug 22, 2007||Feb 28, 2012||Megica Corporation||Structure of high performance combo chip and processing method|
|US8227921||Jul 24, 2012||Amkor Technology, Inc.||Semiconductor package with increased I/O density and method of making same|
|US8298866||Oct 30, 2012||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US8432026||Aug 4, 2006||Apr 30, 2013||Stats Chippac Ltd.||Stackable multi-chip package system|
|US8486764||Sep 26, 2012||Jul 16, 2013||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US8642383||Sep 28, 2006||Feb 4, 2014||Stats Chippac Ltd.||Dual-die package structure having dies externally and simultaneously connected via bump electrodes and bond wires|
|US8710649||Sep 5, 2013||Apr 29, 2014||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US8791501||Dec 3, 2010||Jul 29, 2014||Amkor Technology, Inc.||Integrated passive device structure and method|
|US8796561||Oct 5, 2009||Aug 5, 2014||Amkor Technology, Inc.||Fan out build up substrate stackable package and method|
|US8937381||Dec 3, 2009||Jan 20, 2015||Amkor Technology, Inc.||Thin stackable package and method|
|US8952522||Apr 29, 2014||Feb 10, 2015||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US9048298||Mar 29, 2012||Jun 2, 2015||Amkor Technology, Inc.||Backside warpage control structure and fabrication method|
|US9054117||Dec 30, 2014||Jun 9, 2015||Amkor Technology, Inc.||Wafer level package and fabrication method|
|US9082833||Jan 31, 2013||Jul 14, 2015||Amkor Technology, Inc.||Through via recessed reveal structure and method|
|US20040104486 *||Nov 26, 2003||Jun 3, 2004||Micron Technology, Inc.||Electronic apparatus having an adhesive layer from wafer level packaging|
|US20040113246 *||Nov 26, 2003||Jun 17, 2004||Micron Technology, Inc.||Method of packaging at a wafer level|
|US20040150086 *||Jan 23, 2004||Aug 5, 2004||Lee Tae Heon||Semiconductor package having reduced thickness|
|US20040157361 *||Feb 12, 2003||Aug 12, 2004||Micron Technology, Inc.||Semiconductor substrate for build-up packages|
|US20040188818 *||Mar 24, 2004||Sep 30, 2004||Advanced Semiconductor Engineering, Inc.||Multi-chips module package|
|US20040229400 *||Jun 22, 2004||Nov 18, 2004||Chua Swee Kwang||Multichip wafer level system packages and methods of forming same|
|US20050006748 *||Aug 4, 2004||Jan 13, 2005||Eng Meow Koon||Multiple chip semiconductor package|
|US20050085014 *||Dec 3, 2004||Apr 21, 2005||Micron Technology, Inc.||Semiconductor substrate for build-up packages|
|US20050116337 *||Jan 3, 2005||Jun 2, 2005||Swee Kwang Chua||Method of making multichip wafer level packages and computing systems incorporating same|
|US20050123039 *||Nov 23, 2004||Jun 9, 2005||Samsung Electronics Co., Ltd.||Motion estimation method for motion picture encoding and recording medium having program recorded thereon to implement the motion estimation method|
|US20050146032 *||Feb 10, 2005||Jul 7, 2005||Kazutaka Shibata||Semiconductor chip with external connecting terminal|
|US20050146055 *||Feb 10, 2005||Jul 7, 2005||Kazutaka Shibata||Semiconductor device and method of producing the same|
|US20050146056 *||Feb 10, 2005||Jul 7, 2005||Kazutaka Shibata||Semiconductor chip external connecting terminal|
|US20050224815 *||Apr 12, 2004||Oct 13, 2005||Hung-Yuan Su||Optical semiconductor component|
|US20050236709 *||Jun 30, 2005||Oct 27, 2005||Eng Meow K||Multiple chip semiconductor package and method of fabricating same|
|CN100429774C||Jun 15, 2002||Oct 29, 2008||东部亚南半导体株式会社||Semiconductor packaging device and its manufacturing method|
|U.S. Classification||174/528, 361/734, 361/811, 257/685, 174/533, 257/689, 257/E23.052, 361/738, 174/558, 257/723, 257/E23.055, 257/777, 174/530, 174/254|
|International Classification||H01L25/07, H01L23/495, H01L25/18, H01L25/065|
|Cooperative Classification||H01L24/48, H01L2224/16245, H01L2224/48227, H01L2224/48091, H01L2224/32225, H01L23/49572, H01L23/49575, H01L2224/73265, H01L2924/15311, H01L2924/19041, H01L2224/45147|
|European Classification||H01L23/495L, H01L23/495J|
|Feb 1, 1999||AS||Assignment|
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSUAN, MIN-CHIH;LIN, CHENG-TE;REEL/FRAME:009745/0918
Effective date: 19990118
|Nov 1, 2004||FPAY||Fee payment|
Year of fee payment: 4
|Sep 24, 2008||FPAY||Fee payment|
Year of fee payment: 8
|Oct 3, 2012||FPAY||Fee payment|
Year of fee payment: 12