|Publication number||US6246690 B1|
|Application number||US 09/044,771|
|Publication date||Jun 12, 2001|
|Filing date||Mar 19, 1998|
|Priority date||Mar 19, 1998|
|Publication number||044771, 09044771, US 6246690 B1, US 6246690B1, US-B1-6246690, US6246690 B1, US6246690B1|
|Inventors||Bruno DiPlacido, Lawrence A. Boxer|
|Original Assignee||3Com Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Referenced by (12), Classifications (5), Legal Events (9)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a flow controlled transmitting port according to Ethernet specifications in a computer network, and in particular to buffering data frames between a shared resource and a flow controlled transmitting port.
The institute of electrical and electronic engineers (IEEE) has created a Ethernet specification 802.3X dated 1998. This specification standardizes a way in which transmitting and receiving ports communicate with each other. One of the requirements of this specification is that a receiving port can flow control a corresponding transmitting port between an enabled state and a blocking state. In a particular situation where a flow controllable transmitting port is located, a plurality of transmitting ports receives data from a shared resource. This shared resource sends data frames to the individual transmitting ports. Buffers are placed between the transmitting ports and the shared resource to buffer the movement of data frames from the shared resource to the corresponding data port. When a transmitting port is in the blocked state, the buffer can overflow and no longer accept data from the shared resource.
The buffers and shared resources in many situations are designed to transfer data so reliably, that if a specific buffer becomes full, and the shared resource has a data frame to transfer to that buffer, the shared resource will stop any further operation until the specific data frame can be transferred to the specific buffer. This is a very simple and reliable design, and already exists in many applications. The creation of receive ports which can flow control corresponding transmitting ports, is a new development and can cause existing buffers to quickly overflow and stop operation of the shared resource. This is disadvantageous because the remaining transmitting ports serviced by the shared resource may be able to transmit, and have data frames waiting in the shared resource for sending to corresponding transmitting ports. However, because a single transmitting port is in the block state, and its corresponding buffer overfilled, the shared resource is no longer operating. In this way a single transmitting port in the block state can prevent or disable all other ports associated with a shared resource to stop operation.
This is quite often the case in cross point switches of an Ethernet network. The shared resource is a FIFO with associated logic that sends data frames from the FIFO to corresponding buffers and transmitting ports. The creation of flow controllable transmitting ports, while beneficial in many ways, creates a problem in that the remaining transmitting ports of a shared resource can easily be rendered useless which reduces the operation of the network.
It is a primary object of the present invention to comply with IEEE standard 802.3X of 1998, and provide transmitting ports which are flow controllable, and which will not cause existing buffers and shared resources to stop operation when a transmitting port is in the block state for an extended period of time.
The present invention accomplishes this object by providing a transmitting port with a port control logic means that monitors the data movement between the buffer and the transmiting port.
When the buffer has data for transmission, it sends a valid data signal to the transmitting port. When the transmitting port receives the valid data signal, and is able to transmit a data frame, the transmitting port sends an “unload” signal to the data buffer. The data buffer then unloads the data to the transmitting port, and the transmitting port transmits the data to the corresponding receiving port.
A flow control timer means monitors the unload and valid data signals between the buffer and the transmitting port. When the flow control timer means reads a valid data signal, but no unload signal, the flow control timing means begins measuring time. When the measured time exceeds a predetermined value, the flow control timer means generates a “discard frames” signal to the port control logic. When the port control logic receives the discard frame signal, the port control logic removes data frames from the buffer.
The data frames can be removed from the buffer by either generating the unload signal, and instead of transmitting the data frame to the receive port, the frame is just discarded. This would then restart the flow control timer and restart the measuring of time.
As an alternative, the frames could be discarded by the port control logic without resetting the timer and the measuring of time. The port control logic is then provided with means to remove the data frames without generating the unload signal, or the flow control timer does not reset when the discard claims signal is present or the transmitting port is still blocked. In this latter case there is an additional signal from the port control logic to the flow control timer indicating whether the transmitting port is in the enabled state or the blocking state. When the port control logic indicates that the port is returned to the enabled state, the flow control timer then resets and removes the discard frames signal. The predetermined time value is different depending on whether or not the timer is reset after each unload, or only reset after the transmitting port returns to the enabled state.
In this way, the present invention is able to just replace the existing transmitting ports with a flow control port and keep the rest of the system operating without having other transmitting ports be disabled due to a block transmitter overflowing its corresponding buffer and stopping operation of the shared resource. At worst, a block port will only cease operation of a shared resource for the predetermined time, and then only if the corresponding buffer overfills. The remaining circuitry of the Ethernet system, and in particular the shared resource and buffers of the corresponding switch can remain the same and do not need to be completely redesigned to operate with a flow controlled port. This allows the new IEEE 802.3X specification to be implemented quickly and inexpensively. The design and test of a new chip is therefore minimized.
The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and specific objects attained by its uses, reference is made to the accompanying drawings and descriptive matter in which a preferred embodiment of the invention is illustrated.
In the drawings:
FIG. 1 is a schematic view of a integrated circuit having several transmitting ports associated with a single shared resource;
FIG. 2 is a flow chart showing the flow controllable transmitting port, and its interaction with the buffer;
FIG. 3 is a schematic view of an Ethernet switch.
Referring to the drawings, and in particular to FIG. 1, reference numeral 1 represents an integrated circuit (IC) with a shared resource 3, buffers 5 and transmitting ports 7. The transmitting ports have port connectors 11. In the preferred embodiment the integrated circuit 1 is part of an Ethernet switch, as shown in FIG. 3, having a plurality of transmitting IC's 1 and receiving IC's 9. The transmitting and receiving IC's are connected to a crosspoint switch means 13. Data frames received by the receiving IC's 9, through their corresponding port connectors 11, are sent to the crosspoint switch 13. The crosspoint switch 13 then sends the data frame to the appropriate transmitting IC 1 where it is received by the shared resource 3. The shared resource 3 is preferably a FIFO with control logic to send the data frames to the appropriate transmitting port. Ethernet switches are well known in the art and no further explanation of them is required. The present invention is not limited to use in Ethernet switches, but instead can be used wherever a shared resource interacts with flow controlled transmitting ports.
The buffers 5 between the shared resource 3 and the transmitting ports 7 are used to compensate for possible out of synchronous movements of the data frame in the shared resource and the transmitting ports. The buffer and shared resource are preferably designed to insure that packets are not lost between the shared resource and the transmitting port. The buffer is appropriately sized for average or worst case mismatches in synchronous movements, and the shared resource will complete the sending of one data frame before sending the next data frame.
New IEEE standard 802.3x requires that transmitting ports 7 be flow controlled. This means that a receiving port can require that the corresponding transmitting port 7 stop sending data frames. The transmitting ports 7 are therefore switched between an enabled state where data frames are received from a buffer and transmitted, to a blocking state where no data frames are transmitted. With the buffers and shared resource being designed to reliably transfer packets, a significant backlog can occur where one blocked transmitting port can stop operation of a shared resource and possibly the switch means 13. It is also possible that due to this backlog and stopped operation, data frames can be lost further upstream for other transmitting ports which are in the enabled state.
As shown in FIG. 2, the flow controlled transmitting port has port control logic means 15 for transferring the data frames from the buffer to the transmitting port 7. When the buffer 5 has a data frame for transmission, a “Valid” signal is sent from the buffer to the logic means 15. When the port is enabled and ready to transmit data an “Unload” signal is sent to the buffer, and the data frame is transferred. When the port is blocked or otherwise not ready to transmit another data frame, the Unload signal is removed or absent.
In order to prevent buffers from overfilling, each flow controlled transmitting port also includes Excessive Flow Control Timer Means 17 for timing how long a data frame stays in the buffer when the port is blocked. The timer means 17 monitors the valid and unload signals, and starts measuring time when the valid signal is present and the Unload signal is not present. When the measured time is greater than a Programmed Excessive Flow Control or predetermined time value, the timer means 17 sends a Discard Frame signal to the logic means 15. The logic means then begins removing data frames from the buffer and discards the data frames. This can be done by the same unload signal and process used when the port is in the enable state, except that the data frame is not transmitted. This requires no change on the part of the buffer. Of course, other discarding devices and methods can be used.
As long as the measured time exceeds the predetermined time value, and the port is in the blocking state, the discard Frames signal is maintained and the logic means 15 continues to remove and discard data frames from the buffer. Once the port is switched to the enabled state, the timer is stopped, reset, and the Discard Frames signal removed. Operation of the buffer and transmitting port then continues with the transmitting port receiving and transmitting the data frames.
The present invention also counts the number of discarded data frames. When this number exceeds a maximum, an indication is provided to the Ethernet switch and corrective action is taken.
The timer means 17 operates by counting clock pulses or “Excessive_FC_Clk” signals from a slot timer 19. Since the slot timer 19 very often operates on a very high frequency, a divider 21 can be positioned between the slot timer 19 and the timer means 17. This divider preferably divides the signal from the slot timer by 256.
By using the flow controlled port 7 as described, transmitting IC's comply with the IEEE 802.3 standard, and shared resources and buffers can be used which simply and reliably transfer data frames from the shared resource to the buffer. The buffers are prevented from overflowing and stopping operation of the shared resource, at least for no more than the predetermined time value and then only if the buffer overflows. This prevents other ports from being disabled and prevents the loss of data frames for transmitting ports which are not blocked. The magnitude of the predetermined time value can be varied according to system parameters. One of the system parameters being the size of the buffer. If the buffer is large, the time value can be large without causes excessively long interruption of the shared resource. However the larger the buffer, the more expensive it is. Therefore the network operator is able to balance costs with the value of discarded frames and the effects of disabling other transmitting ports. The predetermined time value can be changed by the network operator if the value of discarded frames or overall network performance changes. The predetermined value can also change on a port by port basis.
The features described in specification, drawings, abstract, and claims, can be used individually and in arbitrary combinations for practicing the present invention.
While specific embodiments of the invention have been shown and described in detail to illustrate the application of the principles of the invention, it will be understood that the invention may be embodied otherwise without departing from such principles.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4897833 *||Oct 16, 1987||Jan 30, 1990||Digital Equipment Corporation||Hierarchical arbitration system|
|US4941143 *||Nov 8, 1988||Jul 10, 1990||Echelon Systems Corp.||Protocol for network having a plurality of intelligent cells|
|US5805589 *||Mar 4, 1996||Sep 8, 1998||International Business Machines Corporation||Central shared queue based time multiplexed packet switch with deadlock avoidance|
|US5822300 *||Apr 2, 1996||Oct 13, 1998||Compaq Computer Corporation||Congestion management scheme|
|US5936962 *||Jul 2, 1997||Aug 10, 1999||Extreme Networks, Inc.||Method and apparatus for predicting and controlling data transmission in a CSMA/CD LAN|
|US5936964 *||Apr 18, 1997||Aug 10, 1999||Telefonaktiebolaget Lm Ericsson||Round-trip delay optimization of multiplexed speech channels|
|US5953335 *||Dec 18, 1997||Sep 14, 1999||Advanced Micro Devices, Inc.||Method and apparatus for selectively discarding packets for blocked output queues in the network switch|
|US6021115 *||Aug 28, 1997||Feb 1, 2000||Sgs-Thomson Microelectronics Limited||ATM switch flow control|
|US6052376 *||Dec 30, 1996||Apr 18, 2000||Hyundai Electronics America||Distributed buffering system for ATM switches|
|US6072772 *||Jan 12, 1998||Jun 6, 2000||Cabletron Systems, Inc.||Method for providing bandwidth and delay guarantees in a crossbar switch with speedup|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6810042 *||Jan 4, 1999||Oct 26, 2004||Cisco Technology, Inc.||Method of queuing traffic to many destinations covering a wide range of transmission speeds while minimizing buffer size|
|US7181637||Dec 2, 2003||Feb 20, 2007||International Business Machines Corporation||Packet processing system and method for a data transfer node with time-limited packet buffering in a central queue|
|US7561590||Sep 23, 2003||Jul 14, 2009||Marvell International Ltd.||Network switch having virtual input queues for flow control|
|US7639684 *||Dec 23, 2004||Dec 29, 2009||Infineon Technologies Ag||Modified ethernet switch|
|US7688736||Sep 23, 2003||Mar 30, 2010||Marvell International Ltd||Network switch with quality of service flow control|
|US8005079||Jul 13, 2009||Aug 23, 2011||Marvell International Ltd.||Network switch having virtual input queues for flow control|
|US8218434 *||Oct 14, 2005||Jul 10, 2012||Ciena Corporation||Ethernet facility and equipment protection|
|US8638784||Aug 22, 2011||Jan 28, 2014||Marvell International Ltd.||Network switch having virtual input queues for flow control|
|US8929363||Jan 27, 2014||Jan 6, 2015||Marvell International Ltd.||Apparatus and method for allocating buffers of a memory including tracking a number of buffers used to store a received frame|
|US20060153183 *||Dec 23, 2004||Jul 13, 2006||Lim Swee H A||Modified ethernet switch|
|CN1917477B||Sep 14, 2006||Aug 11, 2010||杭州华三通信技术有限公司||Method and device of preventing interference of flow control frames|
|WO2005055530A1 *||Nov 25, 2004||Jun 16, 2005||Ibm||Packet processing system and method for a data transfer node with time-limited packet buffering in a central queue|
|U.S. Classification||370/408, 370/446|
|Jun 18, 1998||AS||Assignment|
Owner name: 3COM CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DIPLACIDO, BRUNO;BOXER, LAWRENCE A.;REEL/FRAME:009256/0277;SIGNING DATES FROM 19980319 TO 19980320
|Nov 26, 2004||FPAY||Fee payment|
Year of fee payment: 4
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Owner name: HEWLETT-PACKARD COMPANY, CALIFORNIA
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