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Publication numberUS6249055 B1
Publication typeGrant
Application numberUS 09/017,676
Publication dateJun 19, 2001
Filing dateFeb 3, 1998
Priority dateFeb 3, 1998
Fee statusPaid
Publication number017676, 09017676, US 6249055 B1, US 6249055B1, US-B1-6249055, US6249055 B1, US6249055B1
InventorsValery Dubin
Original AssigneeAdvanced Micro Devices, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Self-encapsulated copper metallization
US 6249055 B1
Abstract
Copper or copper alloy interconnection patterns are formed by a damascene technique. An aluminum or magnesium alloy is deposited in a damascene opening formed in a dielectric layer. Copper or a copper alloy is then electroplated or electroless plated on the aluminum or magnesium alloy, filling the opening. During low temperature annealing, aluminum or magnesium atoms diffuse through the copper or copper alloy layer and accumulate on its surface forming a self-encapsulated oxide to prevent corrosion and diffusion of copper atoms.
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Claims(2)
What is claimed is:
1. A semiconductor device having an interconnection pattern comprising:
a dielectric layer having an opening therein; and
a composite metal layer inlaid in the opening, the composite metal layer comprising:
a metal layer comprising a magnesium alloy lining the entire opening;
a plated layer, comprising an upper surface, comprising electroplated or electroless plated copper or a copper alloy on the metal layer filling the opening; and
a layer of magnesium oxide, formed: (a) directly on the upper surface of and encapsulating the plated layer; and (b) directly on the entire surface of the metal layer lining the opening which is between the metal layer and the dielectric layer.
2. The semiconductor device according to claim 1, wherein the metal layer comprises an alloy containing about 0.1 to about 90 atomic percent Mg.
Description
TECHNICAL FIELD

The present invention relates to electroplated or electroless plated copper or copper alloy metallization. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnect structures.

BACKGROUND ART

The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology, which is considered one of the most demanding aspects of ultra large scale integration technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnect pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.

Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed dielectric interlayers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines formed in trench openings typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.

A conductive plug filling a via hole is typically formed by depositing a dielectric interlayer on a conductive layer comprising at least one conductive pattern, forming an opening through the dielectric interlayer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric interlayer is typically removed by chemical-mechanical polishing (CMP) One such method is known as damascene and basically involves the formation of an opening which is filled in with a metal. Dual damascene techniques involve the formation of an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line. In copending application Ser. No. 08/320,516 filed on Oct. 11, 1994, prior art single and dual damascene techniques are disclosed, in addition to several improved dual damascene techniques simultaneously forming a conductive line in electrical contact with a conductive plug for greater accuracy in forming fine line patterns with minimal interwiring spacings.

High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the interconnection pattern limits the speed of the integrated circuit.

If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays approaches and even exceeds 20%.

One way to increase the control speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques wherein trenches are formed in dielectric layers and filled with a conductive material. Excess conductive material on the surface of the dielectric layer is then removed by CMP. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the sub-micron range, step coverage problems have arisen involving the use of Al which has decreased the reliability of interconnections formed between different wiring layers. Such poor step coverage results in high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with Al.

One approach to improved interconnection paths in vias comprises the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for a wiring metal and W plugs for interconnections at different levels. However, the use W is attendant with several disadvantages. For example, most W processes are complex and expensive. Moreover, W has a high resistivity. The Joule heating may enhance electromigration of adjacent Al wiring. Furthermore, W plugs are susceptible to void formation and the interface with the wiring layer usually results in high contact resistance.

Another attempted solution for the Al plug interconnect problem comprises the use of chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures for Al deposition. The use of CVD for depositing Al has proven expensive, while hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.

Copper (Cu) and Cu alloys have received considerable attention as a candidate for replacing Al in VLSI interconnect metallizations. Cu exhibits superior electromigration properties and has a lower resistivity than Al. In addition, Cu has improved electrical properties vis-á-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.

Electroless plating and electroplating of Cu and Cu alloys offer the prospect of low cost, high throughput, high quality plated films and efficient via, contact and trench filling capabilities. Electroless plating generally involves the controlled autocatalytic deposition of a continuous film on the catalytic surface by the interaction in solution of a metal salt and a chemical reducing agent. Electroplating comprises the electro deposition of an adherent metallic coating on an electrode employing externally supplied electrons to reduce metal ions in the plating solution. A seed layer is required to catalyze electroless deposition or to carry electrical current for electroplating. For electroplating, the seed layer must be continuous. For electroless plating, very thin catalytic layers, e.g., less than 100 Å, can be employed in the form of islets of catalytic metal.

There are disadvantages attendant upon the use of Cu or Cu alloys. For example, Cu is easily oxidized and vulnerable to corrosion. Unlike Al, Cu does not form a self-passivating oxide on its surface. Accordingly, corrosion of Cu is an important issue which requires resolution before Cu can be effectively utilized in many semiconductor device applications. Moreover, Cu readily diffuses through silicon dioxide, the typical dielectric interlayer material employed in the manufacture of semiconductor devices, into silicon elements and adversely affects device performance.

One approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP, as in Chow et al., U.S. Pat. No. 4,789,648. However, due to Cu diffusion through dielectric interlayer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta) , tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), and silicon nitride (Si3N4) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.

In copending application Ser. No. 08/857,129, filed May 15, 1997, now U.S. Pat. No. 5,969,422, issued Oct. 19, 1999 a method of electroless plating or electroplating copper or a copper alloy to fill high aspect ratio openings is disclosed, wherein a seed layer comprising an alloy of a refractory metal and one or more additive metals is initially deposited.

Copending application Ser. No. 08/587,264, filed Jan. 16, 1996, discloses a method of electrolessly depositing Cu in an interconnect structure, which method comprises initially depositing a barrier layer in an opening, depositing a catalytic seed layer, preferably of Cu, on the barrier layer, and then depositing a protective layer the catalytic layer encapsulating and protecting the catalytic layer from oxidation. The preferred protective material is Al which forms an Al—Cu alloy at the interface of the catalytic and protective layers, thereby encapsulating the underlying Cu. Subsequently, Cu is electrolessly deposited from an electroless deposition solution which dissolves the overlying protective alloy layer to expose the underlying catalytic Cu layer.

Al has been suggested as a doping material to improve the oxidation and corrosion resistance of Cu and act as a diffusion barrier by forming a thin protective layer of aluminum oxide on the surface of a Cu layer upon annealing. P. J. Ding et al., “Effects of the Addition of Small Amounts of Al to Copper: Corrosion, Resistivity, Adhesion, Morphology, and Diffusion”. J. Appl. Phys., 75(7) 1994, 3627-3631. Magnesium (Mg) has also been suggested as a doping material to improve the oxidation resistance of Cu.

There exists a need for semiconductor technology enabling the formation of Cu or Cu alloy metallization in interconnection patterns with improved corrosion resistance while substantially reducing or eliminating Cu diffusion.

DISCLOSURE OF THE INVENTION

An object of the present invention is a method electroplating or electroless plating Cu or Cu alloy metallization having high corrosion resistance without any substantial Cu diffusion.

Another object of the present invention is a semiconductor device comprising Cu or Cu alloy metallization exhibiting high corrosion resistance without any substantial Cu diffusion.

Additional objects, advantages and other features of the invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.

According to the present invention, the foregoing and other objects are achieved in part by a method of manufacturing a semiconductor, which method comprises: forming an opening in a dielectric layer; depositing a metal layer comprising an aluminum alloy or a magnesium alloy lining the opening; electroplating or electroless plating Cu or a Cu alloy on the metal layer to form a plated layer filling the opening; and annealing to diffuse aluminum or magnesium atoms from the metal layer through the plated layer, which Al or Mg atoms accumulate on the surface of the plated layer.

Another aspect of the present invention is a semiconductor device having an interconnection pattern comprising: a dielectric layer having an opening therein; and a composite metal layer inlaid in the opening, the composite metal layer comprising: a metal layer comprising an aluminum or a magnesium alloy lining the opening; a plated layer comprising electroplated or electroless plated copper or a copper alloy on the metal layer filling the trench; and a layer of aluminum oxide or magnesium oxide on and encapsulating the plated layer.

Additional objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the invention are described simply by way of illustrating of the best mode contemplated in carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-4 illustrate sequential phases of a method in accordance with an embodiment of the present invention.

FIGS. 5-7 illustrate sequential phases of a method in accordance with another embodiment of the present invention.

DESCRIPTION OF THE INVENTION

The present invention addresses and solves the corrosion problems attendant upon electroplated or electroless plated Cu metallization in a cost effective, simplified manner. In various embodiments of the present invention, the foregoing objective is achieved by initially depositing a metal layer comprising an Al or Mg alloy, and then electroplating or electroless plating Cu or a Cu alloy thereon. Low temperature annealing is then conducted, during which Al or Mg from the underlying Al alloy or Mg alloy layer diffuses through the plated Cu or Cu alloy, accumulating at the surface thereof, because of its (i.e., Al or Mg) low solubility in Cu, and forms a passivating or protective oxide coating on and substantially encapsulating the plated Cu or Cu alloy layer, and at the interface between the underlying Al or Mg alloy layer and a dielectric oxide layer, as well as on the underlying layer. As used throughout this application, the expression “Cu metallization” denotes electroplated or electroless plated Cu or a Cu alloy.

The particular temperature and the thickness of the underlying Al alloy or Mg alloy layer can be optimized in a particular situation. For example, it has been found that an Al alloy or Mg alloy layer having a thickness of about 50 Å to about 1500 Å is suitable in practicing the present invention. An annealing temperature of about 150° C. to 450° C. has been found effective in diffusing Mg or Al through a Cu metallization and to form an effective protective encapsulating oxide on the exposed surface of the Cu metallization, and on the exposed surface of, and at the interface between, the Al or Mg alloy layer and the dielectric oxide layer. The time of annealing can be optimized in a particular situation depending upon the dimensions of the Cu metallization, annealing temperature and particular Al or Mg alloy.

The embodiments of the present invention for producing protective oxide self-encapsulated Cu metallization are particularly applicable in conjunction with damascene techniques wherein an opening is formed in a dielectric layer, such as a silicon oxide, e.g. silicon dioxide. The present invention, however, is not limited to dielectric layers comprising silicon oxide, but can be employed in the context of various dielectric materials, such as low dielectric constant polymers.

Thus, in accordance with the present invention, Cu metallization having a protected, self-encapsulated oxide layer is formed in a damascene opening in a dielectric layer. The damascene opening can be a trench, in which case the Cu metallization forms an interconnection line, or a via/contact hole in which case the Cu metallization forms a via/contact. Double damascene techniques can be employed in which the opening contains a first portion forming a trench and a second portion forming a via/contact hole in communication with the trench, in which case the Cu metallization comprises a first section filling the trench and forming an interconnection line and a second portion filling the hole and forming a contact/via with the interconnecting line electrical connection. The present invention advantageously enables filling openings having high aspect ratios, e.g., greater than about 3:1 with improved uniformity.

Embodiments of the present invention include depositing a diffusion barrier layer prior to depositing the Al alloy or Mg alloy layer, for even greater diffusion prevention. Such a diffusion barrier layer can comprise any of a variety of metals, such as tantalum (Ta), Ta alloys, W or W alloys, and titanium (Ti) or Ti alloys. The diffusion barrier layer can be formed at a thickness of about 50 Å to about 1,500 Å. Optionally, an adhesion promoting layer can be deposited prior to depositing the diffusion barrier layer. A suitable adhesion promoting layer comprises Ti and has a thickness of about 50 Å to about 1,500 Å. The adhesion promoting layer as well as diffusion barrier layer can be deposited by any of various conventional deposition techniques, such as PVD or CVD.

In other embodiments of the present invention, a seed layer is deposited on the Al alloy or Mg alloy layer for enhanced nucleation and adhesion of the electroplated or electroless plated Cu or Cu alloy layer. The seed layer can comprise an alloy of Cu and any of various alloying elements such as Mg, Al, Zinc (Zn), Zirconium (Zr), tin (Sn), nickel (Ni), palladium (Pd), silver (Ag) or gold (Au). The seed layer can be sputter deposited or deposited by CVD.

Embodiments of the present invention include electroless plating or electroplating various Cu alloys, such as alloys of Cu with Mg, Zn, Zr, Sn, Ni, or Pd. After electroplating or electroless plating Cu or Cu alloy on the Al alloy or Mg alloy layer, CMP is typically performed to provide a planarized surface. Low temperature annealing is then conducted to diffuse Al atoms or Mg atoms from the underlying Al alloy or Mg alloy layer through the Cu metallization and accumulate on the surface thereof to form a passivating protective aluminum oxide (Al2O3) or magnesium oxide (MgO) self-encapsulating coating. Advantageously, the protective encapsulating oxide coating prevents corrosion of the Cu metallization and prevents diffusion of Cu atoms from the Cu metallization through the dielectric layer into the silicon elements. Thermal annealing can be conducted in a hydrogen atmosphere, e.g., an atmosphere containing up to 100% hydrogen, e.g., 1% hydrogen or 5% hydrogen, or an atmosphere of pure ammonia (NH3).

An embodiment of the present invention is schematically illustrated in FIGS. 1-4, wherein similar elements bear similar reference numerals. Adverting to FIG. 1, damascene openings are etched in a conventional manner in a dielectric layer 10, typically comprising silicon dioxide. The damascene openings include a trench 12 and a dual damascene opening comprising via hole 13A in communication with trench 13B. As illustrated via hole 13A communicates with an underlying interconnection line 11. However, the present invention is also applicable to a single damascene opening comprising a via hole, a single damascene opening comprising a contact hole or a dual damascene opening comprising a contact hole in communication with a trench.

With continued reference to FIG. 1, after formation of the damascene opening or openings, a layer comprising an Al alloy or a Mg alloy 14, typically containing about 0.1 to about 90 atomic percent of Al or Mg, respectively, is deposited to line the damascene openings. The Al or Mg alloys can contain such alloying elements as Cu, Ta, W, silicon (Si) or nitrogen (N) . The Al alloy or Mg alloy can be deposited by a PVD technique, such as sputtering, or a CVD technique. Typically the Al alloy or Mg alloy layer is deposited to a thickness of about 50 Å to about 1500 Å. As shown in FIG. 1, the Al alloy layer or Mg alloy layer 14 lines the damascene openings as well as the upper surface of dielectric layer 10.

Adverting to FIG. 2, a Cu or Cu alloy layer 20 is then electroplated or electroless plated on the surface of the Al or Mg alloy layer 14. Suitable Cu alloys include alloys of Cu with any of various metals, such as Mg, Sn, Zn, Pd, Au, Ag, Zr and Ni.

Subsequently, as shown in FIG. 3, CMP is performed to provide a planarized upper surface 30, Cu metallization interconnection line 31 is formed in trench 12 (FIG. 1), while a dual damascene Cu metallization structure comprising via 32A connected to interconnection line 32B is formed via hole 13A and trench 13B (FIG. 1)

Adverting to FIG. 4, subsequent to planarization, thermal annealing is conducted at a relatively low temperature of about 150° C. to 450° C., as in a hydrogen or ammonia ambient. During thermal annealing, Al atoms or Mg atoms from underlying layer 14 diffuse through the Cu metallization, accumulate on the surface thereof and oxidize to form a self-passivating, self-encapsulating oxide layer 40 on the exposed interconnection line 31 and on the exposed dual damascene structure comprising via 32A and interconnection line 32B. In addition, a self-passivating oxide layer 40 is formed on the exposed surface of, and at the interface between, underlying layer 14 and dielectric layer 10 when employing an oxide dielectric layer. The self-encapsulating oxide 40, typically has a thickness of about 20 Å to about 200 Å and prevents corrosion of the Cu metallization as well as diffusion of Cu through dielectric layer 10 to active silicon devices.

Another embodiment of the present invention is schematically illustrated in FIGS. 5-7, wherein similar elements bear similar reference numerals. The embodiment schematically illustrated in FIGS. 5-7 is similar to the embodiment schematically illustrated in FIGS. 1-4, except that an initial barrier layer 52 is deposited in the damascene openings in dielectric layer 50 formed over conductive line 51. Barrier layer 52 provides additional protection against diffusion of Cu atoms from the Cu metallization through dielectric layer 50. Suitable barrier layers can include Ti, W, Sn, Si, N, Pd, Ta, and alloys thereof. After deposition of the barrier layer 52, Al or Mg alloy layer 53 is deposited on barrier layer 52 lining the damascene openings. Cu metallization 54 is then deposited filling the damascene openings and extending above the upper surface of substrate 50.

Adverting to FIG. 6, CMP is then conducted to form planarized upper surface 60. The resulting Cu metallization comprises interconnection line 61 and a dual damascene Cu metallization structure comprising via 62A electrically connected to interconnection line 62B. Thermal annealing is then conducted, during which Al atoms or Mg atoms from underlying layer 53 diffuse through the Cu metallization, accumulate on the exposed surface thereof, and react with oxygen to form a self-passivating Al oxide or Mg oxide layer 70 encapsulating interconnection 61 and dual damascene Cu metallization 62A, 62B.

Other embodiments of the present invention, include initially depositing an adhesion promoting layer prior to depositing the diffusion barrier layer 52, as illustrated by reference numeral 55 in FIG. 5. Such adhesion promoting layers can comprise materials such as chromium (Cr), Ta, vanadium (V), and molybdenum (Mo).

Other embodiments of the present invention include depositing a seed layer on the Al alloy or Mg alloy layer to improve nucleation and adhesion of the Cu metallization, as illustrated by reference numeral 56 in FIG. 5. Such seed layers can include various Cu alloys, such as a Cu alloyed with Mg, Al, Zn, Zr, Sn, Ni, Pd, Ag or Au. The adhesion promoting layer 55 and seed layer 56 are now shown in FIGS. 6 and 7 for illustrative clarity.

In accordance with the present invention, Cu metallization structures are formed in an efficient, cost-effective manner. The use of Al alloys or Mg alloys avoids the difficulty in plating Cu directly on Al or Mg, since Al and Mg is easily dissolved in a plating solution. The self-encapsulated Cu metallization formed in accordance with the present invention is particularly advantageous in forming inlaid Cu metallization interconnection patterns, particularly in various types of semiconductor devices having sub-micron features and high aspect ratio openings.

In the previous descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a better understanding of the present invention. However, the present invention can be practiced without resorting to the details specifically set forth. In other instances, well-known processing structures have not been described in detail in order not to unnecessarily obscure the present invention.

Only the preferred embodiment of the invention and but a few examples of its versatility are shown and described in the present disclosure. It is to be understood that the present invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4789648Oct 28, 1985Dec 6, 1988International Business Machines CorporationMethod for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
US5592024 *Oct 28, 1994Jan 7, 1997Kabushiki Kaisha ToshibaSemiconductor device having a wiring layer with a barrier layer
US5604156 *Nov 20, 1995Feb 18, 1997Samsung Electronics Co., Ltd.Wire forming method for semiconductor device
US5766379 *Jun 7, 1995Jun 16, 1998The Research Foundation Of State University Of New YorkForming metal layer on face of microelectronic substrate, forming copper layer on the metal layer, annealing to form oxide of metal on copper layer by heating to diffuse some of metal layer through copper layer
US5913147 *Jan 21, 1997Jun 15, 1999Advanced Micro Devices, Inc.Method for fabricating copper-aluminum metallization
US5933758 *May 12, 1997Aug 3, 1999Motorola, Inc.Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer
US6160315 *Jan 6, 2000Dec 12, 2000Applied Materials, Inc.The alloying metal oxide having a thickness of about 6 nm on the oxide sidewalls encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide
Non-Patent Citations
Reference
1P.J. Ding et al. "Effects of the addition of small amounts of A1 to copper: corrosion, resistivity, adhesion, morphology, and diffusion", Journal of Applied Physics, vol. 15, No. 7, Apr. 1994, pp. 3627-3631.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6404055 *May 23, 2001Jun 11, 2002Samsung Electronics Co., Ltd.Semiconductor device with improved metal interconnection and method for forming the metal interconnection
US6426557 *Feb 25, 2000Jul 30, 2002International Business Machines CorporationSelf-aligned last-metal C4 interconnection layer for Cu technologies
US6455418 *Nov 28, 2000Sep 24, 2002Agere Systems Guardian Corp.Barrier for copper metallization
US6475900 *Dec 19, 2000Nov 5, 2002Hyundai Electronics Industries Co., Ltd.Method for manufacturing a metal interconnection having enhanced filling capability
US6498093 *Jan 17, 2002Dec 24, 2002Advanced Micro Devices, Inc.Formation without vacuum break of sacrificial layer that dissolves in acidic activation solution within interconnect
US6501180 *Jul 19, 2000Dec 31, 2002National Semiconductor CorporationStructure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures
US6512281 *Jul 31, 2001Jan 28, 2003Nec CorporationMethod of forming a semiconductor device and an improved deposition system
US6515368 *Dec 7, 2001Feb 4, 2003Advanced Micro Devices, Inc.Semiconductor device with copper-filled via includes a copper-zinc/alloy film for reduced electromigration of copper
US6515373 *Dec 28, 2000Feb 4, 2003Infineon Technologies AgCu-pad/bonded/Cu-wire with self-passivating Cu-alloys
US6521532 *Jul 19, 2000Feb 18, 2003James A. CunninghamMethod for making integrated circuit including interconnects with enhanced electromigration resistance
US6538327 *Jan 15, 2002Mar 25, 2003Advanced Micro Devices, Inc.Method of copper interconnect formation using atomic layer copper deposition and a device thereby formed
US6544891 *Sep 4, 2001Apr 8, 2003Taiwan Semiconductor Manufacturing CompanyMethod to eliminate post-CMP copper flake defect
US6551872 *Aug 18, 2000Apr 22, 2003James A. CunninghamMethod for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby
US6589874 *Jul 26, 2001Jul 8, 2003International Business Machines CorporationMethod for forming electromigration-resistant structures by doping
US6593656Jan 11, 2002Jul 15, 2003Micron Technology, Inc.Multilevel copper interconnects for ultra large scale integration
US6593660 *May 29, 2001Jul 15, 2003International Business Machines CorporationPlasma treatment to enhance inorganic dielectric adhesion to copper
US6602653 *Aug 25, 2000Aug 5, 2003Micron Technology, Inc.Surface oxidation and removal of selected portions forming fine line structures
US6607982 *Mar 23, 2001Aug 19, 2003Novellus Systems, Inc.High magnesium content copper magnesium alloys as diffusion barriers
US6656834Jun 20, 2001Dec 2, 2003Advanced Micro Devices, Inc.Method of selectively alloying interconnect regions by deposition process
US6660633 *Feb 26, 2002Dec 9, 2003Advanced Micro Devices, Inc.Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed
US6686661 *Oct 12, 2000Feb 3, 2004Lg. Philips Lcd Co., Ltd.Liquid crystal displays; oxidation film; contains magnesium; free of migration and hillocks
US6693343 *Dec 28, 2000Feb 17, 2004Infineon Technologies AgLaser fuse prevented from corrosion and oxidation when fuse is blown by laser energy by annealing copper alloy between liner and dielectric cap to provide self-passivating dopant rich layer on top of fuse and at interfaces
US6713873 *Nov 27, 2002Mar 30, 2004Intel CorporationAdhesion between dielectric materials
US6713875 *May 3, 2002Mar 30, 2004Micron Technology, Inc.Barrier layer associated with a conductor layer in damascene structures
US6818991 *Jun 1, 2000Nov 16, 2004Nec Electronics CorporationCopper alloy with ag, as, bi, p, sb, si, ti, semiconductors
US6841477 *Aug 28, 2000Jan 11, 2005Fujitsu LimitedMetal interconnection, semiconductor device, method for forming metal interconnection and method for fabricating semiconductor device
US6844245Dec 23, 2003Jan 18, 2005Infineon Technologies AgMethod of preparing a self-passivating Cu laser fuse
US6900099Dec 18, 2003May 31, 2005Nanya Technology CorporationFlash memory cell and method for fabricating the same
US6903016Aug 14, 2003Jun 7, 2005Uri CohenCombined conformal/non-conformal seed layers for metallic interconnects
US6911394Jan 13, 2003Jun 28, 2005Texas Instruments IncorporatedSemiconductor devices and methods of manufacturing such semiconductor devices
US6972257Jun 16, 2003Dec 6, 2005Micron Technology, Inc.Conductive material patterning methods
US7026714Mar 18, 2004Apr 11, 2006Cunningham James ACopper interconnect systems which use conductive, metal-based cap layers
US7052993Jan 14, 2004May 30, 2006Lg.Philips Lcd Co., Ltd.Thin film transistor having copper alloy wire and method of manufacturing the same
US7105434Dec 28, 2004Sep 12, 2006Uri CohenAdvanced seed layery for metallic interconnects
US7153775Aug 30, 2005Dec 26, 2006Micron Technology, Inc,Conductive material patterning methods
US7164206 *Mar 28, 2001Jan 16, 2007Intel CorporationStructure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer
US7187080 *Oct 14, 2004Mar 6, 2007Texas Instruments IncorporatedSemiconductor device with a conductive layer including a copper layer with a dopant
US7196365 *Apr 25, 2003Mar 27, 2007Sony CorporationSolid-state imaging device, solid-state imaging apparatus and methods for manufacturing the same
US7199052Feb 14, 2005Apr 3, 2007Uri CohenSeed layers for metallic interconnects
US7282445Jan 17, 2007Oct 16, 2007Uri CohenMultiple seed layers for interconnects
US7300860Mar 30, 2004Nov 27, 2007Intel CorporationIntegrated circuit with metal layer having carbon nanotubes and methods of making same
US7339271Jun 3, 2004Mar 4, 2008Intel CorporationMetal-metal oxide etch stop/barrier for integrated circuit interconnects
US7351655Aug 31, 2006Apr 1, 2008Beck Semiconductor LlcCopper interconnect systems which use conductive, metal-based cap layers
US7361589Aug 31, 2006Apr 22, 2008Beck Semiconductor LlcCopper interconnect systems which use conductive, metal-based cap layers
US7372152Apr 6, 2006May 13, 2008Beck Semiconductor LlcCopper interconnect systems
US7462269 *Jun 20, 2001Dec 9, 2008Semitool, Inc.Method for low temperature annealing of metallization micro-structures in the production of a microelectronic device
US7473634Sep 28, 2006Jan 6, 2009Tokyo Electron LimitedMethod for integrated substrate processing in copper metallization
US7510634Nov 10, 2006Mar 31, 2009Novellus Systems, Inc.Apparatus and methods for deposition and/or etch selectivity
US7550386Oct 5, 2007Jun 23, 2009Uri CohenAdvanced seed layers for interconnects
US7572573 *Jan 30, 2006Aug 11, 2009University Of South FloridaMaskless photolithography for etching and deposition
US7585766Mar 26, 2008Sep 8, 2009Cunningham James AMethods of manufacturing copper interconnect systems
US7611984Oct 14, 2005Nov 3, 2009Fujitsu Microelectronics LimitedManufacture method for semiconductor device having improved copper diffusion preventive function of plugs and wirings made of copper or copper alloy
US7645696Jun 22, 2006Jan 12, 2010Novellus Systems, Inc.Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer
US7659197Sep 21, 2007Feb 9, 2010Novellus Systems, Inc.Selective resputtering of metal seed layers
US7682496Mar 28, 2006Mar 23, 2010Uri CohenApparatus for depositing seed layers
US7682966Feb 1, 2007Mar 23, 2010Novellus Systems, Inc.Multistep method of depositing metal seed layers
US7727892 *Sep 25, 2002Jun 1, 2010Intel CorporationMethod and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects
US7732314Mar 5, 2007Jun 8, 2010Novellus Systems, Inc.Method for depositing a diffusion barrier for copper interconnect applications
US7759712Nov 30, 2006Jul 20, 2010Sony CorporationSolid-state imaging device, solid-state imaging apparatus and methods for manufacturing the same
US7759797 *Oct 11, 2006Jul 20, 2010Taiwan Semiconductor Manufacturing Co., Ltd.Bonding pad structure to minimize IMD cracking
US7781327Oct 26, 2006Aug 24, 2010Novellus Systems, Inc.considerable etching of the diffusion barrier material at the via bottom, while not damaging exposed dielectric elsewhere on the wafer;
US7842605May 24, 2007Nov 30, 2010Novellus Systems, Inc.Atomic layer profiling of diffusion barrier and metal seed layers
US7846833Mar 25, 2010Dec 7, 2010Fujitsu LimitedManufacture method for semiconductor device suitable for forming wirings by damascene method and semiconductor device
US7846839 *Oct 3, 2005Dec 7, 2010Tokyo Electron LimitedFilm forming method, semiconductor device manufacturing method, semiconductor device, program and recording medium
US7855147May 24, 2007Dec 21, 2010Novellus Systems, Inc.Methods and apparatus for engineering an interface between a diffusion barrier layer and a seed layer
US7892976 *Jun 5, 2009Feb 22, 2011Renesas Electronics CorporationSemiconductor device and method for manufacturing the same
US7897516May 24, 2007Mar 1, 2011Novellus Systems, Inc.Use of ultra-high magnetic fields in resputter and plasma etching
US7902062May 23, 2005Mar 8, 2011Infineon Technologies AgElectrodepositing a metal in integrated circuit applications
US7922880May 24, 2007Apr 12, 2011Novellus Systems, Inc.Method and apparatus for increasing local plasma density in magnetically confined plasma
US8003518 *Sep 24, 2009Aug 23, 2011Fujitsu Semiconductor LimitedSemiconductor device fabrication method
US8017523May 16, 2008Sep 13, 2011Novellus Systems, Inc.Deposition of doped copper seed layers having improved reliability
US8043484Jul 30, 2007Oct 25, 2011Novellus Systems, Inc.Methods and apparatus for resputtering process that improves barrier coverage
US8123861Mar 22, 2010Feb 28, 2012Seed Layers Technology, LLCApparatus for making interconnect seed layers and products
US8178437 *Jul 29, 2008May 15, 2012Taiwan Semiconductor Manufacturing Co., Ltd.Barrier material and process for Cu interconnect
US8211740Feb 9, 2010Jul 3, 2012Sony CorporationSolid state imaging device having wirings with diffusion prevention film
US8216940Feb 2, 2011Jul 10, 2012Renesas Electronics CorporationMethod for manufacturing a semiconductor device
US8298933May 15, 2009Oct 30, 2012Novellus Systems, Inc.Conformal films on semiconductor substrates
US8298936Feb 3, 2010Oct 30, 2012Novellus Systems, Inc.Multistep method of depositing metal seed layers
US8299617Apr 19, 2010Oct 30, 2012Intel CorporationMethod and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects
US8383509Feb 28, 2011Feb 26, 2013Fujitsu Semiconductor LimitedManufacture method for semiconductor device having improved copper diffusion preventive function of plugs and wirings made of copper or copper alloy and semiconductor device of this kind
US8449731Feb 23, 2011May 28, 2013Novellus Systems, Inc.Method and apparatus for increasing local plasma density in magnetically confined plasma
US8502381 *Jan 25, 2011Aug 6, 2013Lam Research CorporationBarrier layer configurations and methods for processing microelectronic topographies having barrier layers
US8586471Jan 17, 2012Nov 19, 2013Uri CohenSeed layers for metallic interconnects and products
US8591985Jul 19, 2010Nov 26, 2013Lam Research CorporationSystems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes
US8653663 *Apr 9, 2010Feb 18, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Barrier layer for copper interconnect
US8679972May 29, 2013Mar 25, 2014Novellus Systems, Inc.Method of depositing a diffusion barrier for copper interconnect applications
US8765596Oct 22, 2010Jul 1, 2014Novellus Systems, Inc.Atomic layer profiling of diffusion barrier and metal seed layers
US20090243106 *May 18, 2009Oct 1, 2009Farrar Paul AStructures and methods to enhance copper metallization
US20110117328 *Jan 25, 2011May 19, 2011Lam ResearchBarrier Layer Configurations and Methods for Processing Microelectronic Topographies Having Barrier Layers
US20120074573 *Sep 29, 2010Mar 29, 2012Dallmann GeraldSemiconductor structure and method for making same
US20130260553 *May 13, 2013Oct 3, 2013Hui Jae YooSelf-forming, self-aligned barriers for back-end interconnects and methods of making same
USRE41538Apr 22, 2005Aug 17, 2010Cunningham James AMethod for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby
CN100385660CJul 29, 2005Apr 30, 2008台湾积体电路制造股份有限公司Semiconductor element of improved electronic migration and method for forming semiconductor element
CN100430520CDec 30, 2005Nov 5, 2008东北大学Process for copper coating on surface of magnesium and magnesium alloy
CN100481377COct 28, 2005Apr 22, 2009富士通微电子株式会社Semiconductor device and manufacturing method
CN100490113CApr 2, 2002May 20, 2009先进微装置公司Metal interconnection structure and its manufacture method
CN100585830CNov 20, 2003Jan 27, 2010因芬尼昂技术股份公司Method for electrodepositing a metal, especially copper, use of said method and integrated circuit
CN101504932BOct 28, 2005Jun 29, 2011富士通半导体股份有限公司Semiconductor device and manufacturing method
EP1341227A2 *Feb 4, 2003Sep 3, 2003Texas Instruments Inc.Interconnection structure in semiconductor devices and method for making the same
EP1744358A1 *Oct 4, 2005Jan 17, 2007Fujitsu LimitedSemiconductor device and manufacturing method
EP2028686A1Nov 20, 2003Feb 25, 2009Infineon Technologies AGMethod for electrodepositing a metal, especially copper, and use of said method
EP2128899A1 *Nov 20, 2003Dec 2, 2009Infineon Technologies AGMethod for electrodepositing a metal, especially copper, use of said method and integrated circuit
WO2003001589A2 *Apr 2, 2002Jan 3, 2003Advanced Micro Devices IncA method of selectively alloying interconnect regions by depostion process
WO2004049431A1 *Nov 20, 2003Jun 10, 2004Stephan BradlMethod for electrodepositing a metal, especially copper, use of said method and integrated circuit
WO2013142207A1 *Mar 13, 2013Sep 26, 2013Lam Research CorporationElectroless copper alloy capping
Classifications
U.S. Classification257/758, 257/E21.585, 257/752, 257/751, 257/E21.584, 257/762, 257/765
International ClassificationH01L21/768, H01L23/532
Cooperative ClassificationH01L21/76846, H01L21/76843, H01L21/76874, H01L21/76831, H01L23/53238, H01L21/76888, H01L21/76873, H01L21/76877, H01L21/76834, H01L23/53233
European ClassificationH01L23/532M1C4, H01L23/532M1C2, H01L21/768C4, H01L21/768C8B, H01L21/768B10S, H01L21/768C3S4, H01L21/768C3B, H01L21/768C3B4, H01L21/768C3S2, H01L21/768B10B
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