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Publication numberUS6277725 B1
Publication typeGrant
Application numberUS 09/348,396
Publication dateAug 21, 2001
Filing dateJul 7, 1999
Priority dateJul 7, 1999
Fee statusPaid
Publication number09348396, 348396, US 6277725 B1, US 6277725B1, US-B1-6277725, US6277725 B1, US6277725B1
InventorsChih-Hsiang Hsiao
Original AssigneeUnited Microelectronics Corp.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for fabricating passivation layer on metal pad
US 6277725 B1
Abstract
A method for fabricating a passivation layer on a metal pad. A conformal first silicon dioxide layer is formed on a substrate having a metal pad. A conformal first silicon nitride layer is formed on the first silicon dioxide layer, and then a second silicon dioxide layer is formed on the first silicon nitride layer by high density plasma chemical vapor deposition. The second silicon dioxide layer is planarized to expose the first silicon nitride layer. A portion of the first silicon nitride layer aligned over the metal pad is removed to expose the first silicon dioxide layer. A second silicon nitride layer is formed to cover the first silicon dioxide layer and the second silicon dioxide layer. In the above process, a thickness of the first silicon dioxide layer and a thickness of the second silicon nitride layer are precisely controlled.
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Claims(16)
What is claimed is:
1. A method for fabricating a passivation layer on a metal pad, comprising the steps of:
providing a substrate having a metal pad;
forming a conformal first silicon dioxide layer on the substrate;
forming a conformal first silicon nitride layer on the first silicon di oxide layer;
forming a second silicon dioxide layer on the first silicon nitride layer by high density plasma chemical vapor deposition;
planarizing the second silicon dioxide layer to expose the first silicon nitride layer;
removing only a portion of the first silicon nitride layer which is aligned over the metal pad to expose the first silicon dioxide layer; and
forming a second silicon nitride layer to cover the first silicon dioxide layer and the second silicon dioxide layer.
2. The method of claim 1, wherein constructive interference is produced after light passes through the first silicon dioxide layer and the second silicon nitride layer, and is reflected from the metal pad.
3. The method of claim 1, wherein a thickness of the first silicon dioxide layer is about 700 to 800 Å.
4. The method of claim 1, wherein a thickness of the first silicon nitride layer is about 500 to 2000 Å.
5. The method of claim 1, wherein a thickness of the second silicon nitride layer is about 600 to 700 Å.
6. A method for fabricating a passivation layer on a metal pad, comprising the steps of:
providing a substrate having a metal pad;
forming a conformal first silicon dioxide layer and a conformal first silicon nitride layer on the substrate in sequence;
forming a second silicon dioxide layer on the first silicon nitride layer, during which formation a portion of the first silicon nitride layer at top corners on the metal pad is removed;
planarizing the second silicon dioxide layer to expose the first silicon nitride layer;
removing only a portion of the conformal first silicon nitride layer which is aligned layer the metal pad to expose the first silicon dioxide layer; and
forming a second silicon nitride layer to cover the first silicon dioxide layer and the second silicon dioxide layer.
7. The method of claim 6, wherein constructive interference is produced after light passes through the first silicon dioxide layer and the second silicon nitride layer, and is reflected from the metal pad.
8. The method of claim 6, wherein a thickness of the first silicon dioxide layer is about 700 to 800 Å.
9. The method of claim 6, wherein a thickness of the first silicon nitride layer is about 500 to 2000 Å.
10. The method of claim 6, wherein the step of forming the second silicon dioxide layer comprises high density plasma chemical vapor deposition.
11. The method of claim 6, wherein a thickness of the second silicon nitride layer is about 600 to 700 Å.
12. A method for fabricating a passivation layer on a metal pad, comprising the steps of:
providing a substrate having a plurality of metal pads, wherein spaces are formed between the metal pads;
forming a conformal first silicon oxide layer on the substrate, covering the metal pads;
forming a conformal first silicon nitride layer on the first silicon oxide layer;
forming a second silicon oxide layer on the first silicon nitride layer and filling the spaces between the metal pads, during which formation a portion of the first silicon nitride layer at top corners of the metal pads is removed;
planarizing the second silicon oxide layer until the first silicon nitride layer aligned over the metal pads is exposed, wherein the first silicon nitride layer aligned along the sides of the metal pads is still concealed by the second silicon oxide layer;
removing the first silicon nitride layer which is aligned over the metal pad to expose the first silicon oxide layer; and
forming a second silicon nitride layer on a planar surface of the first silicon oxide layer and the second silicon oxide layer.
13. The method of claim 12, wherein a thickness of the first silicon oxide layer is about 700 angstroms to 800 angstroms thick.
14. The method of claim 12, wherein a thickness of the second silicon oxide layer is about 500 angstroms to about 2000 angstroms thick.
15. The method of claim 12, wherein a thickness of the second silicon nitride layer is about 600 angstroms to about 700 angstroms thick.
16. The method of claim 12, wherein forming the second silicon dioxide layer comprises performing high density plasma chemical vapor deposition.
Description
BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a method for fabricating a passivation layer on a metal pad. More particularly, the present invention relates to a method for fabricating a passivation layer on a metal pad in which the passivation layer protects the metal pad from damage.

2. Description of Related Art

In a conventional semiconductor manufacturing process metal pads are formed on a substrate; some metal pads are for wire bonding and others serve as a high reflectance material layer. After the metal pads are formed, a first silicon dioxide layer serving as a passivation layer is formed by high density plasma chemical vapor deposition to cover the metal pads, and a thickness of the first silicon dioxide layer is 5000 to 15000 Å. A chemical mechanical polishing process is performed to reduce the thickness of the first silicon dioxide layer. After the chemical mechanical polishing process, the thickness of the first silicon dioxide layer is 1500 to 2000 Å. Then, a portion of the first silicon dioxide layer is removed by dry etching to expose the metal pads, so that the residual first silicon dioxide layer remains only between the metal pads. A second silicon dioxide layer whose thickness is controlled precisely and a silicon nitride layer are formed in sequence over the substrate. After light passes through the second silicon dioxide layer and the silicon nitride layer, and is reflected from the metal pads serving as the high reflectance material layer, constructive interference is produced.

In the above process, a dishing effect occurs after the chemical mechanical polishing process and the first silicon dioxide layer is excessively removed during the dry etching process. As a result, the planarity of the semiconductor is poor. Furthermore, the surface of each of the metal pads is damaged during the dry etching process, so that reflectance of each of the metal pads is reduced.

SUMMARY OF THE INVENTION

The invention provides a method for fabricating a passivation layer on a metal pad in which the passivation layer protects the metal pad from damage.

As embodied and broadly described herein, the invention provides a method for fabricating a passivation layer on a metal pad. A conformal first silicon dioxide layer is formed on a substrate having a metal pad. A conformal first silicon nitride layer is formed on the first silicon dioxide layer, and then a second silicon dioxide layer is formed on the first silicon nitride layer by high density plasma chemical vapor deposition. The second silicon dioxide layer is planarized to expose the first silicon nitride layer. A portion of the first silicon nitride layer aligned over the metal pad is removed to expose the first silicon dioxide layer. A second silicon nitride layer is formed to cover the first silicon dioxide layer and the second silicon dioxide layer. In the above process, a thickness of the first silicon dioxide layer and a thickness of the second silicon nitride layer should be controlled precisely.

In the invention, the first silicon dioxide layer covers the metal pad, so that the surface of the metal pad is not damaged during the process. Therefore, reflectance of the metal pad is maintained. Additionally, constructive interference is produced after light passes through the first silicon dioxide layer and the second silicon nitride layer and is reflected from the metal pad because the thicknesses of the first silicon dioxide layer and the second silicon dioxide layer are controlled precisely. By controlling the thickness of the first silicon nitride layer and the chemical mechanical polishing process, the surface composed of the first silicon dioxide layer and the second silicon dioxide layer is planar.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

FIGS. 1A through 1E are schematic, cross-sectional diagrams illustrating a method for fabricating a passivation layer on a metal pad according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1A through 1E are schematic, cross-sectional diagrams illustrating a method for fabricating a passivation layer on a metal pad according to the invention.

Referring to FIG. 1A, a substrate 100 having devices (not shown) is provided. A metal pad 102 is formed on the substrate 100. Metal pads formed on the substrate have two applications: either for wire bonding or as a high reflectance material layer. Even though the metal pads have different uses, they are formed in the same process. In this embodiment, the metal pad 102 is used as a high reflectance material layer.

A conformal silicon dioxide layer 104 serving as a passivation layer and a silicon nitride layer 106 are formed on the substrate 100 in sequence. A thickness of the silicon dioxide layer 104 is about 700 to 800 Å and the thickness of the silicon dioxide layer 104 should be controlled precisely; a thickness of the silicon nitride layer 106 is about 500 to 2000 Å.

Referring to FIG. 1B, a silicon dioxide layer 108 is formed over the substrate 100 by, for example, high density plasma chemical vapor deposition. Since an etching process and a depositing process are performed simultaneously during the high density plasma chemical vapor deposition process, a portion of the silicon nitride layer 106 and a portion of the silicon dioxide layer 104, which are at a corner 110 of the metal pad 102, are removed while forming the silicon dioxide layer 108. Therefore, silicon nitride layer 106 a, 106 b and a silicon dioxide layer 104 a are formed, wherein at the corner 110 of the metal pad 102, the silicon dixoxide layer 104 a is directly in contact with the silicon dioxide layer 108. The silicon nitride layer 106 b is on top of the metal pad 102.

Referring to FIG. 1C, the silicon dioxide layer 108 is planarized to expose the silicon nitride layer 106 b, and then a silicon dioxide layer 108 a is formed. The planarization process is preferably chemical mechanical polishing. The silicon nitride layer 106 a is still covered by the silicon dioxide layer 108 a after the planarizing process.

Referring to FIG. 1D, the silicon nitride layer 106 b (FIG. IC) is removed to expose the silicon dioxide layer 104 a above the metal pad 102 by, for example, wet etching. An etchant used to perform the wet etching process is preferably hot phosphoric acid. When the silicon nitride layer 106 b is removed by wet etching, the silicon dioxide layer 104 a is not etched because the silicon dioxide layer 104 a is covered by the silicon nitride layer 106 a and the silicon dioxide layer 108 a. Furthermore, since the silicon nitride layer 106 a is covered by the silicon dioxide layer 108 a without being contact with the silicon nitride layer 106 b, the silicon nitride layer 106 a is not simultaneously removed with the removal of the silicon nitride layer 106 b by the wet etching process.

By controlling the thickness of the silicon nitride layer 106 (FIG. 1) and the chemical mechanical polishing process, the entire surface composed of the silicon dioxide layer 104 a and the silicon dioxide layer 108 a can be formed planar.

Referring to FIG. 1E, a silicon nitride layer 112 whose thickness is about 600 to 700 Å is formed to cover the silicon dioxide layers 104 a, 108 a. The thickness of the silicon nitride layer 112 should be also controlled precisely.

Since the silicon dioxide layer 104 a covers the metal pad 102, the surface of the metal pad 102 is not damaged during the process, so that reflectance of the metal pad 102 is maintained. By controlling the thickness of the silicon dioxide layer 104 and the silicon nitride layer 112 precisely, constructive interference is produced after light passes through the silicon dioxide layer 104 and the silicon nitride layer 112, and is reflected from the metal pad 102.

According to the foregoing, the advantages of the invention include the following:

1. In the invention, the silicon dioxide layer covers the metal pad, so that the metal pad is not damaged during the manufacturing process. As a result, reflectance of the metal pad is maintained.

2. The surface of the semiconductor is planarized by controlling the thickness of the silicon nitride layer on the metal pad and the chemical mechanical polishing process.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5792705 *Sep 2, 1997Aug 11, 1998Taiwan Semiconductor Manufacturing Company, Ltd.Optimized planarization process for SOG filled vias
US5851603 *Jul 14, 1997Dec 22, 1998Vanguard International Semiconductor CorporationMethod for making a plasma-enhanced chemical vapor deposited SiO2 Si3 N4 multilayer passivation layer for semiconductor applications
US6030881 *May 5, 1998Feb 29, 2000Novellus Systems, Inc.High throughput chemical vapor deposition process capable of filling high aspect ratio structures
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8567658 *Jul 16, 2010Oct 29, 2013Ontos Equipment Systems, Inc.Method of plasma preparation of metallic contacts to enhance mechanical and electrical integrity of subsequent interconnect bonds
US20110011531 *Jul 16, 2010Jan 20, 2011Set North America, LlcMethod of plasma preparation of metallic contacts to enhance mechanical and electrical integrity of subsequent interconnect bonds
Classifications
U.S. Classification438/612, 257/E21.279, 257/E21.58, 438/751, 257/E21.576, 438/613, 438/759, 438/624, 438/756, 257/E21.293, 257/E21.269, 257/E21.244, 438/757
International ClassificationH01L21/314, H01L21/316, H01L21/318, H01L21/768, H01L21/3105
Cooperative ClassificationH01L21/76834, H01L21/76832, H01L21/3145, H01L21/31053, H01L21/3185, H01L21/31612, H01L21/76819, H01L21/76801
European ClassificationH01L21/768B10S, H01L21/768B10M, H01L21/768B, H01L21/314B2, H01L21/768B4
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Jan 20, 2013FPAYFee payment
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Jan 24, 2000ASAssignment
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UNITED SEMICONDUCTOR CORP.;REEL/FRAME:010579/0570
Effective date: 19991230
Owner name: UNITED MICROELECTRONICS CORP. SCIENCE-BASED INDUST
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UNITED SEMICONDUCTOR CORP.;REEL/FRAME:010579/0570
Effective date: 19991230
Jul 7, 1999ASAssignment
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HSIAO, CHIH-HSIANG;REEL/FRAME:010090/0993
Effective date: 19990607
Owner name: UNITED SEMICONDUCTOR CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HSIAO, CHIH-HSIANG;REEL/FRAME:010090/0993
Effective date: 19990607