US 6282690 B1 Abstract A circuit for inserting a parity signal into a data stream, including a precoder circuit to precode the data stream to be written on a medium by generating a precoded data stream; a parity circuit to generate a parity signal based on said data stream at a predetermined time; and an insertion circuit to insert said parity signal into said precoded data stream.
Claims(5) 1. A circuit for inserting a parity signal into a data stream, comprising:
a precoder circuit to precode the data stream to be written on a medium by generating a precoded data stream;
a parity circuit to generate a parity signal based on said precoded data stream at a predetermined time; and
an insertion circuit to insert said parity signal into said precoded data stream,
wherein said precoder circuit includes a feedback circuit based on an output of said insertion circuit.
2. A circuit for inserting a parity signal into a data stream, as in claim
1, wherein said parity signal is inserted following said precoded data stream.3. A circuit for inserting a parity signal into a data stream, as in claim
1, wherein said precoder circuit is clocked at every clock pulse.4. A circuit for inserting a parity signal into a data stream, as in claim
1, wherein said parity circuit is clocked only at said predetermined time.5. A circuit for inserting a parity signal into a data stream, as in claim
1, wherein said precoder circuit is not clocked at said predetermined time.Description The present invention relates generally to write precoders for use in magnetic storage disk drives and more particularly to a method and apparatus for detecting and controlling errors within a data stream through a write precoder. Conventional magnetic storage devices include a magnetic transducer or “head” suspended in close proximity to a recording medium, for example, a magnetic disk having a plurality of concentric tracks. The transducer is supported by an air-bearing slider mounted to a flexible suspension. The suspension in turn is attached to a positioning actuator. During normal operation, relative motion is provided between the head and the recording medium as the positioning actuator dynamically positions the head over the desired track. The information recorded on the magnetic disk is transmitted to a preamplifier which is in turn transmitted to a read channel. One example of read channels in use in today's technology is a PRML read channel. The magnetic recording channel can be characterized as a channel with significant intersymbol interference, particularly at high recording densities. Partial response maximum likelihood (PRML) detection systems based on shaping the channel response to a suitable partial response have become a popular detection method for such channels. Partial responses such as class IV partial response (PR4) and enhanced PR4 (EPR4) are common due to their good performance on moderate density and high density channels. At higher densities, higher order polynomials such as EEPR4 have been proposed. These partial responses are of the form (1−D)(1+D) As recording densities increase, the use of trellis-based coding schemes have also been proposed. These include matched spectral null coding schemes based on the matched spectral null theorem. These have been used to increase the minimum distance on the PR4 based target from 2{square root over (2)} to 4 and have achieved efficient implementations with practical code rates of 8/10 through the use of time varying trellises. At higher recording densities with higher order partial responses, run length constrained codes demonstrate improved distance properties. For example, the use of an EEPR4 target with a 2/3(1,7) code increases the minimum distance from 2{square root over (6)} to 2{square root over (10)}. Codes achieving the same increase in minimum distance but without the “d=1” constraint such as maximum transition run length (MTR) codes have been proposed for the EEPR4 partial response and finite delay tree search type detectors. These run length constrained codes help simplify the target trellis by eliminating states. Even higher rate codes to achieve the same increase in minimum distance have also been proposed. These include a family of codes and the rate 8/9 code based on a time varying MTR (TMTR) constraint. Coding to detect and eliminate certain error events on the PR4 channel was considered. The eliminated error events were the ones most likely due to noise correlation from the equalization to the PR4 response. This achieved an increase in detection SNR of ≈1.25 dB with a rate 8/9 code at recording densities around 2 bits per PW A single bit parity code is utilized to detect the presence of the identified dominant error events. This coding constraint can achieve a moderate coding gain but with a high code rate which is desirable for high density magnetic recording. For the detection of the coded data, a postprocessor is possible based on correlating the received signal to identify the likely locations of the error events. The most likely event is then corrected. The basic recording and detection system model is shown in FIG. 5 with the channel response based on the Lorentzian step response. The channel frequency response is
where PW The recording channel is often shaped to the required target frequency response G(ƒ) through the use of a continuous time and discrete time filter. For the purpose of analysis, the continuous time filter is assumed to band limit the signal and equalize it to the desired response before sampling at the baud rate 1/T. The equalizer is assumed to minimize the mean square error between the equalizer output and the desired target. This requires an equalizer response of where S While this includes distortion, it is considered as Gaussian noise for the purpose of analysis and the noise autocorrelation is assumed to be With maximum likelihood detection, the error rate performance is determined by the distance between any two allowable data sequences and the noise correlation. The probability of an error event occurring in the presence of correlated noise can be calculated as where the error event {e
where * denotes convolution and the sequence g
The error rate performance of the system depends on the likelihood of error events occurring and the noise correlation. As the recording density increases, the optimum target response changes and the likelihood of particular error events change relative to each other. Using the system model to calculate the noise autocorrelation and enumerating the possible error events, the relative likelihood of possible error events can be ranked. Tables I and II list the most likely error events for a channel response target of (1−D As the dominant error events are a While an event length parity code with odd parity can provide some run length constraints with a rate (N−1)/N, stricter constraints may be required to ensure sufficient timing and gain recovery information. An interleaved run length constraint is also required to ensure Viterbi path merging on a target with a Nyquist and DC null. While a time varying trellis incorporating the target response and the parity constraint could be constructed, it would require twice the number of states than the target response on its own. This would require a considerably more complex detector. However, decoding may be achieved through the use of a post processor. The basic detector structure is shown in FIG.
These noise estimates are correlated with the two likely error events to produce a noise correlation for each event at each bit time. The correlation filter is the error event convolved with the channel response all reversed in time. For example, the a
A similar filter is used for the a At each bit time the maximum of the valid noise correlation values and the corresponding type of error event is stored. At each code word boundary, the parity constraint on the estimated bits is checked. If the parity constraint is violated, the maximum valid noise correlation value over the length of the code words and across its boundaries is identified. The estimated bits {tilde over (x)} The use of such a postprocessor avoids increasing the complexity of the Viterbi detector, particularly when only a small number of error events need to be detected. Modulation code on user data for use with recording channels is also known. Binary user data is mapped into constrained sequences, called (D,K/I) sequences, where D represents the minimum and K represents the maximum number of 0's between any pair of consecutive 1's. The parameter I represents the maximum run length of zeroes in the particular all-even and or all-odd subsequences. In a PRML system, such as EPR4, a small value of K is desirable for accurate timing and gain control, and a small value of I value reduces the length of survival registers required in the Viterbi detector due to the reducing length of the Quasi-catastrophic sequences. Using a rate 16/17 base code with constraint (0,6/8), the resulting parity code with have a 16/18 code rate. An even higher rate code can be constructed to meet run length requirements and the parity constraint. Consider a rate 16/17(0,6/8) code which consists of freely concatenateable code words of length 17. If at the end of each pair of code words (34 bits) an additional parity bit is appended, the result is a 32/35 (0,7/9) code. Likewise, if a parity bit is appended to each 3 code words (51 bits), the resulting system will attain a overall 51152 (0,7/9) code. However, the above illustration does not take into consideration the effect of the precoder. FIG. 4A shows a system diagram with the parity bit being inserted before the write precoder, and the parity check after the postcoder during the read process. Inserting the parity bit upstream in the data before the precoder can cause considerable adverse effects. When an error occurs at the boundary of these parity-coded data blocks, the introduced parity bit cannot detect the error if the error event sequence spans over the boundaries of the parity-code data blocks. Therefore, dominant error events with long length could result in higher probability of causing a non-detectable error and reduces the effectiveness of the parity bit post-processing scheme. In an EPR4 channel, the most dominant error events are +/−(1) and +/−(1−1 1) at the output of Viterbi detector. After the postcoding, these two major errors become (1 0 1) and (1 1 0 1 1) assuming a 1/(1xor D The present invention inserts a parity bit into the data stream after the data stream has been precoded by a precoder circuit. Furthermore, the present invention maintains constraints on an encoded word by not breaking the constraints. More particularly, the present invention inserts a parity bit in the RLL code by using feedback in the write precoder which maintains the (D,K/I) constraints. The present invention does not require the need of clock gapping on the precoder side of the parity insertion circuit. The present invention reduces the length of the error event and solves the uncorrectable data problem at the codeword boundaries by inserting the parity bit after the precoder and removing it correspondingly before the postcoder. FIG. 1 illustrates a write precoder and parity insertion circuit with feedback. FIG. 2 illustrates a write precoder and parity insertion circuit without feedback. FIG. 3 illustrates a system of the present invention. FIG. 4 illustrates an example of parity insertion after the precoder with feedback. FIG. 4A illustrates an example of parity insertion before the precoder. FIG. 5 illustrates a detection system model. FIG. 6 illustrates detector structure. In an EPR4 channel, the most dominant error events are +/−(1) and +/−(1−1 1) at the output of Viterbi detector. The EPR4 postprocessor with the parity check circuitry identifies and corrects the above two major error events. After the postcoding, these two major errors become (1 0 1) and (1 1 0 1 1) assuming a 1/(1 xor D
FIG. 2 illustrates a write precoder circuit Additionally, the output from the precoder circuit is input to the exclusive OR circuit The parity bit inserted using the method in FIG. 2 will disturb the precoded data stream and the runlength constraint of the data stream will be increased. For a general base RLL of constraint (0,K/I), the resulting RLL constraint of a system with direct parity insertion after the precoder in FIG. 2 will be (0,K+K/2/I+I/ FIG. 3 illustrates a write precoder circuit with parity insertion and feedback. This circuit inserts a parity bit into the encoded data at predetermined position and the resulting runlength constraint will only be increased to (0,K+1/I+ Turning now to FIG. 1, a precoder receives the input data. The output of D flip-flop FIG. 4 illustrates a system diagram of the present invention. An I/F controller FIG. 3 shows user data with a 16/17 code, three groups of 17 bits of user data combined to form 51 bits, leaving the 52nd bit free for a parity bit. Likewise, with a 24/25 code, two groups of 25 bits form 50 bits, leaving a 51st bit for a parity bit. Patent Citations
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