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Publication numberUS6301366 B1
Publication typeGrant
Application numberUS 09/031,447
Publication dateOct 9, 2001
Filing dateFeb 26, 1998
Priority dateOct 14, 1997
Fee statusPaid
Also published asUS6314330, US6373954, US6405093, US6628999, US6952621
Publication number031447, 09031447, US 6301366 B1, US 6301366B1, US-B1-6301366, US6301366 B1, US6301366B1
InventorsRonald D. Malcolm, Jr., Jeff Klaas
Original AssigneeCirrus Logic, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Single-chip audio system mixing circuitry and methods
US 6301366 B1
Abstract
An audio system 100 disposed on a single chip includes an output mixer 115 having inputs for receiving first digital audio data of a first bit width from a first digital-to-analog converter 110, digital audio data of a second bit width from a second digital-to-analog converter 6601, and analog data from an external port. An output port drives an analog signal output from the output mixer. An input mixer 114 has inputs for receiving analog data from a plurality of sources and analog-to-digital converters 111 to convert an analog output from the input mixer into digital data. An input path transmits the digital data output from the analog to digital convertors 111 to an external digital bus.
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Claims(11)
What is claimed is:
1. An audio system disposed on a single chip:
an output mixer having inputs for receiving first digital audio data of a first bit width from a first digital to analog converter, second digital audio data of a second bit width from a second digital to analog converter, and analog data from a first selected one of a plurality of analog external sources;
an output port for driving an analog signal output from said output mixer;
an input mixer having inputs for receiving analog data from second selected ones of said plurality of analog external sources;
an analog to digital converter for converting an analog output of said input mixer into digital data; and
an input path for transmitting said digital data output from said analog to digital converters to an external digital bus.
2. The audio system of claim 1 wherein said first digital audio data is input to said first digital to analog converter from said external digital bus.
3. The audio system of claim 1 and further comprising an FM synthesizer, said synthesizer outputing data to an input of said second digital to analog converter.
4. The audio system of claim 1 wherein an input to said second digital to analog converter receives data from an external wavetable generator.
5. The audio system of claim 1 wherein an input to said second digital to analog converter receives a signal comprising mixed wavetable and FM synthesizer data.
6. The audio system of claim 1 wherein said first bitwidth equals said second bitwidth.
7. The audio system of claim 1 wherein said first bitwidth is greater than said second bitwidth.
8. The audio system of claim 1 wherein an input of said analog to digital converter receives data from an external audio accelerator.
9. The audio system of claim 1 and further comprising a microcontroller for implementing overall control of said audio system.
10. The audio system of claim 1 wherein an input to said first digital to analog converter and an input to said second digital to analog converter is coupled to a serial port for interfacing with an external serial device.
11. The audio system of claim 1 wherein said input path comprises an ISA bus interface.
Description

This is a division of application Ser. No. 08/949,563 filed Oct. 14, 1997 entitled SINGLE-CHIP AUDIO CIRCUITS, METHODS, AND SYSTEMS USING THE SAME.

CROSS REFERENCE TO RELATED APPLICATIONS

This application for patent is related to the following applications for patent:

Pending U.S. patent application Ser. No. 08/949,563 entitled “SINGLE-CHIP AUDIO CIRCUITS, METHODS AND SYSTEMS USING THE SAME”, filed Oct. 14, 1997;

AUDIO SPATIAL ENHANCEMENT CIRCUITRY AND METHODS USING THE SAME, U.S. patent application Ser. No. 09/031,156, filed concurrently herewith;

SINGLE-CHIP AUDIO SYSTEM POWER REDUCTION CIRCUITRY AND METHODS, U.S. patent application Ser. No. 09/031,116, filed concurrently herewith;

SIGNAL AMPLITUDE CONTROL CIRCUITRY AND METHODS, U.S. patent application Ser. No. 09/031,439, filed concurrently herewith;

SINGLE-CHIP AUDIO SYSTEM VOLUME CONTROL CIRCUITRY AND METHODS, U.S. patent application Ser. No. 09/031,112, filed concurrently herewith;

OSCILLATOR START-UP CIRCUITRY AND SYSTEMS AND METHODS USING THE SAME, U.S. patent application Ser. No. 09/031,444, filed concurrently herewith.

These applications for patent are hereby incorporated by reference in the present disclosure as fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to digital data processing and in particular to single-chip audio circuits, methods and systems using the same.

2. Description of the Related Art

The ability to process audio information has become increasingly important in the personal computer (PC) environment. Among other things, audio is important in many multimedia applications, such as gaming and telecommunications. Audio functionality is therefore typically available on most conventional PCs, either in the form of an add-on audio board or as a standard feature provided on the motherboard itself. In fact, PC users increasingly expect not only audio functionality but high quality sound capability.

The key components in most digital audio information processing systems convert input analog audio information into a digital format for processing processor, support sample rate conversion, SoundBlaster compatibility, wavetable synthesis, or DirectSound acceleration, convert outgoing signals from digital to analog format for eventual audible output to the user, and mix analog and/or digital data streams. In conventional systems, these functions must be provided through multiple chip solutions which make board design and fabrication more complex and expensive.

Thus, to meet the demands of increasingly sophisticated computer users, the need has arisen for new circuits and methods for implementing single-chip audio systems and systems using the same. Among other things, such circuits and methods should provide for the implementation of systems for use with high quality sound systems and should support the latest sound processing standards and game designs.

SUMMARY OF THE INVENTION

A single chip audio system includes a bus interface, digital to analog converters, analog mixer, and analog spatial enhancement circuitry. Digital to analog converters convert digital audio data received through bus interface into analog signals. The Analog mixer mixes signals received from digital to analog converters with an analog signal received from an external source. Analog spatial enhancement circuitry enhances first and second mixed analog signals output from analog mixer.

The principles of the present invention substantially meet the demand of increasingly sophisticated computer users for audio subsystems which produce high quality sound. Additionally, the application of the principles of the present invention allows for the provision of such features as stereo full-duplex coding/decoding, CD differential input, mono microphone input, a headphone output, as well as digital connections to a companion audio controller, as desired.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1A is a diagram of an audio codec according to the principles of the present invention;

FIG. 1B is a diagram of an information processing system employing the audio codec of FIG. 1A;

FIG. 2 is a diagram providing a general overview of the bus structure and principle registers of the codec in FIG. 1A;

FIG. 3 is a functional block diagram of the codec: microcontroller core;

FIG. 4 is a diagram of the microcontroller memory map;

FIG. 5 is a diagram of the mapping of the program RAM space;

FIG. 6 is a diagram of the microcontroller External RAM data definition;

FIG. 7 is a diagram illustrating the timing of a Request/Grant handshake mechanism;

FIG. 8 is a diagram of the bitfields of Port 3 Bit Definitions;

FIG. 9 is a diagram providing an overview of the circuitry supporting a Plug & Play (PnP) interface to an external ISA bus;

FIG. 10A is a diagram emphasizing the configuration/interface logic for a PnP compatible device;

FIG. 10B is a diagram illustrating the typical functional elements of an LFSR device, including a series of storage/shift elements and logic;

FIG. 10C is a diagram of the LSFR checksum circuitry;

FIG. 11 is a diagram illustrating Plug and Play operating states and corresponding commands;

FIG. 12A is a diagram of the bitfields of the Plug & Play Address-Register at microcontroller Address 0x10;

FIG. 12B is a diagram of the bitfields of the Plug & Play Write_Data_Port at microcontroller Address 0x11;

FIG. 12C is a diagram of the bitfields of the Plug & Play Read_Data_Register at microcontroller Address 0x12;

FIG. 12D is a diagram of the bitfields of the Plug & Play State Register at microcontroller Address 0x13;

FIG. 12E is a diagram of the bitfields of the Plug & Play Control/Status register at microcontroller Address 0x14;

FIG. 12F is a diagram of the bitfields of the Sound System Base Address Low at microcontroller Address 0x15;

FIG. 12G is a diagram of the bitfields of the Sound System Base Address High register at microcontroller Address 0x16;

FIG. 12H is a diagram of the bitfields of the Control Base Address Low register at microcontroller Address 0x17;

FIG. 12I is a diagram of the bitfields of the Control Base Address High register at microcontroller Address 0x18;

FIG. 12J is a diagram of the bitfields of the Sound Blaster Base Address Low register at microcontroller Address 0x19;

FIG. 12K is a diagram of the bitfields of the Sound Blaster Base Address High register at microcontroller Address 0x1A;

FIG. 12L is a diagram of the bitfields of the Synthesizer Base Address Low register at microcontroller Address 0x1B;

FIG. 12M is a diagram of the bitfields of the Synthesizer Base Address High register at microcontroller Address 0x1C;

FIG. 12N is a diagram of the bitfields of the MPU-401 Base Address Low register at microcontroller Address 0x1D;

FIG. 12O is a diagram of the bitfields of the MPU-401 Base Address High register at microcontroller Address 0x1E;

FIG. 12P is a diagram of the bitfields of the Game Port Base Address Low register at microcontroller Address 0x1F;

FIG. 12Q is a diagram of the bitfields of the Game Port Base Address High register at microcontroller Address 0x20;

FIG. 12R is a diagram of the bitfields of the CDROM Base Address Low register at microcontroller Address 0x21;

FIG. 12S is a diagram of the bitfields of the CDROM Base Address High register at microcontroller Address 0x22;

FIG. 12T is a diagram of the bitfields of the Synthesizer Interrupt Select register at microcontroller Address 0x23;

FIG. 12U is a diagram of the bitfields of the Sound Blaster Interrupt Select register at microcontroller Address 0x24;

FIG. 12V is a diagram of the bitfields of the Sound System Interrupt Select register at microcontroller Address 0x25;

FIG. 12W is a diagram of the bitfields of the MPU-401 Interrupt Select register at microcontroller Address 0x26;

FIG. 12X is a diagram of the bitfields of the CDROM Interrupt Select register at microcontroller Address 0x27;

FIG. 12Y is a diagram of the bitfields of the Control Interrupt Select register at microcontroller Address 0x28;

FIG. 13 is a diagram defining the Plug and Play Port;

FIG. 14A is a diagram of the bitfields of the Sound Blaster DMA Channel Select registers at microcontroller address 0x29;

FIG. 14B is a diagram of the bitfields of the Sound System Playback/Capture DMA Channel Select registers at microcontroller address 0x2A;

FIG. 14C is a diagram of the bitfields of the Sound System Capture DMA Channel Select register at microcontroller address 0x2;

FIG. 14D is a diagram of the bitfields of the CDROM DMA Channel Select register at microcontroller Address 0x2C;

FIG. 15A is a diagram of the bitfields of the Alternate CDROM Base Address Low register at microcontroller Address 0x2D;

FIG. 15B is a diagram of the bitfields of the Alternate CDROM Base Address High registers at microcontroller Address 0x2E;

FIG. 15C is a diagram of the bitfields of the Physical Device Activation Register at microcontroller Address 0x2F;

FIG. 15D is a diagram of the bitfields of the Modem Base Address Low register at microcontroller Address 0x30;

FIG. 15E is a diagram of the bitfields of the Modem Base Address High register at microcontroller Address 0x30;

FIG. 15F is a diagram of the bitfields of the Alternate CDROM Mask Register at microcontroller Address 0x32;

FIG. 15G is a diagram of the bitfields of the Modem Mask Register at microcontroller Address 0x33;

FIG. 15H is a diagram of the bitfields of the Miscellaneous Control Bits register at microcontroller Address 0x34;

FIG. 15I is a diagram of the bitfields of the Modem Interrupt Select register at microcontroller Address 0x35;

FIG. 15J is a diagram of the bitfields of the Physical Device Activity Register at microcontroller address=0x36;

FIG. 16 is a diagram of the bitfields of the Wavetable and Serial Control Register at microcontroller address 0x40;

FIG. 17 is a diagram of the bitfields of the reserved register at address 0x41;

FIG. 18 is a diagram of the bitfields of the Port 3 Shadow Register at microcontroller address 0x42;

FIG. 19 is a diagram emphasizing the circuitry of the EEPROM interface;

FIG. 20 is a diagram which depicts a flow chart of a detect/load EEPROM sequence;

FIG. 21A is a diagram which depicts the fields o:f address mask register/alternate CDROM base address register (Byte 4);

FIG. 21B is a diagram which depicts the bitfields of Address Mask Register Modem (Byte 5);

FIG. 21C is a diagram which depicts the Miscellaneous Configuration Bits, Byte 6;

FIG. 21D is a diagram which defines the bitfields of the Misc Configuration Bits, Byte 7;

FIG. 21E is a diagram which depicts the Global Configuration, Byte 8 and is copied to 0x4003 on powerup;

FIG. 22A is a diagram which illustrates the timing relationship between the clock and data;

FIG. 22B is a diagram which depicts an EEPROM device read access;

FIG. 23 is a diagram of the Plug and Play interface;

FIG. 24A is a diagram of the bitfields of ISA DATA READ/MIXER LATCH register at microcontroller address 0x00;

FIG. 24B is a diagram of the bitfields of the Sound Blaster Data Latch register at microcontroller address 0x01;

FIG. 24C is a diagram of the bitfields of the MPU-401 Receive Data Latch at microcontroller address 0x02;

FIG. 24D is a diagram of the bitfields of the STATUS REGISTER at microcontroller Address 0x03;

FIG. 24E is a diagram of the Reserved Registers at microcontroller Addresses 0x04 through 0x07;

FIG. 24F is a diagram of the bitfields of the Reset Sound Blaster Busy 2 at microcontroller Address 0x08;

FIG. 24G is a diagram of the bitfields of the Reset Sound Blaster Busy 2 register at microcontroller address 0x00;

FIG. 24I is a diagram of the bitfields of the Sound Blaster ADPCM Data Latch at microcontroller Address 0xC;

FIG. 24J is a diagram of the bitfields of Set Sound Blaster Busy 1 at microcontroller Address MD;

FIG. 24K is a diagram of the bitfields of the Sound Blaster DMA Request Register at microcontroller Address ME which is in response to a write of a DMA command to the Sound Blaster Command Register;

FIG. 24L is a diagram of the bitfields of the Sound Blaster Interrupt Request Register at microcontroller Address 0x0F;

FIG. 25A is a diagram of the bitfields of the Miscellaneous Control Register (at control base +0);

FIG. 25B is a diagram of the bitfields of the Hardware Control Register;

FIG. 25C is a diagram of the bitfields of the Power Down Control Register;

FIG. 25D is a diagram of the bitfields of the bitfields of the Control Address/Index Register;

FIG. 25E is a diagram of the bitfields of the Control Data Register;

FIG. 25F is a diagram of the bitfields of the Command Register;

FIG. 25G is a diagram of the bitfields of the Program RAM Access End Register;

FIG. 25H is a diagram of the bitfields of the Status Register;

FIG. 25I is a diagram of the bitfields of the Miscellaneous Control register;

FIG. 25J is a diagram of the bitfields of the Version/ID at Control Index register;

FIG. 25K is a diagram of the bitfields of SRS Control Register;

FIG. 25L is a diagram of the bitfields of 3D Sound Control Register;

FIG. 25M is a diagram of the bitfields of the S/PDIF Control Register;

FIG. 25N is a diagram of the bitfields of the S/PDIF Channel Status Data register;

FIG. 25O is a diagram of the bitfields of the S/PDIF Channel Status Data register 1;

FIG. 25P is a diagram of the bitfields of the FAB Port ID register;

FIG. 25Q is a diagram of the bitfields of the Wavetable and Serial Port register;

FIG. 25R is a diagram of the bitfields of the Left Output Master Volume register;

FIG. 25S is a diagram of the bitfields of the Right Output Master Volume;

FIG. 26 is a diagram emphasizing the Codec Interface;

FIG. 27A is a diagram of the bitfields Index Address Register;

FIG. 27B is a diagram of the bitfields of Indexed Data Register;

FIG. 27C is a diagram of the bitfields of Status Register;

FIG. 27D is a diagram of the bitfields of Capture I/O Data Register;

FIG. 27E is a diagram of the bitfields of Playback I/O Data Register;

FIG. 27F is a diagram of the bitfields of Left ADC Input Control Register;

FIG. 27G is a diagram of the bitfields of Right ADC Input Control register;

FIG. 27H is a diagram of the bitfields of Left Auxiliary #1 Input Control Register;

FIG. 27I is a diagram of the bitfields of Right Auxiliary #1 Input Control Register;

FIG. 27J is a diagram of the bitfields of Left Auxiliary #2 Input Control Register;

FIG. 27K is a diagram of the bitfields of the Right Auxiliary #2 Input Control Register;

FIG. 27L is a diagram of the bitfields of Left DAC Output Control Register;

FIG. 27M is a diagram of the bitfields of Right DAC Output Control Register;

FIG. 27N is a diagram of the bitfields of Fs and Playback Data Format Register;

FIG. 27O is a diagram of the bitfields of Interface Configuration Register;

FIG. 27P is a diagram of the bitfields of the Pin Control Register;

FIG. 27Q is a diagram of the bitfields of the Error Status and Initialization Register;

FIG. 27R is a diagram of the bitfields of ODE and ID Register;

FIG. 27S is a diagram of the bitfields of Loopback Control Register;

FIG. 27T is a diagram of the bitfields of Playback Upper Base Register;

FIG. 27U is a diagram of the bitfields of Playback Lower Base Register;

FIG. 27V is a diagram of the bitfields of Alternate Feature Enable I Register;

FIG. 27W is a diagram of the bitfields of Alternate Feature Enable II Register;

FIG. 27X is a diagram of the bitfields of Left Line Input Control Register;

FIG. 27Y is a diagram of the bitfields of Right Line Input Control Register;

FIG. 27Z is a diagram of the bitfields of Timer Lower Base Register;

FIG. 27AA is a diagram of the bitfields of Timer Upper Base Register;

FIG. 27AB is a diagram of the bitfields of Alternate Sample Frequency Select Register;

FIG. 27AC is a diagram of the bitfields of Alternate Feature Enable III Register;

FIG. 27AD is a diagram of the bitfields of Alternate Feature Status Register;

FIG. 27AE is a diagram of the bitfields of Mono Input and Output Control Register;

FIG. 27AF is a diagram of the bitfields of Left Output Attenuation Register;

FIG. 27AG is a diagram of the bitfields of Capture Data Format Register;

FIG. 27AH is a diagram of the bitfields of the Right Output Attenuation Register;

FIG. 27AI is a diagram of the bitfields of Capture Upper Base Register;

FIG. 27AJ is a diagram of the bitfields of the Capture Lower Base Register;

FIG. 27AK is a diagram of the bitfields of the Left Alternate FM Input Control Register;

FIG. 27AL is a diagram of the bitfields of the Right Alternate FM Input Control Register;

FIG. 27AM is a diagram of the bitfields of the Left Mic Input Control Register;

FIG. 27AN is a diagram of the bitfields of the Right Mic Input Control Register;

FIG. 27AO is a diagram of the bitfields of Control Register;

FIG. 27AP is a diagram of the bitfields of Control Register;

FIG. 27AQ is a diagram of the bitfields of the Left FM Volume Control Register;

FIG. 27AR is a diagram of the bitfields of Right FM Volume Control Register;

FIG. 27AS is a diagram of the bitfields of Left DSP Serial Port Volume Control Register;

FIG. 27AT is a diagram of the bitfields of Right DSP Serial Port Volume Control Register;

FIG. 27AU is a diagram of the bitfields of Right Digital Loopback Volume Control Register;

FIG. 27AV is a diagram of the bitfields of DAC, SRC Control Register;

FIG. 27AW is a diagram of the bitfields of Capture Sample Rate Control Register;

FIG. 27AX is a diagram of the bitfields of Playback Sample Rate Control Register;

FIG. 27AY is a diagram of the bitfields of Left PCM Audio Volume Control Register;

FIG. 27AZ is a diagram of the bitfields of the Right PCM Audio Volume Control Register;

FIG. 27BA is a diagram of the bitfields of the Left Wavetable Volume Control Register;

FIG. 27BB is a diagram of the bitfields of Right Volume Control Register;

FIG. 28 is a diagram illustrating the timing of context switch mechanism;

FIG. 29 is a diagram of the External Peripheral Port;

FIGS. 30A and 30B are diagrams illustrating exemplary read/write operations through the external peripheral port:

FIG. 31 illustrated the synthesizer and CDROM interface;

FIG. 32 emphasizes the clocking scheme for the device

FIG. 33 is a diagram of the Game Port which provides an interface to a standard personal computer type joystick;

FIG. 34 is a diagram illustrating the speed control variation;

FIG. 35 is a timing diagram illustrating the joystick port timing;

FIG. 36A is a diagram of the Joystick control circuitry;

FIG. 36B is a diagram of the Joystick Digital Assist circuitry;

FIG. 37A is a diagram of the bitfields of the Digital Assist Control/Status Register;

FIG. 37B is a diagram of the bitfields of Joystick Trigger/X1 Position Data Low Byte;

FIG. 37C is a diagram of the bitfields of the X1 Position Data High Byte;

FIG. 37D is a diagram of the bitfields of the Y1 Position Data Low Byte;

FIG. 37E is a diagram of the bitfields of the Y1 Position Data High Byte;

FIG. 37F is a diagram of the bitfields of the X2 Position Data Low Byte;

FIG. 37G is a diagram of the bitfields of the X2 Position Data High Byte;

FIG. 37H is a diagram of the bitfields of the Y2 Position Data Low Byte;

FIG. 37I is a diagram of the bitfields of the Y2 Position Data High Byte;

FIG. 38 is an additional timing diagram illustrating the operation of joystick interface;

FIG. 39 is a diagram of one channel of the input mixer (the second channel is identical);

FIG. 40 is a diagram of one channel of the output. mixer (the second channel is also identical);

FIG. 41 is a diagram of the mono audio channel;

FIG. 42 is a diagram of the digital audio processing subsystem;

FIG. 43 is a diagram of the digital audio mixer;

FIG. 44 is a diagram illustrating the attenuation scheme for the Digital to Analog Converter Volume Control;

FIG. 45 is a more detailed diagram of the FM synthesis block 124;

FIG. 46A is a diagram of the bitfields of the Status Register;

FIG. 46B is a diagram of the bitfields of the Test Register;

FIG. 46C is a diagram of the bitfields of the Timer #1 Register;

FIG. 46D is a diagram of the bitfields of the Timer #2 Register;

FIG. 46E is a diagram of the bitfields of the Timer #1, #2 Control Register;

FIG. 46F is a diagram of the bitfields of the 4-Operator Mode Register

FIG. 46G is a diagram of the bitfields of the Expansion Register;

FIG. 46H is a diagram of the bitfields of the Keyboard Split Register;

FIG. 46I is a diagram of the bitfields of the Power Management Register;

FIG. 46J is a diagram of the bitfields of the Tremolo Effect Register;

FIG. 46K is a diagram of the bitfields of the Vibrato Effect Register;

FIG. 46L is a diagram of the bitfields of the Non-percussive/Percussive Sound Register;

FIG. 46M is a diagram of the bitfields of the Rate Key Scale Register;

FIG. 46N is a diagram of the bitfields of the Frequency Multiplier Register;

FIG. 46O is a diagram of the bitfields of the Total Level Register;

FIG. 46P is a diagram of the bitfields of the Level Key Scale Register;

FIG. 46Q is a diagram of the bitfields of the Attack Rate

FIG. 46R is a diagram of the bitfields of the Decay Rate Register;

FIG. 46S is a diagram of the bitfields of the Release Rate Register;

FIG. 46T is a diagram of the bitfields of the Sustain Level Register;

FIG. 46U is a diagram of the bitfields of the F-Number Register;

FIG. 46V is a diagram of the bitfields of the Block;

FIG. 46W is a diagram of the bitfields of the Key On;

FIG. 46X is a diagram of the bitfields of the Rhythm;

FIG. 46Y is a diagram of the bitfields of the Rhythm Instrument Selection;

FIG. 46Z is a diagram of the bitfields of the Algorithm Selection;

FIG. 46AA are a diagram of the bitfields of the Feedback Modulation;

FIG. 46AB is a diagram of the bitfields of the Output Channel Selection;

FIG. 46AC is a diagram of the bitfields of the Register Settings;

FIG. 47 is a diagram representing the implementation of two audio processing algorithms;

FIG. 48 is a diagram representing the implementation of the algorithms in the 4 operator audio processing mode;

FIG. 49 is a functional block diagram of the stereo processor portion a selected DSP;

FIG. 50A is a diagram of the zero cross volume control circuitry;

FIG. 50B is a diagram showing further detail of the zero cross volume control circuitry of FIG. 50A;

FIG. 51 is a diagram of the hysteresis circuitry for power-on of the VCO;

FIG. 52A is a diagram of the bitfields of the SRS Control Register;

FIG. 52B is a diagram of the bitfields of the 3D Sound Control at Control Index Register;

FIG. 53 is a diagram depicting the operation of the serial port during mode 1;

FIG. 54 is a diagram depicting the operation of the serial port during mode 2;

FIG. 55 is a diagram depicting the operation of the serial port during mode 3;

FIG. 56 is a diagram depicting the operation of the serial port during mode 4;

FIG. 57 is a diagram illustrating a typical block/frame for S/PDIF data;

FIG. 58 is a diagram of the typical serial subframe;

FIG. 59 is a diagram of the coupling between the Codec and a wavetable synthesizer;

FIG. 60 is a diagram of the timing of the exchange of data between the codec and the wavetable synthesizer;

FIG. 61 is a test bit chart describing this mode;

FIG. 62 is a diagram of microcontroller memory map in Test Mode;

FIG. 63 is a diagram of the pinout of the codec device;

FIG. 64A is a diagram of the external microphone circuit;

FIG. 64B is a diagram of an example of a phantom, power microphone circuit;

FIG. 65 is a diagram of a circuit that may be used to drive the Line Out and Headphones;

FIG. 66 is a diagram of an alternate mixer section 6400;

FIG. 67A is a diagram of the control register holding the Version and ID bets in an alternate embodiment;

FIG. 68 is a diagram of the bitfields of the FAB Port ID Register in alternate embodiments;

FIG. 69A is a diagram of the bitfields of the Command Register in alternate embodiments;

FIG. 69B is a diagram of the bitfields of the Program RAM Access End Register in alternate embodiments;

FIG. 70 is a diagram of the PnP status register configuration when Crystal Key 2 is employed;

FIG. 71A is a diagram of the bitfields of the Miscellaneous Control Register in alternate embodiments;

FIG. 71B is a diagram of the bitfields of the Power Down Control Register 1 in alternate embodiments;

FIG. 71C is a diagram of the bitfields of Power Down Control Register 2 in alternate embodiments;

FIG. 72 is a diagram defining the register location for the watchdog timer status bit;

FIG. 73 is a diagram of the bitfields of the interrupt select register;

FIG. 74 is a diagram of the modem mask register in alternate embodiments;

FIG. 75A is a diagram of the analog stereo expansion circuitry in alternate embodiments;

FIG. 75B is a diagram illustrating the frequency response of the analog expansion circuitry of FIG. 75A;

FIGS. 75C and 75D are diagrams of the 3D Sound/Serial Interface Control and 3D Sound Control register, respectively;

FIG. 76 is a diagram representing the serial interface connection of an accelerator/ZVPORT with an alternate embodiment of the codec;

FIG. 77 shows the connection of wavetable synthesizer 134 with the alternate embodiment of the codec;

FIG. 78 is a diagram of the timing for the Internal SCLK Mode, where 16-Bit Data is shown;

FIGS. 79A and 79B and diagrams of the I2S data format;

FIG. 80 is a diagram illustrating the ZV Port Audio Interface timing;

FIG. 81 is a diagram emphasizing one digital audio path for the alternate embodiments;

FIG. 82 depicts the bitfields of the 3D Sound/Serial Interface Control Register;

FIGS. 83 and 84 are diagrams showing Codec registers I17 and I23 in the alternate embodiments;

FIG. 85 is a diagram of the modified codec register I26 in an alternative embodiment in which the mono support logic has been eliminated;

FIG. 86 is a diagram of a modified control register C18;

FIG. 87 is a diagram depicting miscellaneous control bits in alternate embodiments;

FIG. 88 is a diagram of the Global Status Register in alternate embodiments;

FIG. 89 is a diagram of the bitfields of the Global Configuration EEPROM Byte 2; and

FIG. 90 is a diagram of the bitfields of the DMA SP, iRQ EEPROM Byte.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in FIGS. 1-90 of the drawings, in which like numbers designate like parts. Unless otherwise noted, hexadecimal notation is indicated by 0x???? or ????. Byte ordering of words is—high byte, low byte.

FIG. 1A is a functional block diagram of an audio codec 100 according to the principles of the present invention.

The input and output of data and control signals between codec 100 and an external ISA bus is effectuated through an I/O bus interface 101. Configuration and control block within I/O bus interface 101 allows a host, via the ISA bus, to configure codec 100 for selected operating modes, and in particular those required by the Plug and Play standard. Additionally, interface 101 allows a host on the ISA bus to set-up I/O base addressing to codec 100, define the codec 100 to ISA bus interrupt mapping, and define the DMA channel mapping for the codec 100 memory space.

Along with a microcontroller 103, bus interface supports Plug & Play 1.0 as specified by Microsoft and Intel. In particular, Plug & Play is supported generally by the circuitry shown at 106. Circuitry 106 includes configuration and control block 102 discussed above, specific logic circuitry required for the interface 107, including the codec register interface 107 and decoder 108. Circuitry 107 and 108 allow the host to configure codec operations such as the input and output mixing functions.

Microcontroller 103, which includes an Intel™ 8052 core 10 Kbytes of ROM and 1 Kbyte of RAM, also supports the Sound Blaster and MPU-401 standards. MPU-401 standard data interfaces with microcontroller 103 through dedicated interface 104 and port MIDI. For example, data may be exchanged between port MIDI and microcontroller 103 using the 8052 UART standard protocol. Interface 104 also includes logic circuitry required for hardware handshaking of data to and from microcontroller 103 and the ISA bus.

Joystick logic block 105 includes a timer-like interface to the joystick port. External Peripheral EPROM block 109 provides general purpose 8-bit data path control for interfacing to external devices such as a CDROM, modem, or synthesizer chip utilizing /XIOW, /XIOR, ><7:0>, XA <2:0>+/BRESET ports.

The codec portion of codec 100 includes digital to analog converters which convert to analog form digital data such serial audio data received through the SERIAL PORT, parallel sound data received through data port SD<7:0> to interface 101, or synthesizer data generated on chip by an FM synthesizer (discussed below).

The Codec functionality is based on D/A converters 110 and A/D converters 111 utilizing switch-capacitor filter a delta sigma modulator, respectively. The sampling frequency at which the A/D and D/A converters (111 and 110) operate is fixed at 44.1 kHz. The delta-sigma modulator for the A/D conversion is implemented with a third order algorithm. The filter for the D/A conversions is a second order switched capacitor filter, with 128 FS oversampling.

Prior to digital to analog conversion by DACs 118, Sample Rate Converters 112 convert the digital interface sampling rate of the data received from the ISA bus (normally 5.51 kHz to 50.4 kHz) to 44.1 kHz at the inputs to D/A converters 110.

Similarly, analog data from the mixer function, also described below undergo reverse sample rate conversion. Sample Rate Converters 113 convert the output sampling rate from A/D converters 111 from 44.1 kHz to between 5.51 kHz to 50.4 kHz for output to the ISA bus. Only one 16.9344 MHz clock is needed with this Sample Rate Conversion scheme. Independent sample rates for the A/D and D/A converters is also supported.

The Mixer functionality is implemented with 6-channel INPUT Mixers 114 a and 114 b and 6-channel OUTPUT Mixers 115 a and 115 b. The input mixer allows data output from DACs 110 to be mixed with direct audio data, the mixed signal eventually re-converted for delivery to the ISA bus. The output data function allows for selective mixing of the data output from DACs 110 with analog sound data received directly from line in left and right (LLINE, RLINE), the auxiliary lines (LAUX, RAUX and LAUX2, LAUX1) or the microphone line (MIC). Output from the output mixer function is output directly through left, right and middle lines out (LOUT, ROUT, MOUT). The AUX2 input which is typically used for CD-ROM, features a differential input to eliminate ground loop noise. The Microphone stereo inputs can also be configured as mono differential inputs.

An FM Synthesis Engine 124 is also provided. The digital output of FM Synthesis Engine 124 is converted to analog by the Codec function, described above.

Joystick logic block 105 implements a standard interface to two joysticks. The second joystick pins are dual function in that the pins may be switched over to support Serial Port Interface 117. Special Digital Assist hardware has also been included to eliminate the need for the Host to poll the joystick data.

Audio Codec 100 incorporates DSP engine 118 to implement the industry SRS “3D” and QSound “3D” Stereo audio algorithms.

As will be discussed further below, data is input to and output from the mixing function through first-In-First-Out registers (queue) 121. Circuitry 120 allows for standard μlaw, A-law and ADPCM linear processing on both data being input to DACs 110 and output from A to D converters 111.

Synthesis interface 123 allows codec 100 to interface with an external conventional wavetable synthesizer. Sound Blaster (SB) and Windows Sound system (WSS) registers are generally shown at 127 and all discussed more fully below. Generally, these registers allow the host to set-up for industry sound protocols such as Sound Blaster and Microsoft Windows Sound System.

S/PDIF circuitry 119 supports digital data output from Serial Port formatted to the Sony Phillips Digital Interface Format. S/PDIF data can be input directly for transfer to the ISA bus, via sample rate converters 113 or sent to the mixer functions through DACs 110, through serial port 117 discussed above.

FIG. 1B is a diagram of one of a number of possible system applications for codec 100. In this case an audio accelerator 125, such as a Crystal Semiconductor CS461x audio accelerator, receives and accelerates audio from a PCI bus 126. Accelerator 125 also provides in this example a direct interface for SPDIF and/or I2S formatted audio data. Accelerator 125 exchanges data with codec 100 through a Legacy link 127. The accelerator interface of codec 100 will be discussed in detail below.

Codec 100 receives data, such as Plug & Play audio data, directly from an ISA bus 128. This data, as well as any internally generated FM synthesizer data, are passed on to the analog mixing and codec functions of codec 100. These functions also directly interface with such external devices as a joystick, MIDI source, CD player, microphone or external speakers. As discussed below, codec 100 also has provisions for interfacing with an external wavetable synthesizer.

FIG. 2 is a diagram providing a general overview of the bus structure and principle registers of Codec 100. Codec 100 is based upon three buses: bus 201 (the E_BUS); bus 202 (the I_BUS); and bus 203.

In FIG. 2, the codec functionality is generally shown at 204. Codec 204 is associated with Codec registers 205. Microcontroller 103 is associated with microprocessor written registers 206, which also store miscellaneous status bits. Registers 207 are the ISA bus written registers and also store miscellaneous status bits.

The control base and three indirect registers are shown generally at 208. Generally shown at 209 are the C8 register and digital joystick registers.

FIG. 3 is a functional block diagram of microcontroller core 103. Microcontroller core 103 is based on the Intel™ 8052 microcontroller. Core 103 is used in conjunction with 10 Kbytes of external ROM 301 and 1 Kbytes of external RAM 302.

The timing bases from which microcontroller 103 operates are established from external clocks by clock generation circuitry 303 and timing and control circuitry 304. Interrupts are timed by interrupt serial port timers within NSFR registers/timers 305.

Set bar registers/timers 305 also support two 8-bit I/O ports SFRAB and SFRDB.

In addition to the external memory, microcontroller 103 also includes two 56-bytes of random access memory (RAM) 306.

The instruction control and processing portion of core 103 includes instruction register 307, DPT register 308, program counter 309, program counter incrementor 310, buffer 311, program address register 312, stack pointer 313 and B register 314.

The data processing portion of core 103 includes an accumulator 315, temporary storage registers 316 a and 316 b, and ALU 317 and PSW circuitry 318.

I/O interface 319 allows process microcontroller 103 to communicate with ISA interface 101, external ROM 301 and external RAM 302.

Core 103 operates on a 2-phase non-overlap clock with an effective clock rate of 33.8688 MHz (2×16.9344 MHz) or 32.768 MHz (2×24.576/1.5). Core 103 and Codec functions are synchronized to minimize noise generation. The clock is generated by clock generation circuitry 303 from either the 16.9344 MHz or the 24.567 MHz crystal depending on the currently defined sample rate (oscillator 120, FIG. 1). In order to minimize clock switching disturbances, the microcontroller clock is set equal to the 16.9344 MHz crystal frequency or the 24.576 MHz crystal frequency divided by 1.5 (16.384 MHz).

Clock generator circuitry 303 and timing and control circuitry also provide a second timer (“Timer2”) for MIDI baud rate generation. The MIDI baud rate is defined as 31.25 kHz+/−1%. Hence, the frequency variation of the microprocessor clock, as different crystals are selected, violates the MIDI baud rate specification. Therefore the 16.9344 MHz crystal is always used as the clock input to Timer 2. This requires that the 16.9344 MHz crystal must always be running when MIDI is in use and the Timer 2 clock must be input on the external timer input pin (EXTCLK 2). Because microcontroller 103 samples the timer 2 clock input with a clock that is {fraction (1/12)} of the processor clock, the 16.9344 MHz crystal is divided by 17 and fed to the timer 2 input. Timer 2 is then used to perform a divide by 32 to obtain the proper MIDI baud rate. 16.9344 MHz/(32* 17)=31129 kHz which is within the +/−1% specification.

FIG. 4 is a diagram of the microcontroller 103 memory map. As shown in FIG. 4, microcontroller 103 includes three separate memory spaces as follows: ROM, Internal RAM, and External RAM.

10 Kbytes of the microcontroller 103 64 Kbyte ROM space (at addresses 0000H to 27FFH) is used to store the program code for microcontroller 103. After power-on reset microcontroller 103 will start executing instructions from location 0000H.

PnP Serial ID is reported to the host during a PnP ISOLATION operation, discussed below, and is dependent on the following: Whether a Honst Load with PNP_UPDATE command has occurred or an EEPROM is present at Port 109, the resource data sent to the part via a Host Load (host shoot) or EEPROM, or the value seen in register I25 by the Codec 100. A default PNP Serial ID in ROM 301 identifies, among other things, the vendor port number, vendor ROM ID number, program code version and ROM resident LSFR.

A default ROM image of PnP data including the default PnP serial ID is copied from ROM 301 to RAM 302 at powerup, before an external EEPROM coupled to port 109 is detected. The image in RAM 302 is used as the operating program code. If no EEPROM is present on port 109 and no host resource shoot has been performed, the PnP resource data that was copied from ROM to RAM is used. Specifically, the PnP serial ID copied from ROM is used if no EEPROM is present or no host resource shoot has taken place.

The Default ROM PnP Image is defined in TABLE 1:

TABLE 1
CODE
ADDRESSES DEFINITION
000H Address Mask -
CDROM
003H Address Mask -
Modem
080H Misc Config bits
000H Codec 100 Config
bits
00BH Codec 100 Family
byte
020H Reserved
004H Reserved
008H Reserved
010H Reserved
080H Reserved
000H Reserved
000H Reserved
000H 00=4/08=8
Peripheral port
size, XCTL0/XA2
048H LINE, AUX1, AUX2
mapping -
RESERVED
075H IRQ selection A &
B - B- 7, A=5
0B9H IRQ selection C &
0 - D-11, C=9
0FCH IRQ selection E &
F - F-15, E=12
010H DMA selection A &
B - B- 1, A=0
003H DMA selection C-
C=3
00EH 063H 042H ROM_CRY_ID:
036H 0FFH 0FFH 0FFH 0FFH ROM_RES_ID:
0A9H ROM_RES_LSFR:
00AH 010H 003H PnP version X,
Vendor version Y
082H 00EH 000H Vendor Name Codec
ID ANSI ID

If an EEPROM is detected, the EEPROM resource data is copied over the default ROM image in RAM. Firmware then examines the EEPROM serial ID (in RAM) for the 0x0E, 0x63 Vendor EISA ID in the first two serial ID bytes. If these two bytes are not found, the RAM serial ID remains the same as the EEPROM serial ID.

If the first two bytes of EEPROM serial ID are 0x0E, 0x63, then the contents of register I25, which changes based on Bond Out, is used to determine the ‘Vendor Part ID’ portion of the PnP serial ID.

For a host resource shoot followed by a PNP_UPDATE command, the serial ID is examined for a 0x0E, 0x63 in the first two bytes. As in the EEPROM case, if these two byte are, not found, the RAM serial ID (host shoot) remains unchanged.

If the first two bytes of the host shoot serial ID are 0x0E, 0x63, then the contents of register I25 are used to determine the ‘Vendor Part ID’ portion of the PnP serial ID. The serial ID is examined and changed if necessary during the PNP-UPDATE command.

If the firmware causes an update the PnP Serial ID based on the criterion above, I25 will be read and the table scanned for a matching value in the lower five bits. If no match is found, no change will be made. If a match is found, the Vendor Part ID will be replaced with the table value, the OEM ID and serial number are preserved and a new LSFR checksum is calculated.

To facilitate segregation of EEPROM based code shoots among the various past and future pin compatible devices, a ‘Family Byte’ has been created/defined. If the EEPROM supplied Family Byte does not match the ROM expected value, the EEPROM firmware RAM patch will be ignored. The resource data, however, will be loaded normally. This byte allows the firmware to ignore patch code intended for a different release when the EEPROM has not been updated.

EEPROM Hardware configuration byte 9, RAM location 0x4004, is used by the firmware to match EEPROM code shoots to ROM firmware releases. This byte is compared to a stored ROM value for a given ROM release. If the bytes do not match, the EEPROM image load is terminated by the firmware at 0x417F, after the resource data (0x417F is the top of resource data and 0x4190 is the beginning of the firmware RAM patch table).

Support for a Digitally Assisted Joystick is included in the firmware. This feature will be discussed further below with regards to the detailed description of the Game Port. A set of commands issued by the Host which initiates actions to be taken by the microcontroller 103. The Host port is through joystick base+7, but the ROM firmware will mirror this port at joystick base+6.

Codec 100 includes a set of defined pins (Up, Down, Mute) which may be used with external switches to control the overall audio level driven out the line outputs. Microcontroller 103 is used in conjunction with Master Volume control registers I27A and I29A 205. The Master Volume Control provides a dynamic Range of +12 dB to −36 dB. The Master Volume Control will be discussed in detail in conjunction with the Codec Interface.

The firmware revision bytes are used by the host to identify which patch is present in the part and what patch options are set.

The Features Byte/REVISION Byte at 0x41BF indicates major feature sets of the embedded microcode. Each bit in this byte represents a feature or feature set. This byte is written 0x22 on powerup. This byte definition changes definition with each chip family.

The Firmware Revision Number Byte indicates the current revision of the embedded microcode patch.

FIG. 5 is a more detailed diagram of the mapping of the program RAM spacing within RAM 302. In view of FIG. 5, the program RAM of Codec 100 can now be discussed in detail.

In addition to the ROM memory 301, 1.5 Kbytes of Program RAM 302 are included for microcontroller code changes and as a storage area for Plug and Play configuration data. Because microcontroller 103 instructions may only be executed from ROM addressable memory (read only), the Program RAM is mapped into the microcontroller 103 ROM 301 address space. In order to allow the Program RAM to be written via microcontroller 103, the Program RAM is directly mapped into the microcontroller 103 external RAM memory space. In this way the Program RAM may be accessed (read/write) via microcontroller 103 MOVX instructions as well as read during ROM instruction fetches. In this way code changes may be made via the ISA Interface by loading new code into the Program (Instruction) RAM area and then changing the subroutine vector location to correspond to the new code location.

On power-up the microcontroller 103 will load Codec 100 configuration data, Plug-n-Play resource data, and RAM patch code, from external EEPROM into the Program RAM. The data stored in the Program RAM is then used to configure Codec 100 internal hardware.

The fact that the configuration and resource requirements are determined via data that is stored in Program RAM allows the configuration and resource signature of Codec 100 to modified by the host. The host downloads updated configuration and resource data through the Codec 100BA RAM Access Register, discussed further below.

The method by which the Program RAM is accessed by the microcontroller 103 is defined as follows. Strategically placed within the ROM code are a set of instructions. These instructions cause the microcontroller 103 to store an identifier in microcontroller 103 register R7 and a subroutine CALL to address 0x41C0 is made. Address 0x41C0 is located in the Program RAM patch area. Once the CALL is made to 0x41C0, patch RAM routines may read microcontroller 103 register R7 to identify where in the ROM code that the CALL to address 0x41C0 was made. In this way ROM coded routines may be replaced or modified in function by Program RAM resident patch code.

To prevent accidental execution of invalid code, when loading the Program RAM via the host, the Program RAM must be loaded in segments. The very last segment must be a one byte load to address 0x41C0.

Multiple Patch RAM entry points from ROM in locations from 0x4190 to 0x41C0. Initialization code fills all these locations with a RET (0x22) instruction. At strategic points in the ROM code, these entry points are called with the mRAMx macro (macro RAM) where ‘x’ refers to the particular entry point.

The following is an example of an MRAM macro. These macros are placed in the code source to allow RAM based code changes.

mRAM2 MACRO
MOV R7, #RAMCOUNT 2 ; Token
passed to RAM
CALL RAM_ENTRY 2
RAMCOUNT2 SET RAMCOUNT2 +1 ; Add 1 to
token

Multiple CALLs can be made to the same mRAM entry point as each use of the particular mRAMx has a unique value in R7.

If patches have not been loaded, RAM locations 0x4190 through 0x41C0 will contain a 0x22. After a patch is loaded, addresses 0x41BD through 0x41BF contain Firmware Revision data and 0x41C0 will contain a value other than 0x22. Upon a RESET or SW RESET command, the region from 0x4190 to 0x41C0 will be filled with a RET (RAM entry) opcode (0x22). The RAM entry points are identified in TABLE 2. The CALLing points, scattered throughout the ROM, CALL RAM and return. Once a host based (or EEPROM) load image is written to RAM, the code effectively vectors to the patch code when the entry point is called. A JUMP_TO_ROM command is used before loading RAM via the control port to insure code is not loaded over code that is currently executing from RAM (from a previous load).

TABLE 2
Program RAM Address RAM Space Description
41C0 - 45FF PATCH AREA
41BF REVISION BYTE
41BE REVISION BYTE
41BD REVISION RESERVED
41BA mRAM2 ENTRY
41B7 mRAM3 ENTRY
41B4 mRAM4 ENTRY
41B1 mRAM5 ENTRY
41AE mRAM6 ENTRY
41AB mRAM7 ENTRY
41A8 mRAM8 ENTRY
41A5 mRAM9 ENTRY
41A2 mRAM10 ENTRY
419F mRAM11 ENTRY
419C mRAM12 ENTRY
4199 mRAM13 ENTRY
4196 mRAM14 ENTRY
4193 mRAM15 ENTRY
4190 mRAM16 ENTRY
4180 - 418F FREE
400C - 417F TOP OF RESOURCE DATA
4000 - 400B HARDWARE CONFIG DATA

Codec 100 will detect an existing configuration/code load sequence by identifying a RAM load starting at memory location 2090h. Codec 100 will then insure that configuration data is moved to the new RAM area. REVC Sound Blaster code is ignored. Pnp resource data RAM writes to address 2090h are captured by the Codec 100 and translated and written to address 400Ch for resource data compatibility.

The Program Ram is accessible from ISA Bus interface 101 via a Program RAM Access Register (Control_Base +5) and a Program RAM Access End Register (Control_Base +6), When either the Codec 100 Program RAM Access Register or Program RAM Access End Register is read or written by the ISA Bus, an interrupt is generated to the microcontroller 103. The microcontroller 103 reads the data and processes it. These registers locations are discussed below with regards to the Central Register.

Commands and data are written to a Program RAM Access Register. The data may be a command, command parameter data, or data to be loaded into RAM. The Codec 100 supports additional commands other than those specific to RAM access. The Program RAM Access End Register is used to terminate the command/data transfer sequence. Each Program RAM read or write sequence must be terminated with a write to the Program RAM Access End Register.

A command is executed by writing the command data value to the Program RAM Access Register. The available commands, which are also discussed in conjunction with the Control Register description, are as follows:

DISABLE_PNP,

DISABLE_CSC,

UPDATE PNP (0x5A),

RAM_LOAD (0xAA),

FINISH,

RESUME,

RAM_PTR_LOAD,

HOLD,

GO,

JUMP_TO_ROM,

SET_READ_ROM_FLAG,

SET_ACC_INT_FLAG.

A typical sequence to load the Program RAM is as follows:

1. The Codec 100 base I/O address is configured so that the Program Access Registers are accessible:

a. the host sends 32 byte “Key” sequence; and

b. the Codec 100 base I/O address is configured by the host writing the following 8-bytes to address 0x279: 0x15, 0x02, 0x47, 0x_base address high byte, 0x_base address low byte, 0x33, 0x01, 0x79.

2. The host downloads the data to Program RAM:

a. the host sends a RAM_LOAD command by writing a 0xAA to Codec 100 base address +5;

b. the host sends a starting download address (0x4000) by writing low byte starting RAM address (0x00) to Codec 100 base +5 and writing high byte starting RAM address (0x40) to Codec 100 base +5; and

c. the host downloads the data by writing successive bytes to Codec 100 base +5.

3. The host terminates Program RAM download by executing a write of 0x00 to Codec 100 address base +6.

4. The host instructs Codec 100 to update configuration by sending UPDATE_PNP command and writing 0x5A to Codec 100 base address +5.

The External microcontroller 103 RAM area is used for communication to devices external to microcontroller 103. This includes Sound Blaster/MPU-401/wavetable registers and the Program RAM. FIG. 5 emphasizes the interface between microcontroller 103 and external RAM 302 and Codec 100 external registers. The IOHAD[7:0] and XDBAL[7:0] address outputs from microcontroller 103 core are decoded with read/write (RD/WR) circuitry 501 to generate strobes and read enables. Additionally, XDBAL[5:0], and IOHAD[6] are decoded to generate device decodes for all microcontroller 103 externally accessible registers. Bits XDBAL[7:0], IOHAD[3:0], and IOHAD[6] are used in accessing the Program RAM. The XDB[7:0] output from microcontroller 103 core is a bi-directional data bus over which data flows between microcontroller 103 and external devices.

As noted above, in Codec 100 internal microcontroller 103 is used to support any number of functions. These include: PnP, Sound Blaster, MPU-401, and Control Port commands. Microcontroller 103 interrupt capability (Block 305, FIG. 3) is used to call microcontroller 103 when specific ISA Bus host accesses have occurred.

The INTO interrupt input to microcontroller 103 is used for the Plug-n-Play and Crystal Key. Microcontroller 103 INT1 interrupt is used for Sound Blaster, MPU-401, and Control Port commands. Timer interrupt TR0 is used for Sound Blaster ADPCM. (These signals are shown as inputs to block 305 of FIG. 3.)

Because microcontroller 103 requires on the order of 2 usec to respond to an interrupt, the interrupting ISA Bus access is held visa a signal IOCHRDY until microcontroller 103 acknowledges the interrupt request. The way in which microcontroller 103 acknowledges each interrupt is unique.

During Plug-n-Play sequences, the INT0 input to microcontroller 103 is forced active whenever a “Plug-n-Play Key” or “Vendor Key” is received.

In order for microcontroller 103 to be able to identify specific host accesses to Sound Blaster, MPU-401, and Control Ports, Port 1 of microcontroller 103 is used to specify an 8-bit Interrupt Identification byte, the bitfields of which are shown in FIG. 6 and described as follows:

SBD Sound Blaster data available bit.
LD1-LD0 Specify one of four logical devices.
(These logical devices are not related to
Plug-n-Play logical devices.)
A2-A0 ISA Bus address bits SA2, SA1, SA0
respectively.
R/W Indicates current ISA cycle type.
0=Write, 1=Read
SBW Sound Blaster write busy bit

TABLE 3 describes the interrupts for the Sound Blaster and Sound System modes (where INT0, INT1, and TRO are inputs to circuitry 305, FIG. 3):

TABLE 3
MODE OPERATION INPUT INTERRUPT BITFIELDS
Sound Context INTI X 1 1 0 0 0 0 X
System Switch Write
Context X 1 1 0 0 0 1 X
Switch Read
Reserved X 1 1 0 0 1 0 X
Reserved X 1 1 0 0 1 1 X
Reserved X 1 1 0 1 0 0 X
Reserved X 1 1 0 1 0 1 X
Reserved X 1 1 0 1 1 0 X
Reserved X 1 1 0 1 1 1 X
Sound Config Write X 1 1 1 0 0 0 X
Blaster Reserved X 1 1 1 0 0 1 X
Program RAM X 1 1 1 0 1 0 X
Write
Program RAM X 1 1 1 0 1 1 X
Read
Program RAM X 1 1 1 1 0 0 X
End
Reserved X 1 1 1 1 0 1 X
DMA Write X 1 1 1 1 1 0 X
Reserved X 1 1 1 1 1 1 X
Sound Interrupt TRO 0 0 0 0 0 0 0 0
Blaster occurs on a 0 0 0 0 0 0 1 0
ADPCM write of the
ADPCM data
latch.
Plug & Address Port INT0 Described below
Play 0x0279

When a ISA bus Sound Blaster ADPCM DMA write occurs, this interrupt is generated to microcontroller 103. Microcontroller 103 responds by reading the data from external microcontroller 103 address 0x0C.

Significant Sound Blaster performance gains are realized by mapping Codec registers 107 directly into microcontroller 103 SFR address space. This change allows microcontroller 103 independent access to the codec registers (i.e. mixer functions) while DMA data is transferred to and from the FIFO's (discussed later).

TABLE 4 specifies the mapping of codec registers into microcontroller 103 SFR address space. The codec register R0 is only implemented to support the MCE and TRD bits. All other bits in register R0 are don't cares. Codec registers R2 and R3 function normally.

TABLE 4
Codec
SFR Address Register Description
0xC0 I0  Left ADC Input Control
0xC1 I1  Right ADC Input Control
0xC2 I2  Left AUX 1 Input Control
0xC3 I3  Right AUX 1 Input Control
0xC4 I4  Left AUX 2 Input Control
0xC5 I5  Right AUX 2 Input Control
0xC6 I6  Left DAC Output Control
0xC7 I7  Right DAC Output Control
0xD8 I8  FS and Data Playback Format
0xD9 I9  Interface Configuration
0xDA I10 Pin Control
0xDB I11 Error Status and
Initialization
0xDC I12 Mode and ID
0xDD I13 Loopback Control
0xDE I14 Playback Upper Base
0xDF I15 Playback Lower Base
0xE8 I16 Alternate Feature Enable I
0xE9 I17 Alternate Feature Enable II
0xEA I18 Left Line Input Control
0xEB I19 Right Line Input Control
0xEC I20 Timer Lower Base
0xED I21 Timer Upper Base
0xEE I22 Alternate Sample Frequency
Select
0xEF I23 Alternate Feature Enable
III
0xF8 I24 Alternate Feature Status
0xF9 I25 Version/ID
0xFA I26 Mono Input and Output
Control
0xFB I27 Left Output Attenuation
0xF4 I28 Capture Data Format
0xF5 I29 Right Output Attenuation
0xF6 I30 Capture Upper Base
0xF7 I31 Capture Lower Base
0xE4 R0 Index Address Register
0xE5 R1 Index Data Register
0xE6 R2 Status Register
0xE7 R3 PIO Data Register

Codec 100 normally does not allow access to Codec registers 107 by the ISA Bus and microcontroller 103 at the same time. However in the case of Sound System operation with master volume control, Sound System accesses can occur simultaneously with microcontroller 103 access to the master volume control registers I27A and I29A (Codec Registers 205, FIG. 3). To address this problem a Request/Grant handshake mechanism has been developed. The timing is shown in the diagram of FIG. 7.

Two microcontroller 103 accessible bits are defined as a codec access REQUEST and GRANT. These bits are reset to zero via RESDRV and software reset via bits PM1, PM0. Microcontroller 103 sets the REQUEST bit to a one when it requires access to any codec register 205 (I27A, I29A) and when the Context Switch status is in Sound System mode. Once this bit is set the GRANT bit will be generated immediately if no ISA bus access to any codec register is in progress. Otherwise, if an ISA bus access to any codec register is in progress then the generation of GRANT will be delayed until the current ISA bus cycle has finished.

Once the GRANT bit is set, any further ISA Bus cycles to any codec registers are held off via the IOCHRDY signal. Microcontroller 103 is then free to access registers Codec 127A and 129A without contention with the ISA Bus codec register accesses. Once microcontroller 103 has finished its access, it clears the REQUEST bit. The clearing of the REQUEST bit also clears the GRANT bit which in turn releases IOCHRDY. The current ISA Bus codec access being held is then allowed to complete.

The REQUEST/GRANT bits are mapped into microcontroller 103 Port 3 register. For test purposes the bits available on Port 3 are also available at microcontroller 103 external address 0x42. All bits are read only except for the REQUEST bit which is read/write. The mapping of the Port 3 bits at microcontroller 103 external address of 0x42 allows external chip access via Test Mode 4 (discussed below). The function of these bits can thus be verified with and without microcontroller 103 operation.

Port 3 Bit Definitions are shown in FIG. 8 and can be described as follows:

P3.3—REQUEST—Read/Write.

This is set to a one when microcontroller 103 is updating codec registers and there is possible contention with ISA bus accesses (Sound System mode). After polling for GRANT=1, microcontroller 103 may access codec registers as needed. After microcontroller 103 has finished its codec accesses, the REQUEST bit should be set to zero to re-enable ISA access to the codec registers.

P3.4—GRANT—Read Only.

This bit is polled by microcontroller 103 after setting the REQUEST bit=1. When GRANT is equal to one, microcontroller 103 may access codec registers without contention with the ISA bus. When GRANT=1 and subsequent ISA codec accesses are held off via IOCHRDY until the REQUEST bit is set to zero by microcontroller 103.

In Codec 100, microcontroller 103 is used to perform and control a variety of functions. The microcontroller 103 controls these functions through a number of registers that are mapped into microcontroller 103 external memory space. These registers are shown generally at I27 FIG. 1. An external device memory map is provided in TABLE 5:

TABLE 5
Register Name Address Register Function Read/Write
Mixer Data Latch 0x00 Latches mixer data to ISA bus. Write
ISA Data Read 0x00 Read ISA Bus Data Read
Sound Blaster Data 0x01 Holds DSP Output Data to be Read/Write
Latch read by ISA bus. A read of
this address will cause the SB
Command busy1 bit to be
cleared.
MPU-401 Receive Data 0x02 Holds data to be read by ISA Read/Write
Latch bus. A read of this address
will cause the Transmit Buffer
Full Flag to be cleared.
STATUS 0x03 Current Status of Sound Blaster Read/Only
and MPU-401 Handshake bits.
Reserved 0x04
Reserved 0x05
Reserved 0x06
Reserved 0x07
SB Busy2 0x08 Reset Sound Blaster Busy2 Write
Reserved 0x09
Block Power Down 0x0A Individual Power Down Bits Read/Write
Codec 100 Control 0x0B CS4232 Control Base +1 Bits Read/Write
Sound Blaster ADPCM 0x0C SB ADPCM Data Read
Latch
SB Busy1 0x0D Set Sound Blaster Busy Bit Write
SB-DRQ Latch 0x0E Reset current pending Sound Read
Blaster DMA Request that was
set by a write to 8051 address
0x0E.
SB-DRQ Latch 0x0E Generate Sound Blaster DMA Write
Request and store data in
latch.
SB-INT 0x0F Generate Sound Blaster Write
Interrupt
Plug & Play Address 0x10 Stores data written to address Read Only
Register 0x279 from ISA bus.
Plug & Play Write_Data 0x11 Stores data written to address Read Only
Port 0xA79 from ISA bus.
Plug & Play Read_Data 0x12 Written by microcontroller 103 Write Only
Register in response to a read from the
Read_Data_Port address.
Plug & Play State 0x13 Defines current Plug & Play Write Only
state.
Plug & Play 0x14 Control/Status information Read/Write
Control/Status
I/O Base Address - 0x15 Lower 8 bits of address Write Only
Sound System
I/O Base Address - 0x16 Upper 4 bits of address Write Only
Sound System
I/O Base Address - 0x17 Lower 8 bits of address Write Only
Control
I/O Base Address - 0x18 Upper 4 bits of address Write Only
Control
I/O Base Address-Sound 0x19 Lower 8 bits of address Write Only
Blaster
I/O Base Address-Sound 0x1A Upper 2 bits of address Write Only
Blaster
I/O Base Address - 0x1B Lower 8 bits of address Write Only
Synth
I/O Base Address - 0x1C Upper 2 bits of address Write Only
Synth
I/O Base Address - 0x1D Lower 8 bits of address Write Only
MPU-401
I/O Base Address 0x1E Upper 2 bits of address Write Only
MPU-401
I/O Base Address - Game 0x1F Lower 8 bits of address Write Only
Port
I/O Base Address - Game 0x20 Upper 2 bits of address Write Only
Port
I/O Base Address 0x21 Lower 8 bits of address Write Only
0-CDROM
I/O Base Address 0x22 Upper 2 bits of address Write Only
0-CDROM
Interrupt Select - 0x23 Bits [3:0] Write Only
Synth
Interrupt Select - 0x24 Bits[3:0] Write Only
Sound Blaster
Interrupt Select - 0x25 Bits [3:0] Write Only
Sound System
Interrupt Select - 0x26 Bits [3:0] Write Only
MPU-401
Interrupt Select -CDROM 0x27 Bits [3:0] Write Only
Interrupt Select - 0x28 Bits [3:0] Write Only
Control
DMA Channel Select - 0x29 Bits [2:0] Write Only
Sound Blaster
DMA Channel Select - 0x2A Bits[2:0] Playback/Capture Write Only
Sound System
DMA Channel Select - 0x2B Bits [2:0] Capture Write Only
Sound System
DMA Channel Select - 0x2C Bits[2:0] Write Only
CDROM
I/O Base Address 1 - 0x2D Lower 8 bits of address Write Only
CDROM
I/O Base Address 1 - 0x2E Upper 2 bits of address Write Only
CDROM
Logical Device Activate 0x2F Activate logical device when Write Only
bit=1
I/O Base Address - 0x30 Lower 8 bits of address Write Only
Modem
I/O Base Address - 0x31 Upper 2 bits of address Write Only
Modem
Addreas Mask Register - 0x32 Mask used for programmable Write Only
CDROM address range
Address Mask Register - 0x33 Mask used for programmable Write Only
Modem address range
Misc. Hardware 0x34 Miscellaneous Hardware Control Write Only
Configuration Control Bits
Interrupt Select - 0x35 Bits [2:0] Write Only
Modem
Physical Device 0x36 For auto-power management Read Only
Activity
Digital Assist 0x37 Auto-Retrigger Enable/Joystick Read/Write
Control/Status Status
Joystick #1 X 0x38 Joystick Trigger/X Coordinate Read/Write
Coordinate Counter Low Byte
Joystick #1 X 0x39 X Coordinate Counter High Byte Read Only
Coordinate
Joystick #1 Y 0x3A X Coordinate Counter Low Byte Read Only
Coordinate
Joystick #1 Y 0x3B Y Coordinate Counter High Byte Read Only
Coordinate
Joystick #2 X 0x3C X Coordinate Counter High Byte Read Only
Coordinate
Joystick #2 X 0x3D X Coordinate Counter High Byte Read Only
Coordinate
Joystick #2 Y 0x3E X Coordinate Counter Low Byte Read Only
Coordinate
Joystick #2 Y 0x3F Y Coordinate Counter High Byte Read Only
Coordinate
Serial Port Control 0x40 Control for bach serial Read/Write
interface
Bond Out Override 0x41 Bond Out Override bits Read/Write
Port 3 Shadow 0x42 Shadow of Port 3 bits for test Read/Write
purposes
Program RAM 0x4000 1.5 Kbytes Program RAM Read/Write
0x45FF

FIG. 9 is a diagram providing an overview of the circuitry of Codec 100 supporting a Plug & Play (PnP) interface to external ISA bus 130. Included within ISA Interface 101 is an interface to microcontroller 103 core (including control logic 901, data buffer 902, and address latch 903), an interface to Codec 204, and configuration logic 904 that is Intel/Microsoft “Plug & Play” (PnP) compatible. ISA interface 101 also generally includes data buffers 905, circuitry 906 for generating signal IOCHRDY from wait state status information, DMA mapping logic 907 and Interrupt Mapping logic 908.

Codec 100 operates in conjunction with a number of other associated Plug & Play devices 909 also coupled to the ISA bus of independent blocks 909 that are mapped to the ISA Bus. Each block 909 has associated with it a set of resource requirements and associated configuration registers, organized into groups called physical devices. TABLE 6 below lists the maximum resource requirements for each physical device. The Intel/Microsoft Plug & Play specification organizes devices into logical groupings (logical devices) comprised of one or more physical devices.

TABLE 6
Physical Device
Device Name Maximum Resource Requirements
0 WSS Sound System 12-bit I/O Base Address
Decode
Two Sound System 8-bit DMA Channels
One Sound System Interrupt
1 Synth 10-bit I/O Base Address Decode
One-Interrupt
2 Control 12-bit I/O Base Address Decode
One Interrupt
3 MPU-401 10-bit I/O Base Address Decode
One Interrupt
4 CD-ROM 10-bit I/O Base Address Decode
10-bit I/O Alternate Base Address
Decode
One DMA Channel
One Interrupt
5 Game Port 10-bit I/O Base Address Decode
6 SB Pro Sound Blaster 10-bit I/O Base
Address Decode
DMA and Interrupt shared with WSS.
7 Modem 10-bit I/O Base Address Decode
One Interrupt

The Plug & Play Specification 1.0a describes a hardware and software mechanism whereby ISA cards are isolated, identified, and then optimally allocated within a system's resource environment. To be Plug & Play compatible, each interface to the ISA bus, such as ISA 10 Interface logic 101, must respond appropriately to a defined sequence of configuration commands. In Codec 100, microcontroller 103, in conjunction with logic is used to implement the various Plug & Play commands and responses. The end result of a Plug & Play configuration sequence is that the I/O base address decodes, DMA channel selects, and interrupt selects for the various Codec 100 circuit blocks are programmed to specific values.

FIG. 10 is a diagram emphasizing the configuration/interface logic for a PnP compatible device, for example Plug and Play Interface 106 of Codec 100. Configuration/interface 106 includes an address decoder 1001 which receives control bits and 12 address bits from the ISA bus, an address register 1002, linear feedback shift register 1003, plug and play (PnP) registers 1004, output enable circuitry 1005 and register output selector 1006. PnP registers include card control register 1004 a, logical device control register 1004 b and logical device configuration register 1004 c. The theory of Plug and Play operation can now be described in conjunction with FIG. 10A, and the associated functional diagram of FIG. 11, assuming Codec 100 is the PnP compatible device under configuration.

After a power-up sequence or hardware reset via RESDRV, Codec 100 is in the Wait_for_Key state. In this state Plug & Play devices monitor writes to address 0x279. Specifically, Linear Feedback Shift Register (LFSR) 1003 is used in hardware to detect a matching byte sequence. If at any time the data written to address 0x279 does not match the LFSR then the LFSR is reset. The cycle continues until an Initialization Key is received. Once the “Key” has been received, microcontroller 103 writes address 0x13 (the P&P State Register) to a 0x1 so that the configuration logic is now in the “Sleep State.”

FIG. 10B is a diagram generally illustrating the functional elements of LFSR 1003, including a series of storage/shift elements 1201 and logic 1202. LFSR 1003 also includes logic that enables an additional key sequence to be detected. This additional key sequence is referred to as the “Vendor Key”. This Key allows the Plug & Play logic to be bypassed so that Plug & Play configuration registers 1004 may be programmed directly.

Plug & Play Key Sequence

6A, B5, DA, ED, F6, FB, 7D, BE, DF, 6F, 37, 1B, 0D, 86, C3, 61 B0, 58, 2C, 16, 8B, 45, A2, D1, E8, 74, 3A, 9D, CE, E7, 73, 39

Vendor Key Sequence

96, 35, 9A, CD, E6, F3, 79, BC 5E, AF, 57, 2B, 15, 8A, C5, E2 F1, F8, 7C, 3E, 9F, 4F, 27, 13 09, 84, 42, A1, D0, 68, 34, 1A

In the Sleep State, a P&P device, such as circuitry 1904 waits for a Wake[CSN] command with write data set 0x00. All accesses to P&P registers 1004 in this state (0x279, 0xA79) cause the logic to force IOCHRDY low (hold current bus cycle) and set an appropriate bit in microcontroller Port 1. Once microcontroller 103 reads either address 0x10 or 0x11, the Port I bit is cleared and IOCHRDY is released. After the Wake[CSN] is detected microcontroller 103 sets a serial identifier/resource data pointer to the beginning and writes a 0x2 to microcontroller 103 address 0x13 to transition the logic to the Isolation State.

The first time Plug&Play device enters the Isolation State, the Read_Data port address is set using a Set_RD_DATA port command. Codec 100 hardware detects this command and latches the Read_Data port address into a register 2004C and uses it to decode accesses to the Read_Data port 901.

Next, 72 pairs of reads are performed to a PnP Serial Isolation register within registers 1004 c. The Serial Isolation register holds a 72-bit serial identifier. The 72-bit Serial Identifier is used in identifying and isolating individual Plug & Play devices. Microcontroller 103 uses the transition to the Isolation State to retrieve the first bit of the 72-bit serial identifier and writes this bit to microcontroller address 0x14 bit 0.

The isolation sequence proceeds as follows. If the current bit, of the 72-bit serial identifier, is a one then the logic forces a 0x55 onto the ISA data bus when Read Data port 910 is read. When Read_Data port 910 is read a second time, then the logic forces a 0xAA onto the ISA Data bus. After the Read_Data port is read the second time microcontroller 103 is notified via a bit to Port 1 and the next bit of the serial identifier is written to microcontroller 103 address 0x14 bit 0. This sequence continues until either the logic detects an isolation lose condition or all 72 bits have been read.

Otherwise, if the current bit is a zero, the configuration logic tri-states the ISA data bus buffer and monitors the data on the ISA data bus during a read of the Read_Data port 910. If the logic detects that another P&P device is driving the ISA data bus (i.e. detects a 0x55, 0xAA sequence) then the ILS (Isolation lose) bit is set in microcontroller 103 Command/Status register. Upon microcontroller 103 being notified of an Isolation lose the logic is then transitions back to the Sleep State (microcontroller 103 address 0x13=01).

If Codec 100 does not lose isolation during the current isolation sequence then a CSN (Card Select Number) is assigned by the PnP host software. The CSN is a unique value that is assigned to each isolated Plug & Play device. The CSN is used by the host to select individual Plug & Play devices during configuration. Microcontroller 103 stores this CSN in memory and uses it when detecting a Wake[CSN] command. The assigning of the CSN number causes microcontroller 103 to transition to the Config State which in turn causes microcontroller 103 to write address 0x13 to a 0x3.

Card resource data may only be read while in the Config State. A card may get to the Config State by one of two methods: in response to “winning” the serial isolation protocol and having a CSN assigned, as discussed above, or in response to receiving a Wake[CSN] command that matches the card's CSN. Only one Plug & Play device is in the Config State at one time. In this state, resource data are retrieved and the host software uses this information to program the corresponding configuration register 2004 c. Once the resource data has been accessed then the configuration register 2004 c are written and each logical device is activated.

In Codec 100 all accesses to PnP registers 2004 in the Configuration State (write 0x279, write 0xA79, read Read_Data port except resource data reads) result in IOCHRDY being forced low (hold current bus cycle) and the setting of a bit in microcontroller Port 1. Once microcontroller 103 reads either address 0x10, 0x11, or writes 0x12, respectively, then the particular Port 1 bit is cleared and IOCHRDY is released.

During resource data reads a polled handshake mechanism is used. Logic in Codec 100 outputs a ready indicator when a read from the PnP status register occurs. This ready bit is initially set “not ready” until microcontroller 103 outputs the first byte of a resource data read. The bit then remains ready until an ISA bus cycle occurs to read the byte. The occurrence of the ISA bus resource data read resets the ready bit to its “not ready” condition. A bit located on Port I (RDR P1-3 set=one) is used to indicate to microcontroller 103 when the resource data byte has been read. Microcontroller 103 then outputs the next resource byte (microcontroller 103 address-0x12) and the RDR bit is reset to zero. Configuration register data are written one logical device at a time. The individual logical device is selected by the Plug&Play Configuration Manager writing the logical device number to PnP address-0x7. Microcontroller 103 detects this and enables access to the appropriate logical device configuration registers.

After all logical devices have been configured logical device activation occurs one logical device at a time. Microcontroller 103 detects this and then sets the appropriate bit in the Logical Device Activate Register (microcontroller 103 address=0x1F). Each logical device is now enabled onto the ISA bus and should respond to the I/O address range, DMA channel, and interrupts that have been defined.

Plug-n-Play requires that the Plug-n-Play device contain data that indicates what system resources it requires. These resources may include memory space, I/O space, DMA channels, or Interrupts. In the case of Codec 100 the resources include a number of system I/O spaces, DMA channels, and Interrupts. Codec 100 supports two methods (EEPROM loaded, or host downloaded) of storing resource data. Both of these methods are flexible in that the resource data can be customized to support particular requirements.

Plug and Play cards return read-only configuration information in two formats. The serial identifier is returned bit-wise by the Plug and Play devices in response to reads from the Serial Isolation register. This information is returned in a serial format to facilitate the Plug and Play device selection algorithm described earlier. Plug and Play cards also provide resource data sequentially a byte at a time in response to reads from the Resource Data register. The resource configuration data completely describes all resource needs and options of the device and includes a header followed by a set of resource data structures which end with an End Tag:

The header holds the 72 serial identifier that is used during the Isolation sequence described earlier in TABLE 7.

TABLE 7
Field Name Length Definition
Vendor ID Byte 0 8 bits Bit[7] 0
Bits[6:2] First character in
compressed ASCII
Bits[1:0] Second character in
compressed ASCII bits[4:3]
Vendor ID Byte 1 8 bits Bits[7:5] Second character in
compressed ASCII bits[2:0]
Bits[4:0] Third character in
compressed ASCII
Vendor ID Byte 2 8 bits (Vendor Assigned)
First hexadecimal digit of product number
(bit 7 is msb)
Second hexadecimal digit of product number
(bit 3 is msb)
Vendor ID Byte 3 8 bits (Vendor Assigned)
Third hexadecimal digit of product number
(bit 7 is msb)
Bits[3:0] Hexadecimal digit of
revision level (bit 3 is
msb)
Serial/Unique 8 bits Unique device number so the system can
Number differentiate between multiple cards of the
Byte 0 same type in one system. Bits[7:0]
Serial Number 8 bits Serial Number Bits[15:8]
Byte 1
Serial Number 8 bits Serial Number Bits[23:16]
Byte 2
Serial Number 8 bit Serial Number Bits[31:24]
Byte 3
Checksum 8 bits Checksum of ID and serial number verifies
that the information has been correctly read
from a Plug and Play ISA card.

The 32-bit Vendor ID (Bytes 0-3) is an EISA Product Identifier (ID). This ID consists of:

(1) Bits[15:0] are a three character compressed ASCII EISA ID, (Compressed ASCII is defined as 5 bits per character, “00001”=“A” . . . “11010”−“Z”. This field is assigned to each manufacturer by the EISA administrative agent); and

(2) bits[31:16] define a manufacturer specific product number and revision. It is the responsibility of each vendor to select unique values for this field.

The purpose of this field is to serve as a unique board identifier that allows Plug and Play card selection through the isolation algorithm described earlier.

The 32-bit serial number (Bytes 4-7)is used only in the isolation process for selection of individual Plug and Play ISA cards. This unique number differentiates between multiple cards with the same Vendor ID when they are plugged into one system. If this feature is not supported then this field is returned as “FFFFFFFF.” Lack of a unique serial number implies that only one instance of a Vendor ID can be supported in a system.

The checksum field (Byte 8) is used to ensure that no conflicts have occurred while reading the device identifier information. The checksum is generated by using a LFSR mechanism 1007 shown in FIG. 10C. LFSR 1007 includes a series of storage/shift elements 1008 and a pair of exclusive-OR (XOR) gates 1009 and 1010. The LFSR resets to 0x6A upon receiving the WAKE[CSN] command. The next shift value for the LFSR is calculated as LFSR[1] XOR LFSR[0] XOR Serial Data. The LFSR value is shifted right one bit at the conclusion of each pair of reads to the Serial Isolation register. The LFSR[7] is assigned the next shift value again described above.

As indicated above, Plug and Play resource data fully describes all resource requirements of a Plug and Play device as well as resource programmability and interdependencies. Plug and Play resource data are supplied as a series of “tagged” data structures. Two types are supported: large items and small items. The first byte defines the type and size and is followed by one or more bytes of actual information. Bit [7] of the first byte is used as the tag identifier to differentiate between small and large data types.

A Plug and Play logical device may use any number of resources and any combination of small item or large item data types. The general format is:

(1) Plug and Play version number type;

(2) Identifier string resource type;

(3) Logical device ID resource type which identifies;

a) Any compatible device ID resource type for this logical device;

b) Resource data types to match what the function uses (IRQ, memory, I/O, DMA)-the order is not important; and

c) Any dependent functions needed if the Plug and Play card is configurable. The order of the resource data establishes the binding to the configuration registers. (Note: Step 3 is repeated for each logical device present on the Plug and Play card.); and

(4) End tag resource type to indicate the end of resources for this Plug and Play card.

The order of resource descriptors is significant because configuration registers are programmed in the same order that descriptors are read. This may be important in some hardware implementations. Further, in the case of Dependent Functions it may be necessary to include null descriptors (“filler”) in order to maintain the desired descriptor-to-register mapping regardless of which Dependent Function is programmed by the software.

The 3-byte Plug & Play Version Number identifies the version of the Plug and Play specification with which the card is compatible. A vendor specific number is included and may be used by a device driver to verify the version of the card. TABLE 8 summarizes these version numbers.

TABLE 8
Offset Field Name
Byte 0 Value = 00001010B (Type=0, small item name=0x1,
length =2)
Byte 1 Plug and Play version number (in packed BCD
format, major bits[7:4], minor bits[3:0]
Example: Version 1.0 = 0x10, Version 2.3 =
0x23
Byte 2 Vendor specific version number

The Identifier String is an ASCII string used to identify the card type or function. This string is displayed to the user during a Plug n Play sequence. Example: “Crystal Semiconductor Codec 100 Sound Chip.” TABLE 9 summarizes the ASCII string fields and fields related thereto.

TABLE 9
Offset Field Name
Byte 0 Value = 10000010B (Type=1, large item name=0x2)
Byte 1 Length byte 0
Byte 2 Length byte 1
Byte 3 ASCII Identifier String

Each logical device must be defined in order for the operating system to be able to allocate resources and identify and load appropriate device drivers. For each logical device the following data structures are required:

Logical Device ID

Configuration

DMA

IRQ

I/O Descriptors

ANSI ID String

The following data structures are optional:

Start Dependent Functions
Best Configuration
DMA
IRQ
I/O Descriptors
Acceptable Configuration
DMA
IRQ
I/O Descriptors
Sub-Optimal Configuration
DMA
IRQ
1/0 Descriptors
End Dependent Functions

Compatible Device ID

The Logical Device ID provides a mechanism for uniquely identifying multiple logical devices embedded in a single physical board. The fields of the Logical Device ID are summarized in TABLE 10. The format of the logical device ID is identical to the Vendor ID field discussed above:

(1) bits[15:0]—three character compressed ASCII EISA ID) and compressed ASCII is defined as 5 bits per character, “00001”=“A” . . . “11010”=“Z”. This field must contain a valid EISA ID, although it is not required to have the same 3 letters as the Vendor ID); and

(2) bits[31:16]—manufacturer-specific function number and revision. It is the manufacturer's responsibility to have unique bits[31:16] for different functions.

This identifier may be used to select a device driver for the device. Because of this, Logical Device IDs must be uniquely associated with a specific function. However, there is no need for the Logical Device ID itself to have a unique value, either on a card, or across cards. For instance, a card that implements two communications ports may use the exact same Logical Device ID for both. Similarly, two different products (different Vendor IDs) may both implement the same function, and therefore will use the same Logical Device ID for it. The Logical Device ID is required on all cards. On single-function cards, the Logical Device ID may be the same as the card's vendor ID.

TABLE 10
Offset Field Name
Byte 0 Value = 000101xxB (Type=0, small item name=0x2, length
=(5 or 6))
Byte 1 Bit [7] 0
Bits[6:2] First character in compressed ASCII
Bits[1:0] Second character in compressed ASCII
bits[4:3]
Byte 2 Bits[7:5] Second character in compressed ASCII
bits[2:0]
Bits[4:0] Third character in compressed ASCII
Byte 3 (Vendor Assigned)
Bits[7:4] First hexadecimal digit of function number
(bit 7 is msb)
Bits[3:0] Second hexadecimal digit of function number
(bit 3 is msb)
Byte 4 (Vendor Assigned)
Bits[7:4] Third hexadecimal digit of function number
(bit 7 is msb)
Bits[3:0] Hexadecimal digit of revision level (bit 3 is
msb)
Byte 5 Bits[7:1], if set, indicate commands supported per
logical device for registers in the range of 0x31 to 0x37
respectively.
Bit[0], if set, indicates this logical device is capable
of participating in the boot process. Note: Cards that
power-up active MUST have this bit set. However, if this
bit is set, the card may or may not power-up active.
Byte 6 Flags:
Bit[7:0], if set, indicate commands support per logical
device for registers in the range of 0x38 to 0x3F
respectively.

A compatible device ID provides the IDs of other devices with which the given Plug n Play device (e.g., Codec 100) is compatible. The host operating system uses this information to load compatible device drivers if necessary. There can be several compatible device identifiers for each logical device. The order of these device IDs may be used by the operating system as a criteria for determining which driver should be searched for and loaded first. TABLE 11 summarizes the fields of the Compatible Device ID.

TABLE 11
Offset Field Name
Byte 0 Value = 00011100B (Type=0, small item name=0x3, length =
4)
Byte 1 Bit [7] 0
Bits[6:2] First character in compressed ASCII
Bits[1:0] Second character in compressed ASCII
bits[4:3]
Byte 2 Bits[7:5] Second character in compressed ASCII
bits[2:0]
Bits[4:0] Third character in compressed ASCII
Byte 3 (Vendor Assigned)
Bits[7:4] First hexadecimal digit of function number
(bit 7 is msb)
Bits[3:0] Second hexadecimal digit of function number
(bit 3 is msb)
Byte 4 (Vendor Assigned)
Bits[7:4] Third hexadecimal digit of function number
(bit 7 is msb)
Bits[3:0] Hexadecimal digit of revision level (bit 3 is
msb)
Byte 1 Compatible device ID bits[7:0]
Byte 2 Compatible device ID bits[15:8]
Byte 3 Compatible device ID bits[23:16]
Byte 4 Compatible device ID bits[31:24]

As an example of the use of compatible IDs, consider a card vendor who ships a device with logical ID 0xABCD0000. At a later date, this vendor ships a new device with a logical ID 0xABCD0001. This new device is 100% compatible with the old device but also has added functionality. For this device, the vendor could include the Compatible device ID 0xABCD0000. In this case, the exact driver for 0xABCD0001 will be loaded if it can be located. If the driver for 0xABCD0001 can not be found, the driver for device 0xABCD0000 will be loaded for the device.

The IRQ data structure indicates that the Plug n Play device uses an interrupt level and supplies a mask with bits set indicating the levels implemented in the device. For a standard ISA implementation there are 16 possible interrupt levels so a two byte field is used. This structure is repeated for each separate interrupt level required. TABLE 12 summarizes the fields of the IRQ data structure.

TABLE 12
Offset Field Name
Byte 0 Value = 0010001XB (Type=0, small item name=0x4, length
=(2 or 3))
Byte 1 IRQ mask bits[7:0]. Bit[0] represents IRQ0, bit[1] is
IRQ1, and so on.
Byte 2 IRQ mask bits[15:8]. Bit[0] represents IRQ8, bit[1] is
IRQ9, and so on.
Byte 3 IRQ Information. Each bit, when set, indicates this
device is capable of driving a certain type of interrupt.
(optional--if not included then assume ISA compatible
edge sensitive, high true interrupts)
Bit[7:4] Reserved and must be 0
Bit[3] Low true level sensitive
Bit[2] High true level sensitive
Bit[1] Low true edge sensitive
Bit[0] High true edge sensitive (Must be supported
for ISA compatibility)

The DMA data structure, summarized in TABLE 13, indicates that the PnP device uses a DMA channel and supplies a mask with bits set indicating the channels actually implemented in this device. This structure is repeated for each separate channel required.

TABLE 13
Offset Field Name
Byte 0 Value = 00101010B (Type=0, small item name=0x5, length =
2)
Byte 1 DMA channel mask bits[7:0]. Bit[0] is channel 0.
Byte 2 Bit[7] Reserved and must be 0
Bits[6:5] DMA Channel speed supported
Status
00 Indicates compatibiiity mode
01 Indicates Type A DMA as described in
the EISA Specification
10 Indicates Type B DMA
11 Indicates Type F
Bit[4] DMA word mode
Status
0 DMA may not execute in county by
word mode
1 DMA may execute in county by word
mode
Bit[3] DMA byte mode status
Status
0 DMA may not execute in count by
byte mode
1 DMA may execute in county by byte
mode
Bit[2] Logical device bus master status
Status
0 Logical device is not a bus master
1 Logical device is a bus master
Bits[1:0] DMA transfer type preference
Status
00 8-bit only
01 8- and 16-bit
10 16-bit only
11 Reserved

Each logical device requires a set of resources. This set of resources may have interdependencies that need to be expressed to allow arbitration software to make resource allocation decisions about the logical device. Dependent functions are used to express these interdependencies. The data structure definitions for dependent functions are shown in TABLE 14.

TABLE 14
Offset Field Name
Byte 0 Value = 0011000xB (Type=0, small item name=0x6,
length=(0 or 1))

Start Dependent Function fields may be of length 0 or 1 bytes. The extra byte is optionally used to denote priority for the resource group following the Start DF tag. If the extra byte is not included, this indicates the dependent function priority is ‘acceptable’. If the Priority byte is included, the priorities are defined in TABLE 15:

TABLE 15
Value Definition
0 Good configuration - Highest Priority and preferred
configuration
1 Acceptable configuration - Lower Priority but acceptable
configuration
2 Sub-optimal configuration - Functional configuration but
not optimal
3-255 Reserved

Note that if multiple Dependent Functions have the same priority, they are further prioritized by the order in which they appear in the resource data structure. The Dependent Function which appears earliest (nearest the beginning) in the structure has the highest priority, and so on.

TABLE 16 defines the structure for end dependent functions.

TABLE 16
Offset Field Name
Byte 0 Value = 00111000B (Type=0, small item name=0x7, length=0)

Note that only one End Dependent Function item is allowed per logical device. This enforces the fact that Dependent Functions are not nettable.

There are two types of descriptors for I/O ranges. The first type of descriptor is a full function descriptor for programmable ISA cards defined in TABLE 31. The second type of descriptor is a minimal descriptor (Fixed Location I/O Descriptor) for ISA cards with fixed I/O requirements and use a 10-bit ISA address decode. The second type of descriptor is defined in TABLE 17. The first type of descriptor can also be used to describe fixed 1/0 requirements for ISA cards that require a 16-bit address decode. This is accomplished by setting the range minimum base address and range maximum base address to the same fixed I/O value.

TABLE 17
Offset Field Name Definition
Byte 0 I/O port descriptor Value = 01000111B (Type = 0, Small
item name = 0x8, Length = 7)
Byte 1 Information Bits[7:1] are reserved and must be 0
Bit[0], if set, indicates the logical
device decodes the full 16 bit ISA
address. If bit[0] is not set, this
indicates the logical device only
decodes ISA address bits[9:0].
Byte 2 Range minimum base Address bits[7:0] of the minimum base
address I/O address that the card may be
bits[7:0] configured for.
Byte 3 Range minimum base Address bits[15:8] of the minimum
address base I/O address that the card may be
bits[15:8] configured for.
Byte 4 Range maximum base Address bits[7:0] of the maximum base
address I/O address that the card may be
bits[7:0] configured for.
Byte 5 Range maximum base Address bits[15:8] of the maximum
address base I/O address that the card may be
bits[15:8] configured for.
Byte 6 Base alignment Alignment for minimum base address,
increment in 1 byte blocks.
Byte 6 Range length The number of contiguous I/O ports
requested.

TABLE 18
Offset Field name Definition
Byte 0 Fixed Location I/O Value = 01001011B (Type = 0, Small
port descriptor item name = 0x9, Length = 3)
Byte 1 Range base address Address bits[7:0] of the base I/O
bits[7:0] address that the card may be
configured for. This descriptor
assumes a 10 bit ISA address decode.
Byte 2 Range base address Address bits[9:8] of the base I/O
bits[9:8] address that the card may be
configured for. This descriptor
assumes a 10 bit ISA address decode.
Byte 3 Range length The number of contiguous I/O ports
requested.

The vendor defined resource data type is for vendor use and is defined in TABLE 19.

TABLE 19
Offset Field Name
Byte 0 Value = 01110xxxB (Type=0, small item name=0xE,
length=(1-7))
Byte 1 Vendor defined
to 7

The End Tag, defined in TABLE 20, identifies an end of resource data. If the checksum field is zero, the resource data are treated as if it checksummed properly. Configuration proceeds normally.

TABLE 20
Offset Field Name
Byte 0 Value = 01111001B (Type=0, small item name=0xF, length=1)
Byte 1 Check sum covering all resource data after the serial
identifier. This check sum is generated such that adding
it to the sum of all the data bytes will produce a zero
sum.

As indicated above, Plug-n-Play organizes physical devices into groups of logical devices. A logical device may be comprised of up to four non-contiguous Memory Address ranges, eight non-contiguous I/O Address ranges, two Interrupts, and two DMA channels. Codec 100 only supports I/O, interrupts, and DMA.

Codec 100 has a fixed physical-to-logical device mapping summarized in TABLE 21. The Plug-n-Play resource data must match the Logical-to-Physical device mapping defined in TABLE 20. Controller 103 firmware translates Plug-n-Play logical device configuration cycles into writes of the appropriate hardware configuration registers.

TABLE 21
Logical Physical Device 0 Physical Device 1 Physical Device 6
Device 0 Sound System Synth Sound Blaster
I/O Base Address 0 I/O Base Address 1 I/O Base Address
Interrupt 0 Interrupt 1 2
DMA Channel 0 Shared Interrupt
DMA Channel 1 0
Shared DMA
Channel 0
Logical Physical Device 5
Device 1 Game Port
I/O Base Address 0
Logical Physical Device 0 Physical Device 1 Physical Device 6
Device 0 Sound System Synth Sound Blascer
I/O Base Address 0 I/O Base Address 1 I/O Base Address
Interrupt 0 Interrupt 1 2
DMA Channel 0 Shared Interrupt
DMA Channel 1 0
Shared DMA
Channel 0
Logical Physical Device 2
Device 2 Control
I/O Base Address 0
Interrupt 0
Logical Physical Device 3
Device 3 MPU-401
I/O Base Address 0
Interrupt 0
Logical Physical Device 4
Device 4 CDROM
I/O Base Address 0
I/O Base Address 1
Interrupt 0
DMA Channel 0
Logical Physical Device 7
Device 5 Modem
I/O Base Address 0
Interrupt 0

To support environments in which Codec 100 is located directly on Motherboards, a Host Load mechanism is used to download Plug-n-Play resource data to Codec 100. In this environment the Motherboard BIOS loads the resource data into Codec 100 prior to any Plug-n-Play activity taking place.

To download configuration and Plug-n-Play resource data Codec 100 Control logical device must first be mapped into the host I/O space. This is accomplished by sending the Plug-n-Play key sequence described above followed by an isolation and configuration sequence to configure the Control logical device. Once the Control logical device has been mapped then the Plug-n-Play resource data may be loaded into Codec 100 via the Control Port at Control base +5.

For non-motherboard applications and external EEPROM is required to load configuration and resource data into Codec 100. On power-up microcontroller 103 checks for the existence of the EEPROM. If one is found then the EEPROM data, including Plug-n-Play resource data are down loaded from the EEPROM. A description of EEPROM formats that are supported by Codec 100 is discussed in detail below.

In Codec 100 the Plug-n-Play compatibility is accomplished through the use of the internal microcontroller 103 and logic gates. Microcontroller 103 interfaces to the external logic through the use of memory mapped registers. These registers control the mapping of the various Codec 100 physical devices as well as provide a means to control the external logic during certain phases of Plug-n-Play sequences.

As mentioned immediately above a set of registers is memory mapped into microcontroller 103 address space. Microcontroller 103 accesses these registers through specific memory access instructions (MOVX). To facilitate hardware test modes of Codec 100, all Plug & Play configuration registers are reset to default values on power-up. These default values will remain intact only if microcontroller 103 is not operating; which is the case for Test Modes 3, 4, 5, and 6 (discussed below). In non-test mode (normal) operation of Codec 100, microcontroller 103 will modify all the configuration defaults to off/disabled states.

FIGS. 12A-12Y are diagrams of the bitfields of the ISA/PNP Configuration registers.

FIG. 12A is a diagram of the bitfields of the Plug & Play Address-Register at microcontroller 103 Address 0x10. This register stores the last 8-bit data value written to the Plug & Play_Address Register (location 0x279).

FIG. 12B is a diagram of the bitfields of Plug & Play Write_Data_Port at microcontroller 103 Address 0x11. When this address is read the current data on the ISA data bus is enabled onto Codec 100 internal data bus. The read in response to an ISA bus write to the Plug & Play Write_Data register location 0xA79. This register is written by microcontroller 103 during resource data reads.

FIG. 12C is a diagram of the bitfields of the Plug & Play Read_Data_Register at microcontroller 103 Address 0x12. This register is written by microcontroller 103 in response to a read from the Plug & Play Read_Data_Port.

FIG. 12D is a diagram of the bitfields of the Plug & Play State Register at microcontroller 103 Address 0x13. These bits are updated by microcontroller 103 as a Plug & Play sequence progresses through its various states. The hardware requires these bits in order to effect the appropriate responses during a Plug & Play sequence. The decoding to PS0 and PS1 fields is shown in Table 22:

TABLE 22
PS1 PS0 Plug & Play State
0 0 Wait_For_Key
0 1 Sleep
1 0 Isolation
1 1 Configure

FIG. 12E is a diagram of the bitfields of the Plug & Play Control/Status register at microcontroller 103 Address 0x14. This register is reset to zero when RESDRV is high. The decoding is as follows:

Isolation Lose ILS—this bit indicates that the Plug & Play hardware has lost isolation during the current isolation sequence;

Serial Identifier/Sound Blaster Busy SID/SBB—this bit is written by microcontroller 103 during an isolation sequence and holds a serialized version of the 72-bit identifier. The hardware uses this bit to determine how the data bus should be driven (0x55/0xAA or tri-state) during a PnP Isolation sequence, as well as during Sound Blaster operation to enable/disable OR'ing of the current SB Busy with the codec playback DMA request;

Enable E2PROM EEP—this bit when set to a one enables the Port 1 pins 6 and 7 onto the EDATA[0] and EA[0] pins; and

EA2 Function—when 0 will force XCTL0 onto the EA2 pin. When this bit is=1, then the normal EA2 function is output on the EA2 pin.

FIG. 12F is a diagram of the bitfields of the Sound System Base Address Low at microcontroller 103 Address 0x15. This register is reset to zero when RESDRV is high and is used to specify the lower 6-bits of the 12-bit Sound System Codec base address. The number of consecutive locations decoded at this base address is fixed at four bytes.

FIG. 12G is a diagram of the bitfields of the Sound System Base Address High register at microcontroller 103 Address 0x16. This register is reset to zero when RESDRV is high and is used to specify the upper 4-bits of the 12-bit Sound System Codec base address.

FIG. 12H is a diagram of the bitfields of the Control Base Address Low register at microcontroller 103 Address 0x17. This register is reset to zero when RESDRV is high and is used to specify the lower 6-bits of the 12-bit Control base address. The number of consecutive locations decoded at this base address is fixed at eight bytes.

FIG. 12I is a diagram of the bitfields of the Control Base Address High register at microcontroller 103 Address 0x18. This register is reset to zero when RESDRV is high and is used to specify the upper 4-bits of the 12-bit Control base address.

FIG. 12J is a diagram of the bitfields of the Sound Blaster Base Address Low register at microcontroller 103 Address 0x19. This register is reset to zero when RESDRV is high and is used to specify the lower 4-bits of the 10-bit Sound Blaster base address. The number of consecutive locations decoded at this base address is fixed at sixteen bytes.

FIG. 12K is a diagram of the bitfields of the Sound Blaster Base Address High register at microcontroller 103 Address 0x1A. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit Sound Blaster base address.

FIG. 12L is a diagram of the bitfields of the Synth Base Address Low register at microcontroller 103 Address 0x1B. This register is reset to zero when RESDRV is high and is used to specify the lower 6-bits of the 10-bit Synthesizer OPL3 base address. The number of consecutive locations decoded at this base address is fixed at four bytes.

FIG. 12M is a diagram of the bitfields of the Synth Base Address High register at microcontroller 103 Address 0x1C. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit Synthesizer OPL3 base address.

FIG. 12N is a diagram of the bitfields of the MPU-401 Base Address Low register at microcontroller 103 Address 0x1D. This register is reset to zero when RESDRV is high and is used to specify the lower 7-bits of the 10-bit MPU-401 base address. The number of consecutive locations decoded at this base address is fixed at two bytes.

FIG. 12O is a diagram of the bitfields of the MPU-401 Base Address High register at microcontroller 103 Address 0x1E. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit MPU-401 base address.

FIG. 12P is a diagram of the bitfields of the Game Port Base Address Low register at microcontroller 103 Address 0x1F. This register is reset to zero when RESDRV is high and is used to specify the lower 5-bits of the 10-bit Game Port base address. The number of consecutive locations decoded at this base address is fixed at eight bytes.

FIG. 12Q is a diagram of the bitfields of the Game Port Base Address High register at microcontroller 103 Address 0x20. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit Game Port base address.

FIG. 12R is a diagram of the bitfields of the CDROM Base Address Low register at microcontroller 103 Address 0x21. This register is reset to zero when RESDRV is high and is used to specify the lower 6-bits of the I/O-bit CDROM base address. The number of consecutive locations decoded at this base address is fixed at four bytes.

FIG. 12S is a diagram of the bitfields of the CDROM Base Address High register at microcontroller 103 Address 0x22. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit CDROM base address.

TABLE 23 describes the bit decodings for the interrupt select registers depicted in FIGS. 12T-12Y, and discussed below, where IRQA-IRQE describe the interrupt pins enabled by the interrupt mapping value written into the given register.

TABLE 23
PIN Interrupt Mapping
IRQ Disabled 0
IRQA 1
IRQB 2
IRQC 3
IRQD 4
IRQE 5
IRQF 6

FIG. 12T is a diagram of the bitfields of the Synth Interrupt Select register at microcontroller 103 Address 0x23. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the Synthesizer interrupt is mapped.

FIG. 12U is a diagram of the bitfields of the Sound Blaster Interrupt Select register at microcontroller 103 Address 0x24. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the Sound Blaster interrupt is mapped.

FIG. 12V is a diagram of the bitfields of the Sound System Interrupt Select register at microcontroller 103 Address 0x25. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the Synthesizer interrupt is mapped.

FIG. 12W is a diagram of the bitfields of the MPU-401 Interrupt Select register at microcontroller 103 Address 0x26. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the MPU-401 interrupt is mapped.

FIG. 12X is a diagram of the bitfields of the CDROM Interrupt Select register at microcontroller 103 Address 0x27. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the CDROM interrupt is mapped.

FIG. 12Y is a diagram of the bitfields of the Control Interrupt Select register at microcontroller 103 Address 0x28. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the Control interrupt is mapped.

Microcontroller 103 I/O on port 1 is a ISA bus monitoring port. The data present on the I/O port 1 pins indicates to microcontroller 103 what is happening on the ISA Bus as far as Plug & Play register accesses are concerned. Once Codec 100 has made a transition out of the Wait for-Key State then Port 1 is polled for Plug & Play register accesses. FIG. 13 defines PnP Port I, where:

AWR-Address Write Pending—when set to a one indicates that a write to the PnP Address Register(0x279) has occurred. When this bit is a one during Sleep and Configure states, IOCHRDY will be forced high, effectively holding the current ISA bus cycle until microcontroller 103 has accessed microcontroller 103 address 0x10. This bit is cleared to zero upon a read of microcontroller 103 address 0x10.

DWR-Data Write Pending—when set to a one indicates that a write to the PnP Data Write Register has occurred. When this bit is a one during Sleep and Configure states, IOCHRDY WILL be forced high, effectively holding the current ISA bus cycle until microcontroller 103 has accessed microcontroller 103 address 0x11. This bit is cleared to zero upon a read of microcontroller 103 address 0x11.

DRD-Data Read Pending—when set to a one indicates that a read from the PnP Read Data Port has occurred. This bit is cleared to zero upon a write to microcontroller 103 address 0x12 or during an Isolation sequence by a write to microcontroller 103 address 0x14.

KEY/RDR—Key/Resource Data Read—When Codec 100 is in a WAIT_FOR_KEY state and a “PnP Key” or “Crystal Key” sequence (discussed above) is detected, microcontroller 103 is interrupted via INT0. This bit then indicates what “Key” was detected. KEY=0 for “PnP Key” and KEY=1 for “Crystal Key”. Alternately during a Resource Data Read sequence this bit when set to a one indicates that the current resource data byte has been read and that the ISA interface is ready for the next byte. This bit is cleared to zero upon a write to microcontroller 103 address 0x12. This bit is also set when a “Crystal Key Sequence” has been received.

For applications that do not require Plug-n-Play capability the “Crystal Key” backdoor mechanism may be used to program the configuration of Codec 100. Each Codec 100 logical device is configured one at a time. The configuration data must match or be a subset of the logical device definition described above. All commands including the “Crystal Key” sequence are written to the Plug-n-Play port at ISA Bus address 0x279. The following commands are used in performing a configuration sequence.

Typical Programming Sequence bypassing the PnP interface is as follows:

Program Start:
Send Crystal Key
Select Logical Device
Program I/O Base 0
Program I/O Base I - if required
Program I/O Base 2 - if required
Program Interrupt - if required
Program DMA 0 - if required
Program DMA 1 - if required
Activate Logical Device
Select Logical Device
Program I/O Base 0 - if required
Program I/O Base 1 - if required
Program I/O Base 2 - if required
Program Interrupt - if required
Program DMA 0 - if required
Program DMA 1 - if required
Activate Logical Device
|
|
|
Select Logical Device
Program I/O Base 0 - if required
Program 110 Base 1 - if required
Program I/O Base 2 - if required
Program Interrupt - if required
Program DMA 0 - if required
Program DMA 1 - if required
Activate Logical Device
Activate Card
Program End:

The instructions and commands in the foregoing exemplary programmed sequence can be described as follows:

Send Crystal Key—The “Crystal Key” is not a command but a sequence of 32 bytes that are written in succession. When Codec 100 receives the correct sequence of 32 bytes the Plug-n-Play logic of Codec 100 transitions to the Configuration State. The configuration registers of Codec 100 may only be modified when Codec 100 is in the Configuration State.

Program the CSN (Card Select Number) 0x6—The CSN number for Codec 100 may optionally be programmed by executing this command. This command is executed by writing a 0x6 followed by the 8-bit CSN number. If this command is not used then the CSN number for Codec 100 will default to zero.

Select Logical Device (0x15)—The configuration registers of Codec 100 are programmed one logical device at a time. This command is executed by writing a 0x15 followed by an 8-bit logical device number. Codec 100 supports eight physical devices (0:7) as previously noted.

IO Port Base Address 0 (0x47)—This command is executed by writing a 0x47 followed by a write of the low byte of the I/O base address, and a write of the high byte of the I/O base address.

IO Port Base Address I (0x48)—This command is executed by writing a 0x48 followed by a write of the low byte of the I/O base address, and a write of the high byte of the I/O base address.

IO Port Base Address 2 (0x42)—This command is executed by writing a 0x42 followed by a write of the low byte of the I/O base address, and a write of the high byte of the I/O base address.

Interrupt Select 0 (0x2A)—This command is executed by writing a 0x22 followed by a write of the interrupt line to generate an interrupt on.

Interrupt Select 1 (0x27)—This command is executed by writing a 0x27 followed by a write of the interrupt line to generate an interrupt on.

DMA Select 0 (WA)—This command is executed by writing a 0x2A followed by a write of the DMA channel that is to be used.

DMA Select 1 (0x25)—This command is executed by writing a 0x25 followed by a write of the DMA channel that is to be used.

Activate Logical Device (0x33)—This command is executed by writing a 0x33 followed by a byte of one to activate the currently selected logical device.

Deactivate Logical Device (0x33)—This command is executed by writing a 0x33 followed by a byte of zero to deactivate the currently selected logical device.

Activate Codec 100 (0x79) The configuration data are processed and transferred to the appropriate Codec 100 registers upon execution of this command. This command puts Codec 100 into the Wait_For_Key_State.

Once a Plug & Play sequence has transpired each logical device, including Codec 100, will have an I/O base address assigned to it. This assigned base address is stored in each I/O base address register. ISA bus address bits A12 . . . A0 are compared with the values stored in the I/O base address registers, and if a match is found, then the appropriate logical device is selected for access. Each physical device occupies a number of consecutive byte locations. TABLE 24 sets out the address decoding for a selected number of PnP devices, including Codec 100. For 9-bit decodes A11 . . . A10 are assumed to be zero.

TABLE 24
ISA Bus/Address
Physical Device Bits Decoded Number of Consecutive Bytes
Sound System A11 . . . A2 Four via A1 . . . A0
Synth A9 . . . A2, A9 . . . A3 Four or Eight via A2 . . . A0
Sound Blaster A9 . . . A4 Sixteen via A3 . . . A0
Codec 100 A11 . . . A3 Eight via A2 . . . A0
MPU-401 A9 . . . A1 Two via A0
Game Port A9 . . . A3 Eight via A2 . . . A0
CDROM A9 . . . A2, A9 . . . A3 Four or Eight via A2 . . . A0

Because the ISA bus provides 16-bit address for I/O decoding, Codec 100 10-bit and 12-bit decoded address ranges will alias into the upper addresses due to the fact that address bits [A15 . . . A11] and [A15 . . . A13] are not decoded. Normally this is not a problem, but it could be for some mother board manufacturers. In order to prevent the address decoding from aliasing, Codec 100 supports a mode where by the high order address bits (A15 . . . A12) are input via CDROM interface 120. CDROM/Modem interface 120 is not available in this mode. The address bits A15 . . . A12 are then decoded along with [A11 . . . A10] to generate logical device selects for Sound System and Codec 100 registers. A valid logical device decode occurs when bits [A15 . . . A12] are equal to [0,0,0,0] and bits [A11 . . . A0] match one of the current programmed base address registers. For all other address decodes, bits A15 . . . A10 are decoded along with bits [A.9 . . . A0] to generate device selects. A valid logical device decode occurs when [A15 . . . A10] are equal to [0,0,0,0,0,0] and [A9 . . . A0] match one of the current programmed base address registers.

The 16-bit address decode function is selected by the XIOR pin being high at the time the RESDRV pin transitions from a high to low.

Several user defined registers are available in the Card Level Vendor Defined area specified by Plug and Play ISA Specification Version 1.0a.

The RAM Access Register at address 0x28 will allow the host to access program RAM in the similar access through the Control Registers but using PnP ADDRESS, WRITE_DATA and READ_DATA ports instead of Control ports (Control Base +5 and Control Base +6). All control port accessible commands are available with this access method. The JUMP_TO_ROM (57h) command should not be used through this PnP method nor should mixing of control port and PnP accesses be mixed, e.g. a PnP HOLD and a control port GO. A separate PnP JUMP TO ROM command is provided. The following is a typical sequence to access the RAM:

1) Write an 0x28 to the ADDRESS port;

2) Write a relevant function byte to the WRITE_DATA port (such as 0x55 for disable PnP, 0x56 for disable Crystal key, 0x5A for update, 0xAA for RAM write/read, etc.) (For RAM write/read only, steps 3 and 4 are needed.);

3) Write a low byte and high byte of the RAM starting address to the WRITE_DATA port and then write/read the data to/from the WRITE_DATA/READ-DATA port; and

4) Finally execute a RAM END command to finish the RAM write/read.

The RAM END Register 0x2A allows the host to execute a RAM END by:

1) Writing an 0x2A to the ADDRESS port; and

2) Then writing an 0x00 to the WRITE_DATA port.

The RAM JUMP TO ROM Register 0x2B forces code jump to a tight loop in ROM:

1) Write an 0x2B to the ADDRESS port; and

2) Then write an 0x57 to the WRITE_DATA port.

The Chip “Black_out” Register 0x2F causes the chip to enter into “Black_out” state, which will shut down all activated logical devices, cause PnP and Crystal keys to be disabled and force the part go into WAIT_FOR_KEY state.

FIGS. 14A-14D are diagrams of the bitfields of the DMA Channel Select Registers, the bits in each of these registers operate as shown in TABLE 25, where DMA-A to DMA-D are the four available DMA channels enabled:

TABLE 25
DMA CHANNEL REGISTER VALUE
DMA Disabled 4-7
DMA-A 0
DMA-B 1
DMA-C 2
DMA-D 3

FIG. 14A is a diagram of the bitfields of the Sound Blaster DMA Channel Select registers at microcontroller 103 address 0x29. This register is reset to zero when RESDRV is high and is used to specify one of the four ISA DMA channels to which the Sound Blaster DMA signals is mapped.

FIG. 14B is a diagram of the bitfields of the Sound System Playback/Capture DMA Channel Select registers at microcontroller 103 address 0x2A. This register is reset to zero when RESDRV is high and is used to specify one of four the ISA DMA channels to which the Sound System Playback/Capture DMA signals is mapped

FIG. 14C is a diagram of the bitfields of the Sound System Capture DMA Channel Select register at microcontroller 103 address 0x2. This register is reset to zero when RESDRV is high and is used to specify one of the four ISA DMA channels to which the Sound System Capture DMA signals is mapped.

FIG. 14D is a diagram of the bitfields of the CDROM DMA Channel Select register at microcontroller 103 Address 0x2C. This register is reset to zero when RESDRV is high and is used to specify one of the four ISA DMA channels to which the CDROM DMA signals is mapped.

FIGS. 15A-15J are diagrams of the bitfields of miscellaneous registers.

FIG. 15A is a diagram of the bitfields of the Alternate CDROM Base Address Low register at microcontroller 103 Address 0x2D. This register is reset to zero when RESDRV is high and is used to specify the lower 8-bits of the 10-bit CDROM base address. The number of consecutive locations decoded at this base address is fixed at four bytes.

FIG. 15B is a diagram of the bitfields of the Alternate CDROM Base Address High registers at microcontroller Address 0x2E. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit CDROM base address.

FIG. 15C is a diagram of the bitfields of the Physical Device Activation Register at microcontroller 103 Address 0x2F. This register is used to enable specific physical devices after the configuration registers have been programmed. Each bit set equal to a one will enable the particular physical device as shown in TABLE 26. A value of zero will disable the corresponding physical device. When disabled, a particular physical device is physically disconnected (I/O base address, Interrupt and DMA) from ISA bus interface 101.

TABLE 26
Physical Device Activation Bit
Sound System PDA0
Adlib Synth PDA1
Control PDA2
MPU-401 PDA3
CDROM PDA4
Game Port PDA5
Sound Blaster PDA6
Modem PDA7

FIG. 15D is a diagram of the bitfields of the Modem Base Address Low register at microcontroller 103 Address 0x30. This register is reset to zero when RESDRV is high and is used to specify the lower 8-bits of the 10-bit Modem base address. The number of consecutive locations decoded at this base address is fixed at four bytes.

FIG. 15E is a diagram of the bitfields of the Modem Base Address High register at microcontroller 103 Address 0x30. This register is reset to zero when RESDRV is high and is used to specify the upper 2-bits of the 10-bit Modem base address.

FIG. 15F is a diagram of the bitfields of the Alternate CDROM Mask Register at microcontroller 103 Address 0x32. The CDROM Address Mask Register provides a means to vary the number of consecutive byte locations that a secondary CDROM I/O decode may occupy. Each mask bit is used to prevent specific address bits from being decoded in generating the secondary CDROM I/O decode. The valid bit combinations are as shown in TABLE 27.

TABLE 27
CDROM Decode = number of
AMC2 AMC1 AMC0 consecutive bytes
1 1 1 8 bytes, address bits A2, A1, A0 are don't
cares.
0 1 1 4 bytes, address bit A2 is decoded. Bits A1,
A0 are don't cares.
0 0 1 2 bytes, address bits A2 and A1 are decoded.
Bit A0 is a don't care.
0 0 0 1 byte, address bits A2, A1, A0 are all
decoded.

FIG. 15G is a diagram of the bitfields of the Modem Mask Register at microcontroller 103 Address 0x33. The Modem Address Mask Register provides a means to vary the number of consecutive byte locations that the modem decode may occupy. Each mask bit is used to prevent specific address bits from being decoded in generating the modem I/O decode. The valid bit combinations are as shown in TABLE 28.

TABLE 28
Model Decode = number of consecutive
AMM [7:0] bytes
11111111 256 bytes, address bits A[7 . . . 0] are
don't cares.
01111111 128 bytes, address bit A7 is decoded.
Bits A[6 . . . 0] are don't cares.
00111111 64 bytes, address bits A7 and A6 are
decoded. Bits A[5 . . . 0] are don't
cares.
00011111 32 bytes, address bits A[7 . . . 5] are
decoded. Address bits A[4 . . . 0] are
don't cares.
00001111 16 bytes, address bits A[7 . . . 4] are
decoded. Address bits A[3 . . . 0] are
don't cares.
00000111 8 bytes, address bits A[7 . . . 3] are
decoded. Address bits A[2 . . . 0] are
don't cares.
00000011 4 bytes, address bits A[7 . . . 2] are
decoded. Address bits A[1 . . . 0] are
don't cares.
00000001 2 bytes, address bits A[7 . . . 1] are
decoded. Address bits A[0] is a
don't care.
00000000 1 byte, address bits A[7 . . . 0] are
decoded.

FIG. 15H is a diagram of the bitfields of the Miscellaneous Control Bits register at microcontroller 103 Address 0x34. A description of these bits is as follows:

PCDINT—Polarity CDROM Interrupt specifies polarity of CDROM interrupt input:

0=CDROM interrupt is active low; and

1=CDROM interrupt is active high.

PSINT—Polarity Synthesizer Interrupt specifies the polarity of synthesizer interrupt input:

0=synthesizer interrupt is active low; and

1=synthesizer interrupt is active high.

PMINT—Polarity Modem Interrupt specifies the polarity of modem interrupt input:

0=modem interrupt is active low; and

1=modem interrupt is active high.

XBUF—Transceiver buffer control:

XBUF=0 Codec drives data bus on reads of

CDROM addresses; and

XBUF=1 Codec tri-states data bus on reads of CDROM addresses.

SD7DE—SD7 Disable:

SD7DE 0=SD7-SD0 driven during reads of CDROM

Alternate Base +1

SD7DE 1=SD7 tri-stated, SD6-SD0 driven during reads of CDROM Alternate Base +1.

FIG. 15I is a diagram of the bitfields of the Modem Interrupt Select register at microcontroller Address 0x35. This register is reset to zero when RESDRV is high and is used to specify one of the six interrupt pins to which the Modem interrupt is mapped.

FIG. 15J is a diagram of the bitfields of the Physical Device Activity Register at microcontroller address=0x36. Each bit indicates that an ISA Bus access (read or write)to a particular physical device has occurred. The bit is set upon an ISA read or write access to one of eight physical devices as shown in TABLE 29. All bits are reset to zero upon an microcontroller 103 read of the register. In addition any DMA activity to the codec (PDACK,CDACK=0) also sets the Sound System (DA0) and Sound Blaster (DA6) bits.

TABLE 29
Physical Device Device Activity Bit
Sound System DA0
Adlib Synth DA1
Control DA2
MPU-401 DA3
CDROM DA4
Game Port DA5
Sound Blaster DA6
Modem DA7

FIG. 16 is a diagram of the bitfields of the Wavetable and Serial Control Register at microcontroller address 0x40. This register Reset to zero when RESDRV=1. The specific bitfields can be described as follows:

SBSP Sound Blaster Swap Playback—when this bit is set to a zero the current ordering of samples for DMA playback are swapped, relative to the current defined format. This bit affects only 8-bit playback in Sound Blaster mode.

SBSC Sound Blaster Swap Capture—when this bit is set to a one, the current ordering of samples for DMA capture are swapped, relative to the current defined format. This bit affects only 8-bit capture in Sound Blaster mode.

res Reserved

WTEN Wave Table Enable—When this bit is set to a one, the XD7:XD5 pins are switched to support a digital wavetable interface. When this bit is a zero the XD7:XD5 pins operate normally. TABLE 30 describes the decoding of the WTEN bit:

TABLE 30
WTEN 0 1
Pin 1 XD7 - Bi-directional DATA - Input
Pin 2 XD6 - Bi-directional LRCLK - Input
Pin 3 XD5 - Bi-directional MCLK - Output
Pin 4 XD4 - Bi-directional Defined by SPS
Pin 5 XD3 - Bi-directional Defined by SPS
Pin 6 XD2 - Bi-directional Defined by SPS
Pin 7 XD1 - Bi-directional Defined by SPS
Pin 8 XD0 - Bi-directional XD0 - Bi-directional

SPS Serial Port Switch—When this bit is set to a one, and the SPE bit in register I16 is set to a one, the DSP serial port pins are switched from the second joystick pins to the XD pins. If SPS is a zero and the SPE bit in register I16 is set to a one the DSP serial port pins are routed to the second joystick pins. If the SPE bit in register I16 is a zero then the serial port pins do not appear anywhere.

TABLE 31 describes the functioning of the SPS bit:

TABLE 31
SPS 0 1
Pin 1 XD7 - Bi-directional WTEN Defined
Pin 2 XD6 - Bi-directional WTEN Defined
Pin 3 XD5 - Bi-directional WTEN Defined
Pin 4 XD4 - Bi-directional FSYNC - Output
Pin 5 XD3 - Bi-directional SDOUT - Output
Pin 6 XD2 - Bi-directional SDIN - Input
Pin 7 XD1 - Bi-directional SCLK - Output
Pin 8 XD0 - Bi-directional XD0 - Bi-directional
NOTE: If either WTEN or SPS are set to a one then the XBUF bit in CDROM Interface Control Register at microcontroller address 0x34 is forced to a one.
MCLKDIS When this bit is set to a one, and the wavetable serial interface is enabled by WTEN = 1, the MCLK pin to the wavetable device is synchronously forced to zero. MCLK will remain a zero until MCLKDIS is set to zero. At this time MCLK will synchronously be enabled.
BRESET When this bit is set to a one the BRESET pin is forced to zero. This is to allow microcontroller 103 and host control of external devices connected to the BRESET pin.

Codec 100 has the ability to override the current bond out definition by allowing microcontroller 103 access to a register that replaces the bond out wires. The mechanism by which this register is modified is a Control Port Command (RAM Write) to Control_base +5. Registers I25 and C1 should reflect the bond out as defined by either the pads or the register bits BO1:BO0 depending on the state of BOE2:BOE0.

FIG. 17 is a diagram of the bitfields of microcontroller address 0x41. (Reset to 0x00). The bitfields are decoded in TABLE 32 as follows:

res Reserved for future use. Always read back as zero's;

TABLE 32
RES RES RES RES RES RES RES RES
RESERVED LOCATION AT 0 × 41

FIG. 18 is a diagram of the bitfields of the Port 3 Shadow Register at microcontroller address 0x42. The bitfields of this register function as follows:

P3.0—UP—This bit follows the state of Codec 100 UP pin when VCEN is set.

P3.1—DOWN—This bit follows the state of Codec 100 Down pin when VCEN is set.

P3.2—MUTE—This bit follows the state of Codec 100 Mute pin when VCEN is set.

P3.3—REQUEST—This field is set to a one to update codec registers that may be in contention with ISA bus accesses (WSS mode). After polling for GRANT=1, microcontroller 103 may access codec registers as needed. After microcontroller 103 has finished its codec accesses, the REQUEST bit should be set to zero to re-enable ISA access to the codec registers.

P3.4—GRANT—This bit is polled by microcontroller 103 after setting the REQUEST bit=1. When GRANT is equal to one, microcontroller 103 may access codec registers without contention with the ISA bus. When GRANT=1 and subsequent ISA codec accesses are held off via IOCHRDY (discussed below in conjunction with FIG. 19) until the REQUEST bit is set to zero by microcontroller 103.

P3.5—Codec INT—Read Only. This bit follow the state of the internal codec interrupt signal (not

1) Write the appropriate Crystal Key Disable of PnP Key Disable command using the RAM Access Register defined above. The command numbers are identical to the Control Port Command Interface command numbers;

2) Write an 10x2F to the ADDRESS port;

3) Write a zero TO PNP_WRITE_DATA PORT to deactivate the logical; and

4) Either the Crystal Key, or the PnP, or Both functions will be inactive.

External EEPROM

As mentioned above, an external EEPROM is typically for all Codec 100 environments. The EEPROM is coupled to Codec 100 through the EEPROM interface circuitry of block 109. The EEPROM is used for specifying configuration data that is used in setting up Codec 100 operation, Plug-n-Play resource data, and RAM patch data. The EEPROM supports two modes of operation which will be discussed in detail below. The mode identifiers are shown in TABLE 33. FIG. 19 emphasizes the circuitry of the EEPROM interface. Refer to FIG. 20 for a flow chart of a detect/load EEPROM sequence.

The existence and type of EEPROM is determined by two bytes that are located in the first two locations of the EEPROM memory. On power-up Codec 100 looks for the existence of these two bytes via the EEPROM interface. If the first two EEPROM locations are found to contain these matching bytes then Codec 100 will load the EEPROM data into Codec 100 internal memory. How the EEPROM data are interpreted and acted upon is determined by the defined EEPROM mode.

TABLE 33
EEPROM DATA FORMAT IDENTIFICATION WORD
Compatibility Mode 0xAA55
Codec 100 Mode 0xBB55

The first mode of operation assumes that a compatible EEPROM exists. The EEPROM data format for this mode is defined in TABLE 34. The data supports specification of Peripheral Port address length, mapping of interrupt and DMA pins to specific ISA bus lines, and definition of Plug-n-Play resource data. Upon a power-up reset the EEPROM data will be copied into Codec 100 RAM starting at address 0x400C. The additional configuration data needed (0x4000 to 0x400B) will have been copied from ROM defaults to RAM (as the result of a power-on reset) before the EEPROM is detected. The contents of the RAM will then bee used to update the hardware.

TABLE 34
EEPROM
Byte Codec 100
Offset Description Comments Address
0 0x55 EEPROM CS4232 NONE
validation Configuration
1 0Xaa EEPROM Data Type- NONE
validation CS4232, Rev
2 Data length - Length = N − 3 NONE
high byte
3 Data length - (see below for NONE
low byte N)
4 Peripheral Port default = 0x0 0x400C
Address Length
5 Mixer Mapping default = 0x48 0x400D
6 Interrupt default = 0x75 0x400E
Select A/B
7 Interrupt default = 0xB9 0x400F
Select C/D
8 Interrupt default = 0xFC 0x4010
Select E/F
9 DMA Select A/B default = 0x10 0x4011
10  DMA Select C default = 0x3 0x4012
11:18 Plug & Play ID Plug-n-Play 0x4013-
Resource
19:21 Plug & Play Variable
Version
Variable User Defined Variable
ASCII String
Variable Logical Device Variable
Resources
L-1 0x79 End Tag Variable
L Checksum Checksum 0x417F

The Data Length Bytes (2,3) specify the total length of data contained in the EEPROM not including the two validation bytes or the two data length bytes.

The External Peripheral Port I/O Decode Address Length Byte (4) determines which devices connected to the External Peripheral 109 Port may require an I/O decode address length of four or eight:

0x00=I/O Length Four Bytes; and

0x08=I/O Length Eight Bytes

The Mixer Input Mapping Byte (5) (default 0x40) determines what physical devices are connected to the various mixer inputs. TABLE 35 described the available selections.

TABLE 35
D7 D6 D5 D4 D3 D2 D1 D0
LINE IN LINE AUX1 AUX1 AUX2 AUX2 RES RES
IN
Source Device Source Device Source Device Reserved
00 = Line 00 = Line 00 = Line
01 = FM Synth 01 = FM Synth 01 = FM Synth
10 = CD 10 = CD 10 = CD
11 = Other 11 = Other 11 = Other

The Interrupt Selection A,B Bytes (6) determine what physical ISA Bus interrupt pin is connected to the IRQA and IRQB pins of Codec 100. The available connections are shown in TABLE 36.

TABLE 36
D7 D6 D5 D4 D3 D2 D1 D0
Codec 100 IRQB Pin Codec 100 IRQA Pin
0000 = No Connection 0000 = No Connection
0001 = ISA Bus IRQ1 0001 = ISA Bus IRQ1
0010 = ISA Bus IRQ2 0010 = ISA Bus IRQ2
0011 = ISA Bus IRQ3 0011 = ISA Bus IRQ3
0100 = ISA Bus IRQ4 0100 = ISA Bus IRQ4
0101 = ISA Bus IRQ5 0101 = ISA Bus IRQ5
0110 = ISA Bus IRQ6 0110 = ISA Bus IRQ6
0111 = ISA Bus IRQ7 0111 = ISA Bus IRQ7
1000 = ISA Bus IRQ8 1000 = ISA Bus IRQ8
1001 = ISA Bus IRQ9 1001 = ISA Bus IRQ9
1010 = ISA Bus IRQ10 1010 = ISA Bus IRQ10
1011 = ISA Bus IRQ11 1011 = ISA Bus IRQ11
1100 = ISA Bus IRQ12 1100 = ISA Bus IRQ12
1101 = ISA Bus IRQ13 1101 = ISA Bus IRQ13
1110 = ISA Bus IRQ14 1110 = ISA Bus IRQ14
1111 = ISA Bus IRQ15 1111 = ISA Bus IRQ15

C,D, Byte (7) determines what physical ISA Bus interrupt pin is connected to the IRQC and IRQD pins of Codec 100. TABLE 37 shows the possible connections.

TABLE 37
D7 D6 D5 D4 D3 D2 D1 D0
Codec 100 IRQD Pin Codec 100 IRQC Pin
0000 = No Connection 0000 = No Connection
0001 = ISA Bus IRQ1 0001 = ISA Bus IRQ1
0010 = ISA Bus IRQ2 0010 = ISA Bus IRQ2
0011 = ISA Bus IRQ3 0011 = ISA Bus IRQ3
0100 = ISA Bus IRQ4 0100 = ISA Bus IRQ4
0101 = ISA Bus IRQ5 0101 = ISA Bus IRQ5
0110 = ISA Bus IRQ6 0110 = ISA Bus IRQ6
0111 = ISA Bus IRQ7 0111 = ISA Bus IRQ7
1000 = ISA Bus IRQ8 1000 = ISA Bus IRQ8
1001 = ISA Bus IRQ9 1001 = ISA Bus IRQ9
1010 = ISA Bus IRQ10 1010 = ISA Bus IRQ10
1011 = ISA Bus IRQ11 1011 = ISA Bus IRQ11
1100 = ISA Bus IRQ12 1100 = ISA Bus IRQ12
1101 = ISA Bus IRQ13 1101 = ISA Bus IRQ13
1110 = ISA Bus IRQ14 1110 = ISA Bus IRQ14
1111 = ISA Bus IRQ15 1111 = ISA Bus IRQ15

The Interrupt Selection E,F, Byte (8) determines what physical ISA Bus interrupt pin is connected to the IRQD and IRQE pins of Codec 100. The possible connections are described in TABLE 38.

TABLE 38
D7 D6 D5 D4 D3 D2 D1 D0
Codec 100 IRQB Pin Codec 100 IRQA Pin
0000 = No Connection 0000 = No Connection
0001 = ISA Bus IRQ1 0001 = ISA Bus IRQ1
0010 = ISA Bus IRQ2 0010 = ISA Bus IRQ2
0011 = ISA Bus IRQ3 0011 = ISA Bus IRQ3
0100 = ISA Bus IRQ4 0100 = ISA Bus IRQ4
0101 = ISA Bus IRQ5 0101 = ISA Bus IRQ5
0110 = ISA Bus IRQ6 0110 = ISA Bus IRQ6
0111 = ISA Bus IRQ7 0111 = ISA Bus IRQ7
1000 = ISA Bus IRQ8 1000 = ISA Bus IRQ8
1001 = ISA Bus IRQ9 1001 = ISA Bus IRQ9
1010 = ISA Bus IRQ10 1010 = ISA Bus IRQ10
1011 = ISA Bus IRQ11 1011 = ISA Bus IRQ11
1100 = ISA Bus IRQ12 1100 = ISA Bus IRQ12
1101 = ISA Bus IRQ13 1101 = ISA Bus IRQ13
1110 = ISA Bus IRQ14 1110 = ISA Bus IRQ14
1111 = ISA Bus IRQ15 1111 = ISA Bus IRQ15

The DMA Selection A,B Byte (9) determines what physical pair of ISA Bus DMA pins are connected to the DRQA, DRQB and DACKA, DACKB pins of Codec 100. TABLE 39 describes the available connections.

TABLE 39
D7 D6 D5 D4 D3 D2 D1 D0
Codec 100 DRQB, DACKB Codec 100 DRQA, DACKA
Pins Pins
0000 = DMA Channel 0 0000 = DMA Channel 0
0001 = DMA Channel 1 0001 = DMA Channel 1
0010 = DMA Channel 2 0010 = DMA Channel 2
0011 = DMA Channel 3 0011 = DMA Channel 3
0100:1111 No 0100:1111 = No
Connection Connection

The DMA Selection C Byte (A) determines what physical pair of ISA Bus DMA pins are connected to the DRQA, DRQB and DACKA, DACKB pins of Codec 100. TABLE 40 describes the available connections.

TABLE 40
D7 D6 D5 D4 D3 D2 D1 D0
Reserved Codec 100 DRQC, DACKC Pins
0000 = DMA Channel 0
0001 = DMA Channel 1
0010 = DMA Channel 2
0011 = DMA Channel 3
0100:1111 = No Connection

Bytes 11 through L are reserved for Plug-n-Play resource data. The format of the Plug-n-Play data are described above.

Codec 100 EEPROM resource data format for the second mode in TABLE 33 is shown in TABLE 41. The data is copied into Codec 100 RAM memory and the hardware will be updated based on the stored RAM values. The identification word for this format is 0xBB55.

TABLE 41
EEPROM DATA FORMAT
EEPROM
Byte CS4237B
Offset Description Comments Address
 0 0x55 EEPROM CS4237B NONE
validation Configuration
Data
 1 0xBB, EEPROM Data Type - NONE
validation CS4237B
 2 Data length - high Length = N-3 NONE
byte
 3 Data length - low (see below for N) NONE
byte
 4 Address Mask default = 0x0 0x4000
Register -
Alternate CDROM
base address
 5 Address Mask default = 0x3 0x4001
Register - Modem
 6 Miscellaneous HW default = 0x80 0x4002
Configuration Bits
 7 Reserved default = 0x0 0x4003
 8 Device 0 Mapping - default = 0x43 0x4004
Not Supported
 9 Device 1 Mapping - default = 0x20 0x4005
Not Supported
10 Device 2 Mapping - default = 0x04 0x4006
Not Supported
11 Device 3 Mapping - default = 0x08 0x4007
Not Supported
12 Device 4 Mapping - default = 0x10 0x4008
Not Supported
13 Device 5 Mapping - default = 0x80 0x4009
Not Supported
14 Device 6 Mapping - default = 0x0 0x400A
Not Supported
15 Device 7 Mapping - default = 0x0 0x400B
Not Supported
16 Peripheral Port default = 0x0 0x400C
Address Length
17 Mixer Mapping default = 0x48 0x400D
18 Interrupt Select default = 0x75 0x400E
A/B
19 Interrupt Select default = 0xB9 0x400F
C/D
20 Interrupt Select default = 0xFC 0x4010
E/F
21 DMA Select A/B default = 0x10 0x4011
22 DMA Select C default = 0x03 0x4012
23:31 Plug & Play ID Plug n Play 0x4013-
Resource Data
32:34 Plug & Play Variable
Version
Variable User Defined ASCII Variable
String
Variable Logical Device Variable
Resources
L-1 0x79 End Tag Variable
L Checksum Checksum 0x417F
max
L+1 Optional PATCH 0x4180
RAM DATA
N Optional PATCH 0x43FD
RAM DATA max

The fields of address mask register/alternate CDROM base address register (Byte 4) is depicted in FIG. 21A. The CDROM Address Mask Register provides a means to vary the number of consecutive byte locations that the secondary CDROM I/O decode may occupy. Each mask bit is used to prevent specific address bits from being decoded in generating the secondary CDROM I/O decode. The valid bit combinations are as shown in TABLE 42. All other combinations are invalid and may cause erroneous operation.

TABLE 42
AMC2 AMC1 AMCO CDROM Decode = number of consecutive
bytes
1 1 1 8 bytes, address bits A2, A1, A0 are don't
cares.
0 1 1 4 bytes, address bit A2 is decoded. Bits A2,
A0 are don't cares.
0 0 1 2 bytes, address bits A2 and A1 are decoded.
Bit A0 is a don't care.
0 0 0 1 byte, address bits A2, A2, A0 are all
decoded.

The bitfields of Address Mask Register Modem (Byte 5) are shown in FIG. 21B. The Modem Address Mask Register provides a means to vary the number of consecutive byte locations that the modem decode may occupy. Each mask bit is used to prevent specific address bits from being decoded in generating the modem I/O decode. The valid bit combinations are as shown in TABLE 43. All other combinations are invalid and may cause erroneous operation.

TABLE 43
AMM[7:0] Modem Decode = number of consecutive bytes
11111111 256 bytes, address bits A[7..0] are don't
cares.
01111111 128 bytes, address bit A7 is decoded. Bits
A[6..0] are don't cares.
00111111 64 bytes, address bits A7 and A6 are
decoded. Bits A[5..0] are don't cares.
00011111 32 bytes, address bits A[7..5] are decoded.
Address bits A[4..0] are don't cares.
00001111 16 bytes, address bits A[7..4] are decoded.
Address bits A[3..0] are don't cares.
00000111 8 bytes, address bits A[7..3] are decoded.
Address bits A[2..0] are don't cares.
00000011 4 bytes, address bits A[7..2] are decoded.
Address bits A[1..0] are don't cares.
00000001 2 bytes, address bits A[7..1] are decoded.
Address bits A[0] is a don't care.
00000000 1 byte, address bits A[7..0] are decoded.

The Miscellaneous Configuration Bits, Byte 6, are shown in FIG. 21C.

PCDINT—Polarity CDROM Interrupt bit specifies polarity of CDROM interrupt input:

0=CDROM interrupt is active low; and

1=CDROM interrupt is active high.

PSINT—Polarity Synthesizer Interrupt bit specifies polarity of synthesizer interrupt input:

0=synthesizer interrupt is active low; and

1—synthesizer interrupt is active high.

CKD—Crystal Key Disable bit controls response of Codec 100 to the Crystal Key Sequence:

CKD 0=Enable—Codec 100 will Respond to Crystal Key; and

PKD 1=Disable—Codec 100 will NOT Respond to Crystal Key.

PKD—Plug-n-Play Key Disable bit controls response of Codec 100 to the PnP Key Sequence:

PKDO=Enable—Codec 100 will Respond to Pnp Key; and

PKD1=Disable—Codec 100 will NOT Respond to PnP Key.

RES—Reserved, always defined as zero (0);

PMINT—Polarity Modem Interrupt bit specifies polarity of modem interrupt input:

0=modem interrupt is active low; and

1=modem interrupt is active high.

XBUF—Transceiver buffer control:

XBUF=0CS4232 drives data bus on reads of CDROM addresses; and

XBUF=I CS4232 tri-states data bus on reads of CDROM addresses.

SD7DE—SD7 Disable:

SD7DE 0−SD7-SDO driven during reads of CDROM Alternate Base +1; and

SD7DE 1=SD7 tri-stated, SD6-SDO driven during reads of CDROM Alternate Base +1.

FIG. 21D defines the bitfields of the Misc. Configuration Bits, Byte 7. This byte is copied to microcontroller 103 addresses 0x4002 on powerup and 0x34 on powerup or PNP_UPDATE command.

VCEN—Volume Control Enable—This bit is copied to the corresponding VCEN bit in microcontroller 103 register 0x34. The Firmware also uses this bit to enable up/down/mute external pushbutton volume control.

The Global Configuration Byte,Byte 8 is depicted in FIG. 21E and is copied to 0x4003 on powerup. The actions taken based on the data in this byte occur at powerup in the EEPROM case and during a PNP_UPDATE command in the case of a host resource data shoot. NOTE: All defined bits other than D3 and D2 in register 0x40 are preserved. The bit decoding is as follows:

Reserved—These bits are reserved for future use and should be set to zero;

SPS—Serial Port Switch—This bit is copied to the corresponding SPS bit in microcontroller 103 register 0x40;

WTEN—Wave Table Enable—This bit is copied to the corresponding WTEN bit in microcontroller 103 register 0x40;

AIDIS—Alternate Input Disable—This bit, when set, will cause SB initiated writes to registers I18, I19 to NOT be mapped to X0, X1 if IFM or WTEN are set;

VCF0—This bit, along with the VCF1 bit, is used to specify which volume control button scheme is used;

VCF1—This bit, along with the VCF0 bit, is used to specify which volume control button scheme is used; and

IFM—When this bit is set to a one the internal FM synthesizer is enabled.

Firmware Revision information bytes are used by the host to identify which patch is present in the part and what patch options are set.

Features Byte indicates major feature sets of the embedded microcode. Each bit in this byte represents a feature or feature set.

Firmware REVISION at 0x41BE byte indicates the current revision of the embedded microcode patch and is written 0x22 on powerup.

The Logical-to-Physical Device Mapping, Bytes 8-15, are used to map Logical Devices to Physical Devices. Each Logical Device has a byte associated with it. To map physical devices into a particular logical device a one is programmed into the corresponding bit location. TABLE 44 defines the mapping. The physical device bits are mapped the same as the Physical Device Activation register. As an example, to define Logical Device 0 as Sound System/Sound Blaster/Synth, Byte 0 should be written as a 0x43 to mapped the three physical devices to Logical Device 0.

TABLE 44
D7 D6 D5 D4 D3 D2 D1 D0 Logical Device Default Byte Offset
Modem SB Game CD MPU CTRL Synth WSS 0 0x43 0
Modem SB Game CD MPU CTRL Synth WSS 1 0x20 1
Modem SB Game CD MPU CTRL Synth WSS 2 0x04 2
Modem SB Game CD MPU CTRL Synth WSS 3 0x08 3
Modem SB Game CD MPU CTRL Synth WSS 4 0x20 4
Modem SB Game CD MPU CTRL Synth WSS 5 0x80 5
Modem SB Game CD MPU CTRL Synth WSS 6 0x00 6
Modem SB Game CD MPU CTRL Synth WSS 7 0x00 7

Codec 100 EEPROM may also optionally include RAM patch data starting at offset L+1 and continuing to N (max=0x43FD).

Because all implementations of Codec 100 will require either a host resource load or EEPROM, the default (ROM) resource data and configuration has been minimized to save code space and therefore does not contain a full set of Plug-n-Play resource data. However, without an EEPROM, using the default ROM data, Codec 100 will still be able to participate in a PnP or Crystal Key sequence but will have no resource data to report. An example of this feature follows:

Codec 100 ROM RESOURCE DATA
; ** BEGIN Codec 100 RESOURCE DATA
NEW_KEY:
; EEPROM Validation Bytes
DB 055H, 0BBH ; EEPROM Validation Bytes
DB 000H ; EEPROM data length upper byte
DB 02CH ; lower byte, Listed Size of Resource =
44
USER_DATA:
; Hardware Configuration Data (Resource Header)
DB 000H ; Address Mask - CDROM
DB 003H ; Address Mask - Modem
DB 080H ; Misc Config bits
DB 000H ; Reserved
DB 043H ; Reserved
DB 020H ; Reserved
DB 004H ; Reserved
DB 008H ; Reserved
DB 010H ; Reserved
DB 080H ; Reserved
DB 000H ; Reserved
DB 000H ; Reserved
DB 000H ; 00 = 4/08 = 8 peripheral port size,
XCTL0/XA2
DB 048H ; LINE, AUX1, AUX2 mapping - RESERVED
DB 075H ; IRQ selection A & B - B = 7, A = 5
DB 0B9H ; IRQ selection C & D - D = 11, C = 9
DB 0FCH ; IRQ selection E & F - F = 15, E = 12
DB 010H ; DMA selection A & B - B = 1, A = 0
DB 003H ; DMA selection C - C = 3
; PnP Resource Header - Starts with Crystal PnP ID for Codec 100
IC
DB 00EH, 063H, 0A2H, 032H, 0FFH, 0FFH, 0FFH, 0D4H ;
CSCS 232 FFFFFFFF
DB 00AH, 010H, 002H ; PnP version 1.0, Vender version 0.2
DB 082H, 008H, 000H, ‘Codec 100’, 000H ; ANSI ID
DB 079H, ; End of Resource Data, Checksum
03fH
; ** END Codec 100 RESOURCE DATA

As shown in FIG. 19, Codec 100 interfaces to an external EEPROM device via Peripheral Port Interface 109. The acutal pins used are as follows. The XD0 pin connects to the EEPROM data pin and the XA0 pin connects to the EEPROM address pin. To XD0 pin is open-collector and therefore requires a 5K pull-up resistor. The interface is designed to be compatible with a variety of EEPROM devices that are I2C compatible.

The EEPROM is accessible via microcontroller 103 microcontroller and directly via the ISA bus via multiplexer 1901 and read drivers 1902.

Microcontroller 103 access to the EEPROM is enabled via the EPP bit in the Plug-n-Play Control/Status Register (microcontroller 103 address=0x14). When the EPP bit is equal to one microcontroller 103 Port 1 pins 6 and 7 are enabled onto the XD0 and XA0 pins respectively. The only time in which microcontroller 103 enables access to the EEPROM is after a Codec 100 reset (RESDRV=1 or PD1, PD0=10). In this instance, as part of a initialization sequence, microcontroller 103 checks for the existence of an EEPROM device. If a compatible EEPROM is found then its contents are loaded into Codec 100. Microcontroller 103 only reads EEPROM devices it does not have the ability to write EEPROM devices. Writing of the EEPROM is accomplished by using the ISA Bus EEPROM access port via Codec 100 Control Base +1 register. The timing of the data and clock signals are determined by microcontroller 103 ROM code. The timing relationship between the clock and data are shown in FIG. 22A. The state of the data line can change only when the clock line is low. A state change of the data line during the time that the clock line is high is used to indicate start and stop conditions.

Codec 100 supports a single EEPROM up to 2K bytes. EEPROM device read access is shown in FIG. 22B. The timing follows that of a random read sequence. Prior to issuing the slave address with the R/W bit set to a one, Codec 100 first performs a “dummy” write operation. Codec 100 first generates a start condition followed by the slave device address and the byte address of zero. The slave address is made up of a device identifier (0xA) and a bank select (bits A2 . . . A0) which are always zero. Codec 100 always begins access at byte address zero and continues access a byte at a time. The byte address automatically increments by one until a stop condition is detected.

ISA Bus access to the EEPROM is enabled via the DATAIN bit in Codec 100 Control Base+1 register. When the DATAIN bit is set to a one then the CLOCK and DATAOUT bits are enabled on to the XA0 and XD0 pins respectively. The timing of the clock and data signals is completely determined by the host based software program and should be the timing requirements shown in FIG. 28. It should be noted that in order to read back data from the EEPROM device, the DATAOUT bit must be set to a one.

Sound Blaster

The Sound Blaster/MPU-401 to microcontroller 103 interface 2300 is shown in FIG. 23A and consists of a number of data latches 2301 and transceivers 2302 that are used to send and receive data between ISA bus 130 and microcontroller 103. The particular ISA Bus base I/O addresses, as defined by the Plug & Play configuration data, are decoded by ISA address decoder 2303. When a ISA Bus generated read/write occurs to a Sound Blaster or MPU-401 device then an interrupt (active low) is generated on the INT1 TRO input of microcontroller 103. At the same time the ISA Bus IOCHRDY line is driven low to force the current ISA BUS cycle to wait. Data are put on PORT1 to indicate to microcontroller 103 what ISA Bus access has generated the interrupt microcontroller 103 then performs a read or write of the ISA Data Port depending on the current cycle type (read/write). The trailing edge of microcontroller 103 read/write strobe tri-states (releases) the IOCHRDY line and the current ISA cycle is allowed to complete.

It is not required in all cases for microcontroller 103 to access the ISA Data Port immediately after receiving an interrupt. Microcontroller 103 may perform a number of processing tasks, while IOCHRDY holds off the ISA Bus, before the access to the ISA Data Port occurs which releases IOCHRDY. However the amount of time in which IOCHRDY is asserted should be keep to a minimum to minimize the impact on system performance.

The Plug & Play block 106 maps the Sound Blaster functions into the ISA environment. The Sound Blaster I/O map is shown in TABLE 45:

TABLE 45
I/O Address Base + Description Type
0 Left FM Status Read
0 Left FM Register Address Write
1 Left FM Data Write
2 Right FM Status Read
2 Right FM Register Address Write
3 Right FM Status Read
4 Mixer Register Address Write
5 Mixer Data port Read/Write
6 Reset DSP Write
6 Reserved - Read back as 0xFF Read
7 Reserved - Read back as 0xFF Read
8 FM Status Read
8 FM Register Address Write
9 FM Data Write
0xA DSP Read Data Port Read
0xB DSP Read Data Port Read
0xC DSP Command/Write Write
0xC DSP Write Buffer Status (Bit 7) Read
DSP Read Data Port bits 6 . . . 0
0xD DSP Command/Write Write
0xD DSP Write Buffer Status (Bit 7) Read
DSP Read Data Port bits 6 . . . 0
E Data Available Status (Bit 7) Read
DSP Read Data Port bits 6 . . . 0
F Data Available Status (Bit 7) Read
DSP Read Data Port bits 6 . . . 0

The FM registers addresses 0-3 and 8-9 are maps to a synthesizer connected externally to Codec 100 via the External Peripheral Port 109. The Mixer Address and Data registers are mapped into the codec mixer by microcontroller 103. The DSP registers are used to send/receive Sound Blaster commands and data from microcontroller 103. Addresses 0xB, 0xD, and 0xF are aliases from addresses 0xA, 0xC, and 0xE respectively. Unused bits (6 . . . 0) at addresses 0xC, 0xD, 0xE, and 0xF are mapped to bits 6 . . . 0 in latch at address 0xA, B.

The Sound Blaster digital audio DMA functions are supported by the Windows Sound System codec (external to Codec 100). It should be noted that in the Sound Blaster mode (via a context switch) Codec 100 swaps the left right samples in the codec (capture and playback) so that they match the Sound Blaster standard.

The Sound Blaster mixer functions are mapped into codec mixer 204. This mapping is illustrated in FIG. 31 and TABLE 46.

TABLE 46
Register D7 D6 D5 D4 D3 D2 D1 D0
00H DATA RESET
02H RESERVED
04H VOICE VOLUME LEFT VOICE VOLUME RIGHT
06H RESERVED
08H RESERVED
0AH X X X X X MIC MIXING
0CH X X X INPUT X
SELECT
0EH X X DNF1 X X X VSTC X
20H RESERVED
22H MASTER VOLUME LEFT MASTER VOLUME RIGHT
24H RESERVED
26H FM VOLUME LEFT FM VOLUME RIGHT
28H CD VOLUME LEFT CD VOLUME RIGHT
2AH RESERVED
2CH RESERVED
2EH LINE VOLUME LEFT LINE VOLUME RIGHT

The mixer data are buffered by microcontroller 103 into internal memory. Then, during a time in which Codec 100 is holding the ISA bus via IOCHRDY, the appropriate codec mixer writes are done to affect the mixer change. This is done because microcontroller 103 cannot access the codec registers while DMA audio is being transferred to the codec 100. While IOCHRDY is asserted DMA activity to codec 100 is suspended and the Sound Blaster mixer registers are shadowed by microcontroller 103. The Input Filter, DNF1, and VSTC (mono/stereo) bits do not have a CS4231 codec equivalent function and therefore are don't cares.

Sound Blaster Mixer accesses operate as follows:

Mixer Write

1. An ISA Bus write occurs to Sound Blaster Mixer Address Register (Base +5);

Codec 100 drives IOCHRDY low to hold bus. Data are put on PORT1 and a microcontroller 103 interrupt is generated;

microcontroller 103 reads the ISA Data Port (External RAM address=0) and stores address value in local memory; and

IOCHRDY is released and the ISA Bus cycle completes.

2. An ISA Bus write occurs to Sound Blaster Mixer Data Register (Base +6);

Codec 100 drives IOCHRDY low to hold bus, data are put on PORT1 and a microcontroller 103 interrupt is generated;

microcontroller 103 reads ISA Data Port (External RAM address=0) and stores data value in local memory; and

IOCHRDY is released and the ISA Bus cycle completes.

3. Microcontroller 103 then writes codec 100 registers to perform mixer function that was specified.

Mixer Read

1. An ISA Bus write occurs to Sound Blaster Mixer Address Register (Base +5);

Codec 100 drives IOCHRDY low to hold bus, data are put on PORT1, and a microcontroller 103 interrupt is generated;

microcontroller 103 reads ISA Data Port (External RAM address=0) and stores addressed value in local memory; and

IOCHRDY is released and the ISA Bus cycle completes.

2. An ISA Bus read occurs to Sound Blaster Mixer Data Register (Base +6);

Codec 100 drives IOCHRDY low to hold bus, data are put on PORT1, and microcontroller 103 interrupt is generated;

microcontroller 103 writes Mixer Data Latch (External RAM address=0) with shadow Sound

Blaster mixer register contents; and

IOCHRDY is released and the ISA Bus cycle completes.

Sound Blaster interface 2300 further includes uses a hardware handshake mechanism 2304 for processing commands. The mixer does not use a handshake mechanism and is always assumed to be available for ISA bus accesses. Two handshake bits are used: Command Busy, and Data Available. The Command Busy is located in the Write Buffer Status Register (bit 7). The Data Available bit is located in the Data Available Status Register (bit 7). The Command Busy bit indicates when microcontroller 103 is busy processing a command. The Data Available bit is used to indicate when microcontroller 103 has responded to a command with some data. The handshake works as follows:

1. The Command Busy bit is generated by the logical OR of two independently controlled microcontroller 103 accessible bits; SB_BUSY1 and SB_BUSY 2;

Writes to the Sound Blaster Command Register (SB_Base+C) immediately set the Command Busy bit (via SB_BUSY 1);

Microcontroller 103 reads and processes the command. Once the command is processed, a read of the Sound Blaster Data Register (External RAM address 0x01), by microcontroller 103, will clear this bit. This bit is set to a 1 on a reset (RESDRV); and

Writes to the Sound Blaster Reset Register (SB_Base +6) with a D0 value of one immediately sets the Command Busy bit (via SB_BUSY 2). Microcontroller 103 processes the reset command and clears the Command Busy bit by executing a write of microcontroller 103 address 0x8.

2. When microcontroller 103 writes data to the SB Data Register (microcontroller 103 External RAM address 0x02) the Data Available bit is set to a one. This bit is cleared once the Read Data Port (Sound Blaster base address+A) is read via the ISA bus. This bit defaults to 0 on reset.

Codec 100 supports Sound Blaster ADPCM 2:1, 3:1, and 4:1 decompression. When a ADPCM byte is transferred to Codec 100 via DMA, an interrupt is generated to microcontroller 103 via input TRO, and the data are latched. Microcontroller 103 is then able to read the data from the latch by reading from memory location 0xC.

The Sound Blaster RESET command is generated by writing a one to register index 6 and then writing index register 6 to a zero. In Codec 100 hardware detects the zero-one-zero transition and interrupts microcontroller 103 on the one-to-zero transition. The interrupt is acknowledged by microcontroller 103 reading the ISA Data Latch.

In addition,to the standard codec DMA request generation the Sound Blaster hardware has the capability of generating a DMA request via a number of commands. In Codec 100 microcontroller 103 detects these commands and writes microcontroller 103 External RAM address 0xE. The Sound Blaster hardware senses this write and generates a DMA Request on the ISA Bus. In addition microcontroller 103 may write a byte to the Sound Blaster Data Latch depending on which command is being responded to. The ISA Bus will in turn generate a DMA Acknowledge. If the DMA acknowledge is a read then the DMA request is cleared and the data that was written to the Sound Blaster Data Latch is put onto the ISA data bus. If the DMA acknowledge is a write then an interrupt is generated to microcontroller 103 microcontroller via INT1 and the data present on the ISA Data Bus is written into the Sound Blaster ADPCM Data Latch with the trailing edge of the IOW strobe. The leading edge of the IOW strobe clears the DMA Request. Microcontroller 103 responds to the interrupt by reading the Sound Blaster ADFCM Data Latch (microcontroller 103 address 0x0C).

In addition the Sound Blaster hardware may generate its own interrupt. This is accomplished by microcontroller 103 writing to External RAM address 0xFH which will generate an interrupt on the ISA bus. The Sound Blaster interrupt is cleared when a read from Sound Blaster Data Available Register (index 0xE). The MPU-401 has become the defacto standard for controlling MIDI devices via IBM-PC compatible personal computers.

A MPU401 logical device interface occupies 2 I/O locations and utilizes 10-bit address decoding. The standard base address is 330h. This device also requires an interrupt, typically 9.

Codec 100 implements the UART mode of the MPU-401 functionality. This mode is used to send and receive MIDI data to and from the host computer and a external MIDI device through interface 104. MPU-401 Interface 104 consists of two registers (Command/Status Register, Transmit/Receive Register) that are mapped into the host I/O space. MPU-401 interface 104 is idle until a Enter UART Mode command is written to the Command register. Once UART mode is entered, MIDI data are written to or read from the Transmit/Receive register a byte at a time. Microcontroller 103 stores the data in separate receive and transmit FIFO's. Each transfer of a byte into the receive FIFO should generate an interrupt to the host computer.

The Transmit (TXD) and Receive (RXD) pins of microcontroller 103 UART should connect to the MIDI OUT and MIDI IN pins respectively. After power-up reset, the interface is in “non-UART” mode. Non-UART mode operation is defined as follows:

1. All writes to the Transmit Port, MPUbase+0, are ignored;

2. All reads of the Receive Port, MPUbase+0, return the last received buffer data; and

3. All writes to the Command Port, MPUbase+1, are monitored and acknowledged as follows:

a. A write of 3Fh sets the interface into UART operating mode. An acknowledge is generated by putting an FEh into the receive buffer FIFO which generates an interrupt;

b. A write of A0-A7, ABh, ACh, ADh, AFh places an FEh into the receive buffer FIFO (which generates an interrupt) followed by a one byte write to the receive buffer FIFO of 00h for A0-A7, and ABh commands, 15h for ACh, 01h for ADh, and 64h for AFh commands; and

c. All other writes to the Command Port are ignored and an acknowledge is generated by putting an FEh into the receive buffer FIFO which generates an interrupt.

UART mode operation is defined as follows:

1. All writes to the Transmit Port, MPUbase+0, are placed in the transmit buffer FIFO. Whenever the transmit buffer FIFO is not empty, the next byte is read from the buffer and sent out the MIDOUT pin.

The Status Register, MPUbase+1, bit 6, TXS is updated to reflect the transmit buffer FIFO status;

2. All reads of the Receive Port, MPUbase+0, return the next byte in the receive buffer FIFO. When serial data are received from the MDIN pin, it is placed in the next receive buffer FIFO location. If the buffer is full, the last location is overwritten with the new data. The Status Register, MPUbase+1, bit 7, RXS is updated to reflect the new receive buffer FIFO state;

3. A write to the Command Register, MPUbase+1, of FFh will return the interface to non-UART mode; and

4. All other writes to the Command Register, MPUbase+1, are ignored.

MPU-401 interface 104 also uses a hardware handshake mechanism. The MPU-401 interface incorporates receive and transmit FIFO's implemented by microcontroller 103. External handshake bits indicate to the host the current FIFO status. The two handshake bits are as follows: Transmit FIFO Full Flag, and Receive Buffer Empty Flag. The status of both flags is output onto the ISA bus in response to a read of the MPU Commands/Status Register (MPU-401 base address +1). The flags function as follows:

1. Transmit FIFO Full Flag is set when a ISA write cycle occurs to the MPU-401 Transmit/Receive Data Port or the Command/Status Register. This flag is reset when a microcontroller 103 read of the MPU Data Register (External RAM address=0x02) occurs; and

2. Receive Buffer Empty Flag is set to one when an ISA read cycle occurs to the Transmit/Receive Data Port. This flag is reset to zero when microcontroller 103 performs a write to the MPU Data Register (External RAM address=0x02). This write also generates an interrupt on ISA bus. When an ISA Bus read of the Transmit/Receive Register occurs the interrupt will be cleared.

TABLES 47A-47E summarize the Sound Blaster/MPU 401 Hardware Interface Definition and Protocol.

TABLE 47A
Control Base +0
Definition
Context Switching support with
host assistance.
CONSW. (0) Host does not assist in
context-switches; Interrupt
does not get generated upon
context-switch.
(1) Interrupt will get
generated upon
context-switch in order for
host to assist in the
switch.
Context Switching support without host assistance.
When host goes from using SB
interface to using WSS interface,
hardware generates
microcontroller 103 interrupt
with Port 1 = pContextSw1.
Microcontroller 103 will
acknowledge this interrupt by
reading the ISA data register
(0H0).

TABLE 47B
PC DREQ generation.
SB When microcontroller 103 writes data to the
SB DMA register (OEH), the hardware will
drive SB DREQ high.
If the following DACK is part of a DMA write
transfer (memory write/IO read), then the
data in the SB DMA register (OEH) will be
read. This mechanism is needed to help
support SB command 0E2H.
If the following DACK is part of a DMA read
transfer (memory read/IO write), then
microcontroller 103 will be interrupted.
Microcontroller 103 gets the data being
transferred by reading the ISA data register
(OH). This also acknowledges the interrupt.
This mechanism is needed to help support
microcontroller 103 decode of DB ADPCM data.
Six Status Bits. This six status bits described below can be
read by the 8052 from external 8052 address
0x3. Reading this register does not affect
ISA bus accesses to the 4231 codec.
Definition
SB_BUSY 1. Set when host writes Internal Bit
SB COMMAND/DATA port.
Cleared by 8052 dummy
read of SB data
register (1H)
SB_BUSY 2 Set when host writes Internal Bit
a one to the SB base
+6 port. Cleared by
8052 dummy write of
the 8052 address 08H
SB WRITE BUSY Logical OR of (0) Ready for write
SB_BUSY1, SB_BUSY2 to SB
COMMAND/DATA
port.
(1) Not ready for
write to SB
COMMAND/DATA
port.
SB DATA Cleared when host (0) Read from SB
AVAILABLE. reads SB READ DATA READ DATA port
port. Set when 8052 will not return
writes SB data valid data.
register (1H) (2) Read from SB
READ DATA port
will return
valid data.
MPU-401 TXS. Set when host writes (0) Ready for write
MPU-401 COMMAND or to MPU-401 DATA
DATA port. Cleared port or MPU-401
by 8052 dummy read of COMMAND port.
MPU-401 data register (1) Not ready for
(2H) write to
MPU-401 DATA
port or MPU-401
COMMAND port.
MPU-401 RXS. Set when host reads (0) Read from SB
MPU-401 DATA port. READ DATA port
Cleared when 8052 will return
writes MPU-401 data valid data.
register (2H) (1) Read From SB
READ DATA port
will not return
valid data.
CODEC Set when codec DMA (0) No interrupt
INTERRUPT counter reaches pending.
terminal count. (1) Interrupt
pending.
ADPCM Set when the Sound (0) Data not valid
Blaster ADPCM data (1) Data Valid.
latch is written via
the ISA Bus

TABLE 47C
Five 8052 data Registers.
ISA data Read by 8052 in response to interrupt caused
register (OH) by write to SB (Pro) or MPU-401. Written by
8052 in response to SB Pro Mixer Data
Register read.
SB data Written by 8052 when SB data are available;
register (1H) causes SB DATA AVAILABLE status bit to be
set.
Dummy read of this register clears SB WRITE
BUSY status bit.
SB DMA register Written by 8052 when SB DMA data are
(OEH) available in response to SB Table Munge
command. This particular 8052 write will
also cause a SB DREQ.
MPU-401 data Written by 8052 when MPU-401 data are
register (2H). available; causes MPU-401 RXS status bit to
go low which causes MPU-401 IRQ to go high.
Dummy reads of this register clears MPU-401
TXS bit.
SB ADPCM data Written by ISA bus Sound Blaster DMA cycle.
register (0CH)

TABLE 47D
Responses to the following Sound Blaster/MPU-401 cycles.
Write to SB DSP Hardware detects valid SB DSP Reset sequence;
RESET port. i.e., write 1 to SB DSP RESET port, delay of
at least 3 us, write 0 to SB DSP RESET port,
and then interrupts the 8052.
8052 acknowledges interrupt by reading the
ISA data register (OH).
Write to SB Hardware interrupts 8052 via INT1 8052
COMMAND/DATA acknowledges interrupt by reading the ISA
port. data register (OH).
Read from SB Hardware brings or keeps SB DATA AVAILABLE
READ DATA port. status bit low; no 8052 interrupt required.
Read from SB Hardware brings or keeps SB IRQ low; no 8052
DATA interrupt required unless CODEC INT is active
AVAILABLE in which case hardware interrupts 8052 and
port. 8052 acknowledges by reading the ISA data
register (OH).
Write to SB Pro Hardware interrupts 8052 via INT1. 8052
Mixer Address acknowledges interrupt by reading ISA data
Register. register (OH).
Write to SB Pro Hardware interrupts 8052 via INT1. 8052
Mixer Data acknowledges interrupt by reading ISA data
Register. register (OH).
Read from SB Hardware interrupts 8052 via INT1. 8052
Pro Mixer Data acknowledges interrupt by writing ISA data
Register. register (OH).
ISA Bus DMA Hardware interrupts 8052 via TR0. 8052
write to SB acknowledges interrupt by reading ADPCM data
ADPCM data register (0CH).
register
Write to Hardware interrupts 8052 via INT1. 8052
MPU-401 DATA acknowledges interrupt by reading ISA data
port. register (OH).
Read from Hardware brings or keeps MPU-401 RXS bit
MPU-401 DATA high; no 8052 interrupt required.
port.
Write to Hardware interrupts 8052 via INT1. 8052
MPU-401 acknowledges interrupt by reading ISA data
COMMAND port. register (OH).

FIGS. 24A-24L are diagrams of the bitfields of the Sound Blaster/MPU-401 registers.

FIG. 24A is a diagram of the ISA DATA READ/MIXER LATCH register at microcontroller address 0x00. This microcontroller 103 address location is read by microcontroller 103 in response to a ISA bus write cycle to the Sound Blaster DSP Command Register, Mixer Address Register, Mixer Data Register, or the MPU-401 Command Register. When microcontroller 103 read strobe is low, ISA bus data is enabled onto microcontroller 103 XDB[7:0] bus (FIG. 3). A write to this location occurs in response to read from the Mixer Data Port. The write strobe of microcontroller 103 is used to clock the data from XDB[7:0] into a latch. The output from the latch is then enabled onto the ISA data bus where it is read.

FIG. 24B is a diagram of the bitfields of the Sound Blaster Data Latch register at microcontroller address 0x01. This microcontroller 103 address location is written by microcontroller 103 in response to a ISA bus write to the Sound Blaster Command Register. The write strobe of microcontroller 103 is used to clock the data from XDB[7:0] into a latch. The output from the latch is then enabled onto the ISA data bus-where it is read.

FIG. 24C is a diagram of the bitfields of the MPU-401 Receive Data Latch at microcontroller address 0x02. This microcontroller 103 address location is written by microcontroller 103 in response to a ISA bus write to the MPU-401 Command Register or read by the ISA bus of the MPU-401 Transmit/Receive Register. The write strobe of microcontroller 103 is used to clock the data from XDB[7:0] into a latch. The output from the latch is then enabled onto the ISA data bus where it is read.

FIG. 24D is a diagram of the bitfields of the STATUS REGISTER at Address 0x03. This microcontroller address location when read by microcontroller 103 returns the current status of the Sound Blaster, MPU-401 ISA bus handshake bits, codec interrupt, and Sound Blaster ADPCM data ready:

RXS-MPU-401 Receive Buffer Status 0=not empt, 1=empty;

TXS-MPU-401 Transmit Buffer Status 0=not full, 1=full;

SCB-Sound Blaster Command Busy 0=not busy, 1=busy;

SDA-Sound Blaster Data Available 0=no data available, 1=data available;

CINT-Codec Interrupt Status 0=no interrupt pending, 1=interrupt pending; and

SBAD Sound Blaster ADPCM Status 0=old ADPCM data, 1=new ADPCM data.

FIG. 24E is a diagram of the Reserved Registers at microcontroller Addresses 0x04 through 0x07.

FIG. 24F is a diagram of the bitfields of Reset Sound Blaster Busy 2 at microcontroller 103 Address 0x08.

FIG. 24G is a diagram of the bitfields of the Reset Sound Blaster Busy 2 register at microcontroller address 0x08. When this microcontroller 103 address is written, the Sound Blaster Command Busy 2 flag is forced to a zero.

FIG. 24I is a diagram of the bitfields of the Sound Blaster ADPCM Data Latch at microcontroller 103 Address 0xC. This address is read in response to a Sound Blaster ADPCM DMA write (ADPCM Status bit=1 and TR0 interrupt active). A microcontroller 103 read of this address resets the ADPCM Status bit to a zero.

FIG. 24J is a diagram of the bitfields of Set Sound Blaster Busy 1 at microcontroller 103 Address MD. When this microcontroller 103 address is written the Sound Blaster Command Busy 1 flag is forced to a one.

FIG. 24K is a diagram of the bitfields of the Sound Blaster DMA Request Register at microcontroller 103 Address ME which is in response to a write of a DMA command to the Sound Blaster Command Register. The write strobe of microcontroller 103 is used to clock the data from XDB[7:0] into a latch which also results in a DMA Request being generated on the ISA bus. When the ISA bus responds via a DMA acknowledge, the data that was written to this register is enabled onto the ISA bus where it is read. The DMA request may also be cleared by microcontroller 103 performing a read of this register.

FIG. 24L is a diagram of the bitfields of the Sound Blaster Interrupt Request Register at microcontroller 103 Address 0x0F. When this microcontroller 103 register is written an interrupt is generated on the ISA bus. The interrupt is cleared when the Sound Blaster DSP Data Port is read.

Control Register Interface

In the Control Logical Device space exits a set of registers for Codec 100 specific functions. These functions include EEPROM programming, power management modes, host interrupt generation, Sound Enhancement control, SP/DIF control, and various other miscellaneous control bits. The control registers are summarized in TABLES 48A and 48B.

TABLE 48A
ADDRESS
hex D7 D6 D5 D4 D3 D2 D1 D0
Control PM1 PM0 CONSW PDC PDP PDM JR1 JRO
base + 0
Control PCDIN PSINT ADC1 ADC0 PMINT DIN/EEN DOUT CLK
base + 1
Control PDWN SRC VREF MIX ADC DAC PROC FM
base + 2
Control CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA1
base + 3
Control CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
base + 4
Control CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
base + 5
Control RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
base + 6
Control CWSS ICTRL ISB IWSS IMPU res res res
base + 7
Control RESERVED
base +
9-15

TABLE 48B
Indirect Registers: (CI0-CI255)
CA4-CA0 D7 D6 D5 D4 D3 D2 D1 D0
CI0 RWSS res res res res res res res
default =
0x0
CI1 V2 V1 V0 res res CID2 CID1 CID0
default =
0x88
CI2 SPC3 SPC2 SPC1 SPC0 CTR3 CTR2 CTR1 CTR0
default =
0x0
CI3 3DEN 3DMON 3DSP QSEN res res res res
default =
0x0
CI4 S/PDIF BLKST U V res res res res
default =
0x0
CI5 CS9 CS8 CS5 CS4 CS3 CS2 CS1 CS0
default =
0x0
CI6 CS25 CS24 CS15 CS14 CS13 CS12 CS11 CS10
default =
0x0
CI7 FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0
CI8 SPBSP SBSC WTEN SPS MCLKDIS BRESET
default =
0x0
CI9-CI26 RESERVED
CI27 LOAM LMS1 LMS0 LOA3 LOA2 LOA1 LOA0
CI28 res res res res res res res res
CI29 ROAM RMS1 RMS0 ROA3 ROA2 ROA1 ROA0
CI30-CI54 RESERVED
CI55 ARE Y2 X2 Y1 X2
CI56 X1-7 X1-6 X1-5 X1-4 X1-3 X1-2 X1-1 X1-0
CI57 X1-15 X1-14 X1-13 X1-12 X1-11 X1-10 X1-9 X1-8
CI58 Y1-7 Y1-6 Y1-5 Y1-4 Y1-3 Y1-2 Y1-0 Y1-0
CI59 Y1-15 Y1-14 Y1-13 Y1-12 Y1-11 Y1-10 Y1-9 Y1-8
CI60 X2-7 X2-6 X2-5 X2-4 X2-3 X2-2 X2-2 X2-0
CI61 X2-15 X2-14 X2-13 X2-12 X2-11 X2-10 X2-9 X2-8
CI62 Y2-7 Y2-6 Y2-5 Y2-4 Y2-3 Y2-2 Y2-1 Y2-0
CI63 Y2-15 Y2-14 Y2-13 Y2-12 Y2-11 Y2-10 Y2-9 Y2-8
CI64-CI255 RESERVED
Note: CI55-CI63 are only accessible in Test Mode 9 or Test Mode 10.

FIGS. 25A-25S and the accompanying text describe each of the Control Registers in detail.

FIG. 25A is a diagram of the Miscellaneous Control Register (at base +0, default=0x00000000). Microcontroller 103 reads this register and controls the various functions accordingly. An ISA bus write of this register will also generate an interrupt to microcontroller 103 microcontroller via INT1. The bitfields can be described as follows.

JS1, JS0 These bits select among four joystick operating speeds:

0 0=slowest speed;

0 1−medium slow speed;

1 0−medium fast speed;

1 1=fastest speed

The CONSW bit controls host interrupt generation when a context switch occurs. The interrupt will only be passed through to the ISA bus if an interrupt resource was specified for Codec 100 logical device and the PlugnPlay configuration manager mapped the interrupt. Thus setting CONSW to a one does not necessarily guarantee that an ISA bus interrupt will get generated on a context switch. The decoding is:

0−no interrupt generated on context switch

1−interrupt generated on context switch

The PM1, PM0 bits control the various power down modes of Codec 100.

0 0=normal operation with bits PDC, PDP, PDM enabled;

0 1=A/D and D/A of codec are powered down. Analog mixer is still active in this mode, but gain/attenuation values are frozen. Bits PDC and PDM disabled;

1 0=full Codec 100 power down. All Codec 100 functions are disabled except reads and writes to this register. This is a software version of the RESDRV pin. A reset will be generated (all clocks disabled), and held, to all Codec 100 internal logic including microcontroller 103 and all internal registers. The reset is released once these bits are written to 00 and the clocks are re-enabled;

1 1=In this mode the A/D and DIA of the Codec, microcontroller 103, and the codec mixer including VREF are all powered down. Microcontroller 103 is forced into idle mode. An interrupt to microcontroller 103 will cause microcontroller 103 to exit idle mode and resume normal operation, but the codec A/D, D/A, and mixer will remained powered down. The mixer register settings are reset to default settings in this mode. When these bits are set to one all accesses to codec registers are disabled. When these bits are toggled from a 11 to a zero there will be a delay, caused by VREF capacitor charging, until the codec registers may be accessed reliably. The delay is determined by the capacitor value on the VREF pin and typically is on the order of 200 ms.

The PDC bit (Power Down Codec) controls codec power down:

0=Normal operation

1=A/D and D/A functions of codec are powered down.; the codec interface remains active and registers, including mixer registers, may be read or written.

The PDP Power Down Processor bit:

0=Normal operation

1=microcontroller 103 is forced into idle mode. Any interrupts generated to microcontroller 103 (PnP, Sound Blaster, MPU-401, Context Switch) will cause microcontroller 103 to exit IDLE mode and resume normal operation. Microcontroller 103 will clear this bit when idle mode operation is exited.

The PDM Power Down Mixer:

0=Normal operation

1=Mixer is powered down. While in this mode the codec interface is enabled and the codec registers are accessible.

RES—The RES bits are reserved bits that may be required for future changes or additions. These bits should have physical storage elements associated with them.

FIG. 25B is a diagram of the Hardware Control Register (at address base +1, default=0x10000000). This bitfield of this register can be described as follows:

The PCDINT (Polarity CDROM Interrupt) bit specifies polarity of CDROM interrupt input:

0=CDROM interrupt is active low; and

1=CDROM interrupt is active high.

The PSINT (Polarity Synthesizer Interrupt) bit specifies polarity of synthesizer interrupt input:

0=synthesizer interrupt is active low; and

1=synthesizer interrupt is active high.

The PMINT (Polarity Modem Interrupt) bit specifies polarity of modem interrupt input:

0−modem interrupt is active low; and

1=modem interrupt is active high.

The ADC1, ADCO (A/D Control 1,0) bits are used to control an additional analog mix/feedback path into the A/D converters:

00=normal operation. A/D input from input mux/gain, stage. No mix of Input MLJX to output;

01=output from Input Mux is mixed into line outputs. A/Dinput is from Input Mux;

10=output from Input Mux is mixed into line outputs. A/D input is from line outputs; and

11−reserved.

FIG. 25C is a diagram of the Power Down Control Register (at address control base +2, default=00000000). Microcontroller 103 reads this register and controls the various functions accordingly. An ISA bus write of this register will also generate an interrupt to microcontroller 103 microcontroller via INT1. This register is decoded:

Full Power Down Power down. When this bit is
set to 1 Codec 100 is put into a
full power down mode. All
functions are disabled except
reads and writes to this
register. Microcontroller 103
is held reset and all clocks are
disabled. When this bit is set
to zero Codec 100 will resume
normal operation after valid
clocks are detected, VREF has
reached the operating level, and
a calibration cycle has been
completed. Only the codec
analog mixer registers are reset
when this bit is set to a one.
Due to the fact that
microcontroller 103 is reset by
this bit, internal registers may
be changed as defined by
microcontroller 103 start-up
initialization sequence.
SRC Power* down of the Sample Rate Converter
when set = 1. If the input sampling rate
is at 44100 Hz, the data will feed through
unaffected.
REF Power down of the reference voltage source
when set = 1. The complete analog section
of the device powers down. When VREF is
powered up and the Mixer is powered down,
Mono Bypass Mode is functional. A pop on
the line outputs will always occur if this
bit is set even if the master volume is
muted. When this bit is set to one all
accesses to codec registers are disabled
and when toggled from a one to a zero
there will be a delay, caused by VREF
capacitor charging, until the codec
registers may be accessed reliably. This
delay is determined by the capacitor value
on the VREF pin and typically is on the
order of 200 ms.
MIXER Power down of the mixer analog section
when set = 1. All op amps except for the
MONO in and MONO out opamps are powered
down, all analog inputs and outputs are
centered around VREF, if VREF is enabled
and not powered down. A reset is not
required to maintain the calibrated state
if the mixer is powered down and VREF is
powered up.
ADC Power down of the A/D converter,
decimator, A/D SRC, and A/D compression
circuitry. Capture timing is disabled.
DAC Power down of the DAC, switch cap filter,
interpolator, SRC, decompressor circuitry,
FM engine, serial port circuitry.
Playback timing is disabled.
MC Microcontroller 103 is put into IDLE mode
Any interrupts generated to
microcontroller 103 (PnP, Sound Blaster,
MFU-401, Context Switch) will cause
microcontroller 103 to exit IDLE mode and
resume normal operation.
FM Power down of the FM synthesis engine.
NOTE: Software should mute the ADC, DAC, FM and Mixer outputs when asserting or deasserting any power down modes to prevent clicks and pops.

FIG. 25D is a diagram of the bitfields of the Control Address/Index Register (at address, base +3, default=00000000). The Control Address/Index Register is used to specify an index into a set of extended control registers, discussed further below. Once a particular register index has been specified the register may be accessed by reading or writing the Control Data Register. Bits D7 . . . D4 are decoded and must be zero's to access the extended control registers.

FIG. 25E is a diagram of the bitfields of Control Data Register (at address base +4, default=00000000). The Control Data Register is used to access data from an extended control register that is specified in the Control Address/Data Register.

FIG. 25F is a diagram of the bitfields of the Command Register (at address base +5, default=00000000). This register is used to control various functions of Codec 100. A Command is executed after the appropriate Command identifier is written to this register. When this register is either read or written via the ISA bus an interrupt will occur to microcontroller 103 via INT1. The support commands are listed below:

DISABLE_PNP (0x55) This command is used to disable
Codec 100 Plug & Play function
so that Codec 100 may operate in
non-PnP environments.
DISABLE_CSC (0x56) This command is used to disable
Codec 100 “Crystal Key” back
door mechanism so that Codec 100
may operate in multiple Codec
100 environments in which the
“Crystal Key” is used to
configure a Codec 100.
UPDATE_PNP (0x5A) This command is used to force an
update of the current values
that specify the settings for
mapping inputs to Codec 100
mixer as well as the settings
for ISA Bus interrupt and DMA
mapping and configuration data
for all Codec 100 logical
devices. If the current
settings were changed due to a
Program RAM load then this
command will force the new
settings to be transferred to
the hardware. This command will
also disable any logical
devices, including the Control
Port, that are active at the
time this command is sent.
RAM_LOAD (0xAA) This command is used to
read/write the Program Ram.
Once the 0xAA command is
received Codec 100 expects the
following two bytes to specify a
starting address location. This
starting address location
specifies where data are to be
written into or read from the
Program RAM. The first byte
following the command byte
specifies the low byte of a
16-bit RAM load start address
and the second byte specifies
the high byte. Subsequent bytes
are then written to RAM (Write
Cycle to the Program RAM Access
Register) or read from the RAM
(Read Cycle to the Program RAM
Access Register). After each
byte is transferred, the RAM
address pointer is automatically
incremented to point to the next
location. Data will continue to
be written to or read from the
RAM until the Program RAM Access
End Register is written. The
data written to the Program RAM
Access End Register is a don't
care.
SOFTWARE RESET (0x59) When this value is written to
Codec 100 Control Port
microcontroller 103 will be
forced to jump to ROM location
0x0000. This will cause all the
hardware configuration registers
to be reset back to an off
state. The function of any
multi-function pins will be
unchanged by this command. If a
Legacy Mode EEPROM is present,
then the hardware configuration
registers are re-programmed
according to the data contained
in the EEPROM. If a Legacy Mode
EEPROM is not present then the
configuration registers must be
setup by a host load or PnP
configuration sequence.
SUSPEND REQUEST When this value is written to Codec
(0x33) 100 Control Port microcontroller 103
will copy the current microcontroller
103 state into the area of RAM that
is used to store the Plug-n-Play
resource data. This command will
cause Codec 100 to hold IOCHRDY low
until microcontroller 103 has been
copied to RAM.
SUSPEND (0x3C) When this value is written to Codec
100 Control Port microcontroller 103
will enter IDLE mode.
RESUME (0xCC) When this value is written to Codec
100 Control Port microcontroller 103
will exit from IDLE mode and restore
the state of microcontroller 103 from
RAM.

FIG. 25G is a diagram of the bitfields of the Program RAM Access End Register (at address base +6, default=00000000). This register is used to end access to the Program RAM memory of Codec 100. When this register is written via the ISA bus, an interrupt will occur to microcontroller 103 via INT1.

FIG. 25H is a diagram of the bitfields of the Status Register (at address base +7, default=00000000). The bitfields decoding is as follows:

CSS (Context Switch Status) bit indicates current operating mode of Codec 100:

0=Sound Blaster; and

1=Sound System.

The CSI (Context Switch Interrupt Status) bit indicates current status of Context Switch Interrupt:

0=no interrupt pending; and

1=interrupt pending.

The SBI (Sound Blaster Interrupt Status) bit indicates current status of Sound Blaster Interrupt:

0=no interrupt pending; and

1=interrupt pending.

The CDECI (Codec Interrupt Status) bit indicates current status of Codec Interrupt:

0=no interrupt pending; and

1=interrupt pending.

The MPUI (MPU401 Interrupt Status) bit indicates current status of MPU-401 Interrupt:

0=no interrupt pending; and

1=interrupt pending.

Control Indirect Registers (C10-C131) are summarized in TABLE 48B above. The individual registers can now be described in further detail

FIG. 25I is a diagram of the bitfields of the Miscellaneous Control at Control Index register (C0, default=00000000). The bitfields decoding is as follows:

RWSS Reset code registers. Resets all codec
registers to zero while this bit is set to a
one. When this bit is set back to zero then
all codec registers are reset to default
values.
res Reserved.

FIG. 25J is a diagram of the bitfields of the Version/ID at Control Index register (C1, default=10000100). This read only register shadows the current contents of codec indirect register I25. The register holds the current chip identifier and version number where:

V2-V0 Version number. See section 8 for a
description of these bits.
res Reserved
CID2-CID0 Chip Identification.

FIG. 25K is a diagram of the bitfields of SRS Control Register at Control Index (C2, default=00000010). The bitfield decodings are:

SPC (Space) 3-0, SRS processed signal gain termed “SPACE”. The least significant bit represents −1.5 dB, the attenuation range is from 0 dB to −22.5 dB, with 0000=(0 dB or min attenuation). TABLE 49A associates the SPC register values with the resulting attenuation.

CNT (Center) 3-0, SRS processed signal gain termed “CENTER”. The least significant bit represents −1.5 dB, the attenuation range is from 0 dB to −22.5 dB, with 0000=(0 dB or min attenuation). TABLE 49B associates the CNT register values with the resulting attenuation.

When the SRS/MONO bit is set to a one this register is reset to 00100000.

TABLE 49A
SPC SPC SCP SCP
3 2 1 0 LEVEL
0 0 0 0 0 0 dB
1 0 0 0 1 −1.5 dB
2 0 0 1 0 −3.0 dB
3 0 0 1 1 −4.5 dB
4 0 1 0 0 −6.0 dB
5 0 1 0 1 −7.5 dB
6 0 1 1 0 −9.0 dB
7 0 1 1 1 −10.5 dB
8 1 0 0 0 −12.0 dB
9 1 0 0 1 −13.5 dB
10 1 0 1 0 −15.0 dB
11 1 0 1 1 −16.5 dB
12 1 1 0 0 −18.0 dB
13 1 1 0 1 −19.5 dB
14 1 1 1 0 −21.0 dB
15 1 1 1 1 −22.5 dB

TABLE 49B
CNT CNT CNT CNT
3 2 1 0 LEVEL
0 0 0 0 0 0 dB
1 0 0 0 1 −1.5 dB
2 0 0 1 0 −3.0 dB
3 0 0 1 1 −4.5 dB
4 0 1 0 0 −6.0 dB
5 0 1 0 1 −7.5 dB
6 0 1 1 0 −9.0 dB
7 0 1 1 1 −10.5 dB
8 1 0 0 0 −12.0 dB
9 1 0 0 1 −13.5 dB
10 1 0 1 0 −15.0 dB
11 1 0 1 1 −16.5 dB
12 1 1 0 0 −18.0 dB
13 1 1 0 1 −19.5 dB
14 1 1 1 0 −21.0 dB
15 1 1 1 1 −22.5 dB

FIG. 25L is a diagram of the bitfields of 3D Sound Control Register at Control Index (C3, default=00000000). The field decodings are as follows:

3DEN When this bit is set to 1, the 3D Audio
DSP is enabled and will process any stereo
signal from the Digital Mixer. The
processed signal is converted by the DAC
to “3D” stereo analog 2 channel audio
data. The 3D Audio DSP will process
either SRS or QSound based on which ROM
code is selected by the “Bond Out Option.”
3DMON When this bit is set to 1, the SRS Mono to
Stereo DSP is enabled instead of the SRS
Stereo DSP, and will process any mono or
stereo signal from the Digital Mixer. The
processed signal is converted by the DAC
to “pseudo” stereo analog 2 channel audio
data. The 3DEN bit must be set to 1, on
Codec 100 - SRS Bond Out Option.
3DSP When this bit is set to 1, the digital
data to the Serial Port is from the 3D
Audio DSP. When this bit is set to 0, the
digital data to the Serial Port is from
the A/D converter.
QSEN This bit when set to a one will enable the
QSound circuitry.
Res Reserved for future use.
Note: SRS MONO - When the Mono to Stereo function is selected, the “Space” and “Center” bits in register C2 are blocked from writing to, and the registers are set to the default values - “Space” −3 dB or 0010 and “Center” 0 dB or 0000.

FIG. 25M is a diagram of the bitfields of the S/PDIF Control Register at Control Index (C4, default=00000000). The decodings are as follows:

SPDIF When this bit is set to 1 and the indirect
register I6 is set to 1 (Serial Port
enable), the digital data to the Serial
Port is formatted to the S/PDIF protocol.
When this bit is set to 0 and the indirect
register I16 SPEN bit is set to a 1
(Serial Port enable), the Serial Port
transmits the standard format digital data
from the A/D or 3D data as selected by the
3DSP bit in register C3.
BLKST A low to high transition specifies a new
channel status block boundary.
(Block Start)
U U Bit is a user defined bit.
V Validity Bit. Indicates whether the audio
sample is “suitable for conversion to an analog signal”.
res Reserved for future use

FIG. 25N is a diagram of the bitfields of S/PDIF Channel Status Data −0 at Control Index (C5, Default=00000000). The bitfields are decoded as follows:

CS0 0 = Consumer;
CS1 Audio:
0 = Digital Audio; and
1 = Non - Audio Data;
CS2 Copy/Copyright:
0 = copy inhibited/copyright asserted; and
1 = copy permitted/copyright not asserted;
CS3-CS4 Pre-emphasis:
00 - defines no pre-emphasis - if CSO = 0
(digital audio); and
1 = 50/15 us pre-emphasis;
CS5 Lock: Source Sample frequency:
0 = locked; and
I = unlocked;
CS24 Fs: Sample frequency 0 = 44.1 kHz; and
CS25 Fs: Sample frequency 0 - 44.1 kHz.

FIG. 25O is a diagram of the bitfields of S/PDIF Channel Status Data −1 at Control Index (C6) (Default=00000000). The bitfields are decoded as follows:

CS15 L Bit Generation Status:
0 = Original; and
1 = 1st Generation or higher; and
CS8-CS14 Category Code:
0000000 General;
0000001 Experimental;
0001xxx Solid State Memory;
001xxxx Broadcast Reception;
010xxxx Digital/Digital converters;
01100xx A/D converters w/o copy info;
01101xx A/D converters w/ copy info
- (using Copy and L bits);
0111xxx Broadcast reception;
100xxx Laser-Optical;
101xxxx Musical Instruments;
110xxxx Magnetic tape or disk; and
111xxxx Reserved.

FIG. 25P is a diagram of the bitfields of FAB Port ID at Control Index (C7, Default=00000000). In order to track the various FAB ports of Codec 100 this register is updated each time any changes are done to the current revision in order to accommodate FAB specific requirements.

FB7-FBO = 0x00 FAB 1;
0x01 FAB 2;
0x02 FAB 3; and
0x03 FAB 4.

FIG. 25Q is a diagram of the bitfields of Wavetable and Serial Port at Control Index (C8, Default=00000000). The bitfield encodings are as follows:

SBSP Sound Blaster Swap Playback - when this
bit is set to a zero the current ordering
of samples for DMA playback are swapped
relative to the current defined format;
SBSC Sound Blaster Swap Capture - when this bit
is set to a one the current ordering of
samples for DMA capture are swapped
relative to the current defined format;
res Reserved;

WTEN Wavetable Enable—When this bit is set to a one the XD7:XD5 pins are switched to support a wavetable interface as shown in TABLE 50:

TABLE 50
WTEN 0 1
Pin 1 XD7 - Bi-directional DATA - Input
Pin 2 XD6 - Bi-directional LRCLK - Input
Pin 3 XD5 - Bi-directional MCLK - Output
Pin 4 XD4 - Bi-directional Defined by SPS
Pin 5 XD3 - Bi-directional Defined by SPS
Pin 6 XD2 - Bi-directional Defined by SPS
Pin 7 XD1 - Bi-directional Defined by SPS
Pin 8 XD0 - Bi-directional XD0 - Bi-directional

SPS Serial Port Switch - When this bit is set
to a one and the SPE bit in register I16
is set to a one the DSP serial port pins
are switched from the second joystick pins
to the XD pins as shown in TABLE 51. If
SPS is a zero and the SPE bit in register
I16 is set to a one the DSP serial port
pins are routed to the second joystick
pins. If the SPE bit in register I16 is a
zero then the serial port pins do not
appear anywhere.

TABLE 51
SPS 0 1
Pin 1 XD7 - Bi-directional WTEN Defined
Pin 2 XD6 - Bi-directional WTEN Defined
Pin 3 XD5 - Bi-directional WTEN Defined
Pin 4 XD4 - Bi-directional FSYNC - Output
Pin 5 XD3 - Bi-directional SDOUT - Output
Pin 6 XD2 - Bi-directional SDIN - Input
Pin 7 XD1 - Bi-directional SCLK - Output
Pin 8 XD0 - Bi-directional XD0 - Bi-directional

If either WTEN or SPS are set to a one then the XBUF bit in CDROM Interface Control Register at microcontroller 103 address 0x34 is forced to a one.

MCLKDIS When this bit is set to a one, and the
wavetable serial interface is enabled by
WTEN = 1, the MCLK pin to the wavetable
device is synchronously forced to zero.
MCLK will remain a zero until MCLKDIS is
set to zero. At this time MCLK will
synchronously be enabled; and
BRESET When this bit is set to a one the BRESET
pin is forced to zero. This is to allow
microcontroller 103 and host control of
external devices connected to the BRESET
pin;

FIG. 25R is a diagram of the bitfields of Left Output Master Volume at Control Index (C27, default=001x0000) where:

LOA3-LOA0 are the Left Output Master Volume bit LOA0 is the least significant bit and represents 2 dB steps. The range is +12 db to −18 db; and

LMS1:LMS0 are the Left Output Mixer Summer Attenuation bits and:

0 0 −12 dB;
0 1  0 dB;
1 0  −6 dB; and
1 1 −18 dB.

FIG. 25S is a diagram of the bitfields of Right Output Master Volume at Control Index (c29, default=001x000) where:

ROA3-ROA0 are the Right Output Master Volume bits.

ROA0 is the least significant bit and represents 2 dB steps. The range is +12 dB to −18 dB; and

RMS1:RMS0 Right Output Mixer Summer Attenuation

where:

0 0 −12 dB
0 1  0 dB
1 0  −6 dB
1 1 −18 dB.

Codec Interface

Codec Interface 107 includes logic that enables access to the registers located in core from either the ISA bus (through Plug-n-Play configuration registers) or microcontroller 103. FIG. 26 is a diagram emphasizing Codec Interface 100.

The Sound System Codec software interface consists of 4 I/O locations starting at the Plug and Play address values ‘WSSbase’ shown in TABLE 52A, and supports 12-bit address decoding. If the upper address bits, SA12-SA15 are used, they must be a 0 to decode a valid address. The SS Codec also requires one interrupt and one or preferably two DMA channels, one for playback and one for capture. Since the SS Codec and Sound Blaster device are mutually exclusive, the two devices share the same interrupt and DMA playback channel.

TABLE 52A
Direct Registers: WSSbase (R0-R3)
Address D7 D6 D5 D4 D3 D2 D1 D0
WSSbase + 0 R0 INIT MCE TRD IA4 IA3 IA2 IA1 IA0
WSSbase + 1 R1 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
WSSbase + 2 R2 CU/L CL/R CRDY SER PU/L PL/R PRDY INT
WSSbase + 3 R3 CD7/PD7 CD6/PD6 CD5/PD5 CD4/PD4 CD3/PD3 CD2/PD2 CD1/PD1 CD0/PD0

TABLE 52B
Indirect Registers: (CI0:I31)
IA4-IA0 D7 D6 D5 D4 D3 D2 D1 D0
I0 LSS1 LSS0 LMGE LAG3 LAG2 LAG1 LAG0
I1 RSS1 RSS0 RMGE RAG3 RAG2 RAG1 RAG0
I2 LX1M LX11M LXIMM LX1G4 LX1G3 LX1G2 LX1G1 LX1G0
I3 RX1M RX11M RX1G4 RX1G3 RX1G2 RX1G1 RX1G0
I4 LX2M LX21M LX2G4 LX2G3 LX2G2 LX2G1 LX2G0
I5 RX2M RX21M RX2G4 RX2G3 RX2G2 RX2G1 RX2G0
I6 LDM LDA6 LDA5 LDA4 LDA3 LDA2 LDA1 LDA0
I7 RDM RDA6 RDA5 RDA4 RDA3 RDA2 RDA1 RDA0
I8 FMT1 FMT0 C/L S/M CFS2 CSF1 CSF0 C2S1
I9 CPIO PPIO CAL1 CAL0 SDC CEN PEN
I10 XCTL1 XCTL0 OSM1 OSM0 DEN DTM IEN
I11 COR PUR ACI DRS ORR1 ORR0 ORL1 ORL0
I12 MODE2 MODE3 ID3 ID2 ID1 ID0
I13 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 LBE
I14 PUB7 PUB6 PUB5 PUB4 PUB3 PUB2 PUB1 PUB0
I15 PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB0
I16 TE CMCE PMCE SF1 SF0 SPE DACZ
I17 TEST TEST TEST TEST APAR XTALE HPF
I18 LLM LLM LLMM LLG4 LLG3 LLG2 LLG1 LLG0
I19 RLM RLM RLMM RLB4 RLG3 RLG2 RLG1 RLG0
I20 TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0
I21 TU7 TU6 TU5 TU4 TU3 TU2 TU1 TU0
I22 SRE DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 CS2
I23 XA3 XA2 XA1 XA0 XRAE XA4 ACF
I24 TI CI PI CU CO PO PU
I25 V2 V1 V0 CID2 CID1 CID0
I26 MIM MOM MBY MIA3 MIA2 MIA1 MIA0
I27
I28 FMT1 FMT0 C/L S/M
I29
I30 CUB7 CUB6 CUB5 CUB4 CUB3 CUB2 CUB1 CUB0
I31 CLB7 CLB6 CLB5 CLB4 CLB3 CLB2 CLB1 CLB0

TABLE 52C
Extended Registers: (X0:X17)
XA3-XA0 D7 D6 D5 D4 D3 D2 D1 D0
X0 LL2M LL2IM LL2OM LL2G4 LL2G3 LL2G2 LL2G1 LL2G0
X1 RL2M RL2IM RL2OM RL2G4 RL2G3 RL2G2 RL2G1 RL2G0
X2 LMIM LMM LMBST LMCG4 LMCG3 LMCG2 LMCG1 LMCG0
X3 RMIM RMM RMBST RMCG4 RMCG3 RMCG2 RMCG1 RMCG0
X4 MIMR LIS1 LIS0 IFM IS0 IS1 MTE
X5 MOMR RIS1 RIS0 DIFMIC
X6 LFMM LFMA5 LFMA4 LFMA3 LFMA2 LFMA1 LFMA0
X7 RFMM RFMA5 RFMA4 RFMA3 RFMA2 RFMA1 RFMA0
X8 LSPOM LSPA5 LSPA4 LSPA3 LSPA2 LSPA1 LSPA0
X9 RSPOM RSPA5 RSPA4 RSPA3 RSPA2 RSPA1 RSPA0
X10 SLBE RLBA5 RLBA4 RLBA3 RLBA2 RLBA1 RLBA0
X11 LDIM RDIM SRCE
X12 SRAD7 SRAD6 SRAD5 SRAD4 SRAD3 SRDA2 SRAD1 SRDA0
X13 SRDA7 SRDA6 SRDA5 SRDA4 SRDA3 SRDA2 SRDA1 SRDA0
X14 LDDM LDD6 LDD5 LDD4 LDD3 LDD2 LDD1 LDD0
X15 RDDM RDD6 RDD5 RDD4 RDD3 RDD2 RDD1 RDD0
X16 LBM LB5 LB4 LB3 LB2 LB1 LB0
X17 RBM RB5 RB4 RB3 RB2 RB1 RB0
X25 V2 V1 V0 res res CID2 CID1 CID0

The WSS Codec functions 204 include FIFOs 121 and 122 (FIG. 1) 16-sample FIFOs in both the playback and capture digital audio data paths. The FIFOs are transparent and have no programming associated with them.

When playback is enabled, playback FIFO 121 continually requests data until the FIFO is full, and then makes requests as positions inside the FIFO are emptied, thereby keeping as full as possible. Thus, when Codec 100 cannot respond within a sample period, the FIFO starts to empty, avoiding a momentary loss of audio data output to the ISA bus. If the FIFO runs out of data, the last valid sample can be continuously output to the DACs (if DACZ in register I16 is set) which will eliminate pops from occurring.

When capture is enabled, capture FIFO 121 continually makes requests to the ISA bus every sample period thereby attempting to remain empty. Thus, when codec 100 cannot respond within a sample period, capture FIFO 121 starts filling, thereby avoiding a loss of data in the audio data stream.

Four I/O mapped locations (block 107, FIG. 1) are available for accessing the Codec functions and mixer. The control registers allow access to status, audio data, and all indirect registers via the index registers. The IOR and IOW signals are used to define the read and write cycles respectively. A PIO access to the Codec begins when the host puts an address on the ISA bus which matches WSSbase and drives AEN low. WSSbase is programmed during a Plug and Play configuration sequence. Once a valid base address has been decoded then the assertion of IOR will cause the WSS Codec to drive data on the ISA data bus lines. Write cycles require the host to assert data on the ISA data bus lines and strobe the IOW signal. The WSS Codec will latch data into the PIO register on the rising edge of the IOW strobe.

The audio data interface typically uses DMA request/grant pins to transfer the digital audio data between WSS Codec 204 functions and the bus. WSS Codec 204 functions is responsible for asserting a request signal whenever the Codec's internal buffers need updating. The bus responds with an acknowledge signal and strobes data to and from the Codec, 8 bits at a time. WSS Codec functions keep the request pin active until the appropriate number of 8-bit cycles have occurred to transfer one audio sample. Note that different audio data types require a different number of 8-bit transfers.

The second type of parallel bus cycle from WSS Codec 204 is a DMA transfer. DMA cycles are distinguished from PIO register cycles by the assertion of a DRQ, while AEN is inactive, followed by an acknowledgment by the host by the assertion of DACK. While the acknowledgment is received from the host, WSS Codec 204 assumes that any cycles occurring are DMA cycles and ignores the addresses on the address lines.

WSS Codec 204 may assert the DMA request signal at any time. Once asserted, the DMA request will remain asserted until a complete DMA cycle occurs. DMA transfers may be terminated by resetting the PEN and/or CEN bits in the Interface Configuration register (I9), depending on the DMA that is in progress (playback, capture, or both). Termination of DMA transfers may only happen between sample transfers on the bus. If DRQ goes active while resetting PEN and/or CEN, the request must be acknowledged with DACK and a final sample transfer completed.

Mapping of the WSS Codec DRQ and DACK onto the ISA bus is accomplished by the Plug and Play configuration registers. If the Plug and Play resource data specifies only one DMA channel for the Codec (or the codec is placed in SDC mode discussed below) then both the playback and capture DMA requests should be routed to the same DRQ/DACK pair (DMA Channel Select 0). If the Plug and Play resource data specifies two DMA channels for the Codec, then the playback DMA request will be routed to the DMA pair specified by the DMA Channel Select 0 resource data, and the capture DMA requests will be routed to the DMA pair specified by the DMA Channel Select 1 resource data.

WSS Codec 204 supports a single and a dual DMA channel mode. In dual DMA channel mode, playback and capture DMA requests and acknowledges occur on independent DMA channels. In dual DMA mode, SDC should be set to 0. The Playback- and Capture-Enables (PEN, CEN, I9) can be changed without a Mode Change Enable (MCE, R0). This allows for proper full duplex control where applications are independently using playback and capture.

When two DMA channels are not available, the SDC mode forces all DMA transfers (capture or playback) to occur on a single DMA channel (playback channel). The trade-off is that the WSS Codec will no longer be able to perform simultaneous DMA capture and playback.

To enable the SDC mode, set the SDC bit in the Interface Configuration register (I9). With the SDC bit asserted, the internal workings of the WSS Codec remain exactly the same as dual mode, except for the manner in which DMA request and acknowledges are handled.

The playback of audio data will occur on the playback channel exactly as dual channel operation; however, the capture audio channel is now diverted to the playback channel. Alternatively stated, the capture DMA request occurs on DMA channel select 0 for WSS Codec 204. (In MODE 2, the capture data format is always set in register I28.) If both the both playback and capture are enabled, the default will be playback. SDC does not have any affect when using PIO accesses.

As discussed briefly above, Windows Sound System codec 204 is mapped via four locations. The I/O base address, WSSbase, is determined by the Plug and Play configuration. The WSSbase supports four direct registers, shown in TABLE 52A. The first two direct registers are used to access 32 indirect registers shown in TABLE 52B. The Index Address register (WSSbase+0) points to the indirect register that is accessed through the Indexed Data register (WSSbase+1).

The Master Volume Control uses a 26-step linear mapping of 2 dB per step. The Sound Blaster Mixer Master Fader Control uses the non-linear Sound Blaster mapping with a range of 0 dB to −28 dB in eight steps.

The ISA bus writes to the Sound Blaster Mixer Master address and Volume change button pushes are mapped to the CODEC_MASTER_OUT registers, I27A and I29A. The Sound Blaster mixer range is implemented as a gain reduction to the current CODEC Master Volume setting. Thus, the Master Volume setting of +2 dB will allow a 2 dB to −26 dB Sound Blaster Master Out control gain range. A Master Volume setting of −30 dB will allow a −30 db to −36 dB range for the Sound Blaster Master Out control. In all cases, moving the Sound Blaster Master Out Control to the bottom of its range (zero or one) will cause a CODEC mute. Also the lowest CODEC Master Volume step (twenty six) will cause a CODEC mute.

The default for the Master Volume control is 0 dB. The default for the Sound Blaster Master Out Control is −11 dB.

The UP/DOWN/MUTE pins are accessible by microcontroller 103 at Port 3 when the VCEN bit has been set to a one at microcontroller 103 address 0x34. FIG. 8, discussed briefly above, generally describes the bit fields of Port 3. Once VCEN=1, microcontroller 103 access to Port 3 will return the current data present on the UP/DOWN/MUTE pins (TTL levels).

The 26-step volume control is implemented using a 26 byte table which maps the numbers 0-25 with the Summer and Gain settings.

The user changes the Sound Blaster Master Volume by using ISA bus writes to the Sound Blaster mixer (external) mapped at I/O addresses 0x224 and 0x225.

The embedded code uses a combination of 2 groups of internal RAM variables and the I27A/I29A codec registers to accomplish Master volume control. The user hits buttons and the embedded code increments or decrements a count to keep track of the Master volume. This value is then combined with the appropriate mode fader (SB Master volume for Sound Blaster mode or WSS Master volume for Windows Sound System mode) to arrive at the final register value which will be written to the Codec registers I27A and I29A 205. TABLE 53 defines the Codec Master Map which correlates index values, register values and dB settings.

Master Volume Algorithm:

dCodecMasterVoiL/R+dWSSMasterVoil/*R=“index into CODEC_MASTER_MAP_TABLE ”

“CODEC_MASTER_MAP_TABLE Register Value”=I27A/I29A value.

*It is assumed that because the driver will vary the Codec Master Volume that the WSS Master Volume will not be used and therefore will always remain at its default value of 0 (db). Because of this the dWSSMasterVoiL and dWSSMasterVolR values can be ignored when handling the Master Volume Control.

TABLE 53
Index Value Register Value dB Setting
0 20H +12 dB
1 21H +10 dB
2 22H +08 dB
3 23H +06 dB
4 41H +04 dB
5 42H +02 dB
6 43H  0 dB
7 44H −02 dB
8 45H −04 dB
9 46H −06 dB
10 47H −08 dB
11 48H −10 dB
12 49H −12 dB
13 4AH −14 dB
14 4BH −16 dB
15 4CH −18 dB
16 4DH −20 dB
17 4EH −22 dB
18 4FH −24 dB
19 0DH −26 dB
20 0EH −28 dB
21 0FH −30 dB
22 6DH −32 dB
23 6EH −34 dB
24 6FH −36 dB
25 EFH MUTE

To read the Codec Master volume:

1. Read dCodecMasterVolL/dCodecMasterVolR (using a RAM Internal Access command)to obtain Index Value.

2. Convert Index Value to dB setting using the CODEC_MASTER_MAP_TABLE.

To write the Codec Master volume:

1. Receive user dB setting;

2. Convert dB setting to Index Value based on CODEC_MASTER_MAP_TABLE;

3. Convert dB setting to Register Value based on CODEC_MASTER_MAP_TABLE;

4. Write dCodecMasterVolL/dCodecMasterVolR registers with Index Value (using new RAM Internal Access command);

5. Write dLMasterHold/dRMasterHold registers with the Register Value (using new RAM Internal Access command); and

6. Perform Hold/Go OR Write I27/I29 via the Hold/Go mechanism using the Register Value. (Any Hold/Go sequence will cause I27/I29 registers to be updated with the register values in dLMasterHold/dRMasterHold).

EXAMPLE

The Codec Master Volume Buttons are set at Max (+12 dB) volume. If a 0x16 is written to dWSSMasterVolL and dWSSMasterVolR via the control port commands, then the Master output level will be −32 dB.

In both Sound Blaster mode and WSS mode, the user may change the CODEC Master Volume via pins connected to physical switches or buttons. There are four different “button schemes” supported by the Codec 100.

The user selects one of these four schemes by setting the VCF1 and VCF0 bits in the Hardware Configuration Data, Global Configuration Byte, contained in external EEPROM.

In the first scheme, the Up and Down pins are connected to momentary SPST switches and the Mute pin connected to a Push on/push off SPST switch. This scheme is selected by setting VCF1 and VCF0 to 00. The first scheme provides the functionality described in TABLE 54.

TABLE 54
Up Button Push +2dB volume increase
Up Button Hold +2dB volume increase every 500 ms (approx.)
Down Button Push −2dB volume decrease
Down Button Hold −2dB volume decrease every 500 ms (approx.)
Mute Button Push On Mute On
Mute Button Push Off Mute Off
*Pushing the Up button or the Down button will NOT un-mute Codec 204 if it was muted.

In the second scheme, the Up, Down and Mute pins are connected to momentary SPST switches and is selected by setting VCF1 and VCF0 to 01. TABLE 55 describes button operations in this scheme.

TABLE 55
Up Button Push +2dB volume increase
Up Button Hold +2dB volume increase every 500 ms (approx.)
Down Button Push −2dB volume decrease
Down Button Hold −2dB volume decrease every 500 ms (approx.)
Mute Button Push Toggles Mute on or off
Mute Button Hold No affect
*Pushing the Up button or the Down button will un-mute the Codec if it was muted.

In the third scheme, the Up and Down pins are connected to momentary SPST switches and the Mute pin is NOT connected. This scheme is selected by setting VCF1 and VCF0 to 10. TABLE 56 describes the button operations in this scheme.

TABLE 56
Up Button Push +2dB volume increase
Up Button Hold +2dB volume increase every 500 ms
(approx.)
Down Button Push −2dB volume decrease
Down Button Hold −2dB volume decrease every 500 ms
(approx.)
Up and Down Button Toggles Mute on or off
Push
UP and Down Button No affect
Hold
*Pushing the Up button or the Down button will un-mute the Codec if it was muted.

In the fourth scheme, the Mute and Down pins are connected to momentary SPST switches. The Mute pin is connect to the Up button momentary SPST switch. The Up pin is NOT connected. This scheme is selected by setting VCF1 and VCF0 to 11. Button functionality for the fourth scheme is described in TABLE 57.

TABLE 57
Up Button Push (Mute pin) +2dB volume increase
Up Button Hold (Mute pin) +2dB volume increase every 500 ms
(approx.)
Down Button Push −2dB volume decrease
Down Button Hold −2dB volume decrease every 500 ms
(approx.)
Up and Down Button Push Toggles Mute on or off
UP and Down Button Hold No affect
*Pushing the Up button or the Down button will un-mute the Codec if it was muted.

FIG. 27A-27BB and the accompanying text describe Codec Register 107 in further detail.

FIG. 27A is a diagram of the bitfield Index Address Register at address (WSSbase +0, R0). The bitfields are described below:

IA4-IA0 Index Address: These bits define the
address of the indirect register accessed
by the Indexed Data register (R1). These
bits are read/write;
IA4 Allows access to indirect registers 16-31.
Only available MODE 2. In MODE 1, this bit is
reserved;
TRD Transfer Request Disable: This bit, when set,
causes DMA transfers to cease when the INT bit
of the Status Register (R2) is set. Independent
for playback and capture interrupts:
0 - Transfers Enabled (playback and capture
DRQs occur uninhibited); and
1 - Transfers Disabled (playback and capture
DRQ only occur if INT bit is 0);
MCE Mode Change Enable: This bit must be set
whenever the current mode of WSS Codec 204 is
changed. The Data Format (I8, I28) and
Interface Configuration (I9) registers cannot
be changed unless this bit is set. The
exceptions are CEN and PEN which can be changed
“on-the-fly”. The DAC output is muted when MCE
is set; and
INIT WSS Codec Initialization: This bit is read as 1
when Codec 204 is in a state in which it cannot
respond to parallel interface cycles. This bit
is read-only.

Immediately after RESET (and once WSS Codec 204 has left the INIT state), the state of this register is: 010x0000 (binary - where ‘x’ indicates unknown). During initialization and software power down (PMl, 0=01), this register cannot be written and always reads 10000000 (80 h).

FIG. 27B is a diagram of the bitfield of Indexed Data Register (at address WSSbase+1, R1). The bitfield decoding is as follows:

ID7-ID0 Indexed Data register: These bits are the indirect register referenced by the Indexed Address register (R0).

During initialization and software power down of WSS Codec 204, this register cannot be written and is always read 10000000 (80h).

FIG. 27C is a diagram of the bitfield Status Register (at address WSSbase+2, R2, Read Only). The bitfield decodings are:

INT Interrupt Status: This indicates the status of
the internal interrupt logic of WSS Codec 204.
This bit is cleared by any write of any value
to this register. The IEN bit of the Pin
Control register (I10) determines whether the
state of this bit is reflected on the IRQ pin
assigned to the WSS Codec:
Read States:
0 - Interrupt inactive; and
1 - Interrupt active;
PRDY Playback Data Ready. The Playback Data
register (R3) is ready for more data. This bit
would be used when direct programmed I/O data
transfers are desired:
0 - Data still valid. Do not overwrite; and
1 - Data stale. Ready for next host data write
value;
PL/R Playback Left/Right Sample: This bit indicates
whether data needed is for the Left channel or
Right channel in all data formats except ADPCM.
In ADPCM it indicates whether the first two or
last two bytes of a 4-byte set (8 ADPCM
samples) are needed:
0 - Right or 3/4 ADPCM byte needed; and
I - Left, Mono, or 1/2 ADPCM byte needed;
PU/L Playback Upper/Lower Byte: This bit indicates
whether the playback data needed is for the
upper or lower byte of the channel. In ADPCM
it indicates, along with PL/R, which one of the
four ADPCM bytes is needed:
0 - Lower or 1/3 ADPCM byte needed; and
I - Upper, any 8-bit format, or 2/4 ADPCM byte
needed;
SER Sample Error: This bit indicates that a sample
was not serviced in time and an error has
occurred. The bit indicates an overrun for
capture and underrun for playback. If both the
capture and playback are enabled, the source
which set this bit cannot be determined.
However, the Alternate Feature Status register
(I24) can indicate the exact source of the
error;
CRDY Capture Data Ready. The Capture Data register
(R3) contains data ready for reading by the host. This
bit would be used for direct programmed I/O data
transfers:
0 - Data are stale. Do not reread the
information; and
1 - Data are fresh. Ready for next host data
read;
CL/R Capture Left/Right Sample: This bit indicates
whether the capture data waiting is for the
Left channel or Right channel in all audio data
formats except ADPCM. In ADPCM it indicates
whether the first two or last two bytes of a
4-byte set (8 ADPCM samples) are waiting:
0 - Right or 3/4 ADPCM byte available; and
1 - Left, Mono, or 1/2 ADPCM byte available
CU/L; and
CU/L Capture Upper/Lower Byte: This bit indicates
whether the capture data ready is for the upper
or lower byte of the channel. In ADPCM it
indicates, along with CL/R, which one of four
ADPCM bytes is available:
0 - Lower or 1/3 ADPCM byte available; and
1 - Upper, any 8-bit format, or 2/4 ADPCM byte
available.

Note on PRDY/CRDY: These two bits are designed to be read as one when action is required by the host. For example, when PRDY is set to one, the device is ready for more data; or when the CRDY is set to one, data are available to the host. The definition of the CRDY and PRDY bits are therefore consistent in this regard.

The PIO Data register is two registers mapped to the same address. Writes to this register sends data to the Playback Data register. Reads from this register will receive data from the Capture Data register.

During initialization and software power down of WSS Codec 204, this register cannot be written and is always read 10000000 (80 h).

FIG. 27D is a diagram of the bitfield Capture I/O Data Register (at address WSSbase+3, R3, Read Only). The bitfield encodings are as follows:

CD7-CF0 Capture Data Port. This is the control register where capture data are read during programmed I/O data transfers.

The reading of this register will increment a state machine so that the following read will be from the next appropriate byte in the sample. The exact byte which is next to be read can be determined by reading the Status register (R2). Once all relevant bytes have been read, the state machine will point to the last byte of the sample until a new sample is received from ADCs lll. Once the Status register (R2) is read and a new sample is received from the FIFO, the state machine and Status register (R2) will point to the first byte of the new sample.

During initialization and software power down of WSS Codec 204, this register cannot be written and is always read 10000000 (80 h).

FIG. 27E is a diagram of the bitfield of Playback I/O Data Register (at address WSSbase+3, R3, Write Only).

PD7-PD0 Playback Data Port. This is the control register where playback data are written during programmed IO data transfers.

Writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this port are ignored. The state machine is reset after the Status register (R2) is read, and the current sample is sent to the DACs 110 via the FIFOs 122.

The indirect registers are accessed by placing the appropriate index in the Index Address register (R0) and then accessing the Indexed Data register (R1) discussed above. A detailed description of each indirect register is given below. All reserved bits should be written zero and may be 0 or 1 when read. Note that indirect registers 16-31 are only available when the MODE 2 bit in MODE and ID register (I12) is set.

FIG. 27F is a diagram of the bitfield of Left ADC Input Control (I0, default=000x0000). The field decodings for this register are:

LAG3-LAG0 Left ADC Gain. The least significant bit
represents +1.5 dB, with 0000 = 0 dB;
res Reserved. Must write 0, could read as 0 or 1;
LMGE Left Mic Gain Enable: This bit enables the 20 dB
gain stage of the left mic input signal,
LMIC.LWSS1-LWSS0;
LWSS1-LWSS0 Left ADC Input Source Select. These bits
select the input source
for the left ADC channel:
0 - Left Line: LLINE;
1 - Left Auxiliary 1: LAUX12;
2 - Left Microphone: LMIC3; and
3 - Left Line Output Loopback.

FIG. 27G is a diagram of the bitfield of Right ADC Input Control (I1, default=000x0000). The bitfield decodings are:

RAG3-RAG0 Right ADC Gain. The least significant bit
represents +1.5 dB, with 0000 = 0 dB;
res Reserved. Must write 0, could read as 0
or 1;
RMGE Right Mic Gain Enable: This bit enables
the 20 dB gain stage of the right mic input
signal, RMIC; and
RWSS1-RWSS0 Right ADC Input Select. These bits select
the input source for the right ADC
channel:
0 - Right Line: RLINE;
1 - Right Auxiliary 1: RAUX1;
2 - Right Microphone: RMIC; and
3 - Right Line Out Loopback.

FIG. 27H is a diagram of the bitfield of Left Auxiliary #1 Input Control (I2, default=1xx01000). The bitfield decoding for this register is:

LX1G4-LX1G0 Left Auxiliary #1, LAUX1, Mix Gain. The
least significant bit represents 1.5 dB,
with 01000 = 0 dB;
res Reserved. Must write 0, could read as 0
or 1; and
LX1M Left Auxiliary #1 Mute. When set to 1,
the left Auxiliary #1 input, LAUX1, to the
mixer, is muted.

FIG. 27I is a diagram of the bitfield of Right Auxiliary #1 Input Control (I3, default=1xx01000). The bitfields are:

RX1G4-RX1G0 Right Auxiliary #1, RAUX1, Mix Gain. The
least significant bit represents 1.5 dB,
with 01000 = 0 dB;
res Reserved. Must write 0, could read as 0
or 1; and
RX1M Right Auxiliary #1 Mute. When set to 1,
the right Auxiliary #1 input, RAUX1, to
the mixer, is muted.

FIG. 27J is a diagram of the bitfield of Left Auxiliary #2 Input Control (I4, default=1xx01000). The bitfield decodings are:

Left Auxiliary #2, LAUX2, Mix Gain. The least
significant bit represents 1.5 dB, with 01000 =
0 dB;
res Reserved. Must write 0; and
LX2M Left Auxiliary #2 Mute. When set to 1, the left
Auxiliary #2 input, LAUX2, to the mixer, is
muted.

FIG. 27K is a diagram of the bitfields of Right Auxiliary #2 Input Control (I5, default=1xx01000). The bitfields decodings are:

RX2G4-RX2G0 Right Auxiliary #2, RAUX2, Mix Gain. The
least significant bit represents 1.5 dB,
with 01000 = 0 dB;
res Reserved. Must write 0, could read as 0
or 1; and
RX2M Right Auxiliary #2 Mute. When set to 1,
the right Auxiliary #2 input, RAUX2, to
the mixer, is muted.

FIG. 27L is a diagram of the bitfield of Left DAC Output Control (I6, default=1x000000).

LDA5-LDA0 Left DAC Attenuator. The least
significant bit represents −1.5 dB, with
000000 = 0 dB;
res Reserved. Must write 0, could read as 0
or 1; and
LDM Left DAC Mute. When set to 1, the left
DAC output to the mixer will be muted.

FIG. 27M is a diagram of the bitfield of Right DAC Output Control (I7, default=1x000000). The bitfields are decoded as:

RDA5-RDA0 Right DAC Attenuator. The least
significant bit represents −1.5 dB, with
000000 = 0 dB;
res Reserved. Must write 0, could read as 0
or 1; and
RDM Right DAC Mute. When set to 1, the right
DAC output to the mixer will be muted.

FIG. 27N is a diagram of the bitfield of Fs and Playback Data Format (I8, default=00000000). The bitfield decoding is as follows:

C2SL Clock 2 Source Select: This bit selects the
clock source used for the audio sample rates
for both capture and playback. Note that this
bit can be disabled by setting SRE in I22.
C2SL can only be changed while MCE (R0) is set:
0 - XTAL1 Typically 24.576 MHz; and
1 - XTAL2 Typically 16.9344 MHz;
CFS2-CFS0 Clock Frequency Divide Select: These bits
select the audio sample frequency for both
capture and playback. The actual audio sample
frequency depends on which clock source (C2SL)
is selected and its frequency. Frequencies
listed as N/A are not available because their
sample frequency violates the maximum
specifications; however, the decodes are
available and may be used with crystals that do
not violate the sample frequency
specifications. Note that these bits can be
disabled and controlled by I22. CFS2-CFS0 can
only be changed while MCE (R0) is set:
XTAL1 XTAL2
Divide 24.576 MHz 16.9344 MHz
0 - 3072  8.0 kHz  5.51 kHz
1 - 1536 16.0 kHz 11.025 kHz
2 - 896 27.42 kHz 18.9 kHz
3 - 768 32.0 kHz 22.05 kHz
4 - 448 N/A 37.8 kHz
5 - 384 N/A 44.1 kHz
6 - 512 48.0 kHz 33.075 kHz
7 - 2560  9.6 kHz  6.62 kHz; and
S/M Stereo/Mono Select: This bit determines how the
audio data streams are formatted. Selecting
stereo will result in alternating samples
representing left and right audio channels.
Mono playback plays the same audio sample on
both channels. Mono capture only captures data
from the left channel. In MODE 1, this bit is
used for both playback and capture. In MODE 2,
this bit is only used for playback, and the
capture format is independently selected via
I28. MCE (R0) or PMCE (I16) must be set to
modify S/M:
0 - Mono; and
1 - Stereo

C/L, FMT1, and FMT0 bits set the audio data format as shown in TABLE 58. In MODE 1, FMT1, which is forced low, FMT0, and C/L are used for both playback and capture. In MODE 2, these bits are only used for playback, and the capture format is independently selected via register I28. MCE (R0) or PMCE (I16) must be set to modify the lower four bits of this register. See Changing Audio Data Formats section for more details.

TABLE 58
FMT
FMT 0 C/L
†D7 D6 D5 Audio Data Format
0 0 0 Linear, 8-bit unsigned
0 0 1 u-law, 8-bit commanded
0 1 0 Linear, 16-bit two's complement,
Little Endian
0 1 1 A-law, 8-bit commanded
1 0 0 RESERVED
1 0 1 ADPCM, 4-bit, IMA compatible
1 1 0 Linear, 16-bit two's complement,
Big Endian
1 1 1 RESERVED
†FMT1 is not available in MODE 1 (forced to 0)

FIG. 27O is a diagram of the bitfield of Interface Configuration (I9, default=00x01000). The bitfields are decoded as follows:

PEN Playback Enable. This bit enables playback.
The WSS Codec will generate a DRQ and respond
to DACK signal when this bit is enabled and
PPIO = 0. If PPIO = 1, PEN enables PIO
playback mode. PEN may be set and reset
without setting the MCE bit:
0 - Playback Disabled (playback DRQ and PIO
inactive); and
1 - Playback Enabled;
CEN Capture Enabled. This bit enables the capture
of data. WSS Codec 204 will generate a DRQ and
respond to DACK signal when CEN is enabled and
CPIO = 0. If CPIO = 1, CEN enables PIO capture
mode. CEN may be set and reset without setting
the MCE bit:
0 - Capture Disabled (capture DRQ and PIO
inactive); and
1 - Capture Enabled;
SDC Single DMA Channel: This bit will force BOTH
capture and playback DMA requests to occur on
the Playback DMA channel. This bit forces WSS
Codec 204 to use one DMA channel. Should both
capture and playback be enabled in this mode,
only the playback will occur:
0 - Dual DMA channel mode; and
1 - Single DMA channel mode;
CAL1,0 Calibration: These bits determine which type
of calibration WSS Codec 204 performs whenever
the Mode Change Enable (MCE) bit, R0, changes
from 1 to 0. The number of sample periods
required for calibration is listed in
parenthesis:
0 - No calibration (0, 40 the first time);
1 - Converter calibration (136);
2 - DAC calibration (40); and
3 - Full calibration (168);
PPIO Playback PIO Enable: This bit determines
whether the playback data are transferred via
DMA or PIO:
0 - DMA transfers; and
I - PIO transfers;
CPIO Capture PIO Enable: This bit determines whether
the capture data are transferred via DMA or
PIO:
0 - DMA transfers; and
I - PIO transfers.

This register, except bits CEN and PEN, can only be written while in Mode Change Enable (either MCE or PMCE).

FIG. 27P is a diagram of the bitfields of Pin Control (I10, default=0000000x). The bitfields are:

res Reserved. Must write 0, could read as 0 or 1;
IEN Interrupt Enable: This bit enables the
interrupt pin. The Interrupt pin will reflect
the value of the INT bit of the Status register
(R2). The interrupt pin is active high:
0 -Interrupt disabled; and
1 - Interrupt enabled;
DTM DMA Timing Mode. Mode 2 only. When set, causes
the current DMA request signal to be deasserted
on the rising edge of the IOW or IOR strobe
during the next to last byte of a DMA transfer.
When DTM = 0 the DMA request is released on the
falling edge of the IOW or IOR during the last
byte of a DMA transfer;
DEN Dither Enable: When set, triangular pdf dither
is added before truncating the ADC 16-bit value
to 8-bit, unsigned data. Dither is only active
in the 8-bit unsigned data mode:
0 -Dither enabled; and
1 - Dither disabled;
OSM1-OSM0 These bits are enabled by Setting SRE = 1 in
register I22. These bits in combination with
DIV5-DIV0 and CS2 (I22) determine the current
sample rate of WSS Codec 204 when SRE = 1:
00 - 12 kHz < Fs â 24 kHz;
01 - Fs > 24 kHz;
10 - Fs â 12 kHz; and
11 - reserved; and.
XCTL1-XCTL0 XCTL Control:
0 - TTL logic low on XCTL1,0 pins; and
1 - TTL logic high on XCTL1,0 pins.

FIG. 27Q is a diagram of the bitfields of Error Status and Initialization (I11, Read Only, default=00000000). The bitfields are decoded as:

ORL1-ORL0 Overrange Left Detect: These bits determine the
overrange on the left ADC channel. These bits
are updated on a sample by sample basis:
0 - Less than −1.5 dB;
1 - Between −1.5 dB and 0 dB;
2 - Between O dB and 1.5 dB overrange; and
3 - Greater than 1.5 dB overrange;
ORR1-ORR0 Overrange Right Detect: These bits determine
the overrange on the Right ADC channel:
0 - Less than −1.5 dB;
1 - Between −1.5 dB and 0 dB;
2 - Between O dB and 1.5 dB overrange; and
3 - Greater than 1.5 dB overrange;
DRS DRQ Status: This bit indicates the current
status of the DRQs assigned to the WSS Codec:
0 - Capture AND Playback DRQs are presently
inactive; and
1 - Capture OR Playback DRQs are presently
active;
ACI Auto-calibrate In-Progress: This bit indicates
the state of calibration:
0 - Calibration not in progress; and
1 - Calibration is in progress;
PUR Playback underrun: This bit is set when
playback data has not arrived from the host in
time to be played. As a result, if DACZ = 0,
the last valid sample will be sent to DACs 110.
This bit is set when an error occurs and will
not clear until the Status register (R2) is
read; and
COR Capture overrun: This bit is set when the
capture data has not been read by the host
before the next sample arrives. The old sample
will not be overwritten and the new sample will
be ignored. This bit is set when an error
condition occurs and will not clear until the
Status register (R2) is read.

The SER bit in the Status register (R2) is simply a logical OR of the COR and PUR bits. This enables a polling host CPU to detect an error condition while checking other status bits.

FIG. 27R is a diagram of the bitfield of ODE and ID (I12, default=10xx1010). The bitfields are decoded as follows:

ID3-ID0 Codec ID: These four bits indicate the ID
and initial revisions of the codec.
Further revisions are expanded in indirect
register 25. These bits are read only:
0001 - Rev A; and
1010 - Rev B;
res Reserved. Must write 0, could read as 0
or 1;
MODE 2 MODE 2: Enables the expanded mode of the
CS4232. Must be set to enable access to
indirect registers 16-31 and their
associated features:
0 - MODE 1: CS4248 “look-alike”; and
1 - MODE 2: Expanded features.

FIG. 27S is a diagram of the bitfield of Loopback Control (I13, default=000000x0). The bitfields of this register are decoded as follows:

LBE Loopback Enable: When set to 1, the ADC data
are digitally mixed with data sent to the DACs:
0 -Loopback disabled; and
1 - Loopback enabled;
res Reserved. Must write 0, could read as 0 or 1;
and
LBA5-LBA0 Loopback Attenuation: These bits determine the
attenuation of the loopback from ADC to DAC.
The least significant bit represents −1.5 dB,
with 000000 = 0 dB.

FIG. 27T is a diagram of the bitfield of Playback Upper Base (I14, default=00000000) The bitfields of this register are decoded as follows:

PUB7-PUB0 Playback Upper Base: This register is the upper byte which represents the 8 most significant bits of the 16-bit Playback Base register. Reads from this register return the same value which was written. The Current Count registers cannot be read. When set for MODE 1 or SDC, this register is used for both the Playback and Capture Base registers.

FIG. 27U is a diagram of the bitfield of Playback Lower Base (I15, default=00000000). The bitfields of this register are decoded as Follows:

PLB7-PLB0 Lower Base Bits: This register is the lower byte which represents the 8 least significant bits of the 16-bit Playback Base register. Reads from this register return the same value which was written. When set for MODE 1 or SDC, this register is used for both the Playback and Capture Base registers.

FIG. 27V is a diagram of the bitfield of Alternate Feature Enable I (I16, default=00000000). The bitfields of this register are decoded as follows:

DACZ DAC Zero: This bit will force the output
of the playback channel to AC zero when an
underrun error occurs:
1 - Go to center scale; and
0 - Hold previous valid sample;
SPE Serial Port Enable. When enabled, audio
data from the ADCs is sent out SDOUT and
audio data from SDIN is sent to the DACs:
1 - Enable serial port; and
0 - Disable serial port. ISA Bus used for
audio data;
SF1, SF0 Serial Format. Selects the format of the
serial port when enabled by SPE:
0 - 64-bit enhanced;
1 - 64-bit;
2 - 32-bit; and
3 - Reserved;
PMCE Playback Mode Change Enable. When set, it
allows modification of the stereo/mono and
audio data format bits (D7-D4) for the
playback channel, I8. MCE in R0 must be
used to change the sample frequency;
CMCE Capture Mode Change Enable. When set, it
allows modification of the stereo/mono and
audio data format bits (D7-D4) for the
capture channel, I28. MCE in R0 must be
used to change the sample frequency in I8;
TE Timer Enable: This bit, when set, will
enable the timer to run and interrupt the
host at the specified frequency in the
timer registers; and
OLB Output Level Bit: Provided for backwards
compatibility, internally providing a
typical output full-scale voltage of
2.8 Vpp.

FIG. 27W is a diagram of the bitfield of Alternate Feature Enable II (I17, default=0000x000). The bitfields of this register are decoded as follows:

HPF High Pass Filter: This bit enables a
DC-blocking high-pass filter in the
digital filter of the ADC. This filter
forces the ADC offset to 0:
0 - disabled; and
1 - enabled;
XTALE Crystal Enable;
res Reserved. Must write 0, could read as 0
or 1;
APAR ADPCM Playback Accumulator Reset. While
set, the Playback ADPCM accumulator is
held at zero. Used when pausing a
playback stream; and
TEST Factory Test. These bits are used for
factory testing and must remain at 0 for
normal operation.

FIG. 27X is a diagram of the bitfield of Left Line Input Control (I18, default=1xx01000). The bitfields of this register are described as follows:

LLG4-LLG0 Left line, LLINE, Mix Grain. The least
significant bit represents 1.5 dB, with
01000 = 0 dB;
res Reserved. Must write 0, could read as 0
or 1; and
LLM Left Line Mute. When set to 1, the left
Line input, LLINE, to the mixer, is muted.

FIG. 27Y is a diagram of the bitfield of Right Line Input Control (I19, default=1xx01000). The bitfields of this register are decoded as follows:

RLG4-RLG0 Right Line, RLINE, Mix Gain. The least
significant bit represents 1.5 dB, with 01000 =
0 dB;
res Reserved. Must write 0, could read as 0 or 1;
and
RLM Right Line Mute. When set to 1, the Right Line
input. RLINE, to the mixer, is muted.

FIG. 27Z is a diagram of the bitfield of Timer Lower Base (I20, default=00000000). The bitfields of this register are decoded as follows:

TL7-TL0 Lower Timer Bits: This is the low order byte of the 16-bit timer base register. Writes to this register cause both timer base registers to be loaded into the internal timer, therefore, the upper timer register should be loaded before the lower. Once the count reaches zero, an interrupt is generated, if enabled, and the timer is automatically reloaded with these base registers.

FIG. 27AA is a diagram of the bitfield of Timer Upper Base (I21, default=00000000). The bitfields of this register are decoded as follows:

TU7-TU0 Upper Timer Bits: This is the high order
byte of the 16-bit timer. The time base
is determined by the clock source selected
from either C2SL in I8 or CS2 in I22;
C2SL = 0 - divide XTALI by 245 (24.576 MHz -
9.969 ms); and
C2SL = 1 - divide XTAL2 by 168 (16.9344 MHz -
9.92 ms).

FIG. 27AB is a diagram of the bitfield of Alternate Sample Frequency Select (I22, default=00000000). The bitfields of this register are decoded as follows:

CS2 Crystal 2 Select. This bit selects the clock
source used for generating the audio sample
rate:
0 - XTAL1 = 24.576 MHz; and
1 - XTAL2 = 16.9344 MHz;
DIV5 - DIV0 Clock Divider. These bits select the
audio sample frequency for both
capture and playback:
Fs = (2*XTAL)/(M*N);
XTAL = 24.576 MHz CS2 = 0;
XTAL = 16.9344 MHz CS2 = 1;
N = DIV5-DIV0;
16 ≦ N ≦ 49 for XTAL = 24.576 MHz;
12 ≦ N ≦ 33 for XTAL = 16.9344 MHz;
(M set by OSM1,0 in I10);
M = 64 for Fs > 24 kHz;
M = 128 for 12 kHz < Fs â 24 kHz; and
M = 256 for Fs â 12 kHz;
SRE Alternate Sample Rate Enable. When this bit is
set to a one, bits 0-3 of I8 will be ignored,
and the sample frequency is then determined by
CS2, DIV5-DIV0, and the oversampling mode bits
OSM1, OSM0 in I10.

FIG. 27AC is a diagram of the bitfield of Alternate Feature Enable III (I23, default=xxxxxxx0). The bitfields of this register are decoded as follows:

ACF ADPCM Capture Freeze. When set, the capture
ADPCM accumulator and step size are frozen.
This bit must be set to zero for adaptation to
continue. This bit is used when pausing a
ADPCM capture stream;
res Reserved. Must write 0, could read as 0 or 1;

FIG. 27AD is a diagram of the bitfield of Alternate Feature Status (I24, default=x0000000). The bitfields of this register are decoded as follows:

PU Playback Underrun: This bit, when set,
indicates that the DAC has run out of data and
a sample has been missed;
PO Playback Overrun: This bit, when set,
indicates that the host attempted to write data
into a full FIFO and the data was discarded;
CO Capture Overrun: This bit, when set, indicates
that the ADC had a sample to load into the FIFO
but the FIFO was full. In this case, this bit
is set and the new sample is discarded;
CU Capture Underrun: This bit indicates that the
host has read more data out of the FIFO than it
contained. In this condition, the bit is set
and the last valid byte is re-read by the host;
PI Playback Interrupt: This bit indicates that an
interrupt is pending from the playback DMA
count registers;
CI Capture Interrupt: This bit indicates that an
interrupt is pending from the capture DMA count
registers;
TI Timer Interrupt: This bit indicates that an
interrupt is pending from the timer count
registers; and
res Reserved. Must write 0, could read as 0 or 1.
The PI, CI, and TI bits are reset by writing a
“0” to the particular interrupt bit or by
writing any value to the Status register (R2).

FIG. 27AE is a diagram of the bitfield of Mono Input and Output Control (I26, default=101x0000). The bitfields of this register are decoded as follows:

MIA3-MIA0 Mono Input Attenuation. When MIM is 0, these
bits set the level of MIN summed into the
mixer. MIA0 is the least significant bit and
represents 3 dB attenuation, with 0