US 6331976 B1 Abstract A communication system (
10) comprising circuitry (RCVR1) for receiving a bitstream packet (P). The bitstream packet comprises at least three groups of bits: (i) a plurality of preamble prefix bits having a predetermined bit pattern; (ii) a plurality of synchronization word bits following the plurality of preamble prefix bits; and (iii) a plurality of data bits following the plurality of synchronization word bits. The system further includes circuitry for completing a carrier and clock recovery operation in response to receiving a first portion of the plurality of preamble prefix bits. Still further, the system includes circuitry (30) for determining a location of the plurality of synchronization word bits within the bitstream packet. The circuitry for determining comprises circuitry (36) for performing a number of comparisons between a bit test pattern vector (32) and a sample vector (34) of bits from the bitstream packet. The bit test pattern vector and the sample vector of bits both change for each of the number of comparisons. For at least one of the number of comparisons the sample vector of bits comprises a second portion of the plurality of preamble prefix bits following the first portion of the plurality of preamble prefix bits. Further, for at least some of the number of comparisons, the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises one or more bits matching the synchronization word bits.Claims(32) 1. A communication system, comprising:
circuitry for receiving a bitstream packet, the bitstream packet comprising:
a plurality of preamble prefix bits having a predetermined bit pattern;
a plurality of synchronization word bits following the plurality of preamble prefix bits; and
a plurality of data bits following the plurality of synchronization word bits;
circuitry for completing a carrier and clock recovery operation in response to receiving a first portion of the plurality of preamble prefix bits;
circuitry for determining a location of the plurality of synchronization word bits within the bitstream packet, the circuitry for determining comprising circuitry for performing a number of comparisons between a bit test pattern vector and a sample vector of bits from the bitstream packet;
wherein the bit test pattern vector and the sample vector of bits both change for each of the number of comparisons;
wherein for at least one of the number of comparisons the sample vector of bits comprises a second portion of the plurality of preamble prefix bits following the first portion of the plurality of preamble prefix bits; and
wherein for at least some of the number of comparisons the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises one or more bits matching the synchronization word bits.
2. The communication system of claim
1 wherein, for all of the number of comparisons except one of the comparisons, the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises one or more bits matching at least a portion of the synchronization word bits.3. The communication system of claim
2 wherein, for the except one of the comparisons, the bits in the bit test pattern vector match the bits in the synchronization word bits.4. The communication system of claim
3 wherein the circuitry for determining the location of the plurality of synchronization word bits within the bitstream packet further comprises:circuitry for providing a measure of accuracy for each of the number of comparisons; and
circuitry for storing the measure of accuracy for each of the number of comparisons.
5. The communication system of claim
1 wherein for at least some of the number of comparisons the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises a number of bits matching all of the synchronization word bits.6. The communication system of claim
5 wherein, for all of the number of comparisons except one of the comparisons, the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises a number of bits matching all of the synchronization word bits.7. The communication system of claim
6 wherein, for the except one of the comparisons, the bits in the bit test pattern vector match the bits in the synchronization word bits.8. The communication system of claim
7 wherein the circuitry for determining the location of the plurality of synchronization word bits within the bitstream packet further comprises:circuitry for providing a measure of accuracy for each of the number of comparisons; and
circuitry for storing the measure of accuracy for each of the number of comparisons.
9. The communication system of claim
1 wherein the circuitry for determining the location of the plurality of synchronization word bits within the bitstream packet further comprises:circuitry for providing a measure of accuracy for each of the number of comparisons; and
circuitry for storing the measure of accuracy for each of the number of comparisons.
10. The communication system of claim
9:wherein the bit test pattern vector is represented by a positive one for each bit of a first logical state and by a negative one for each bit of a second logical state different than the first logical state;
wherein the sample vector of bits is represented by a positive one for each bit of the first logical state and by a negative one for each bit of the second logical state; and
wherein the circuitry for performing a number of comparisons between the bit test pattern vector with the sample vector of bits comprises:
circuitry for performing a bitwise multiplication of the bit test pattern vector with the sample vector of bits; and
circuitry for summing a product of each of the bitwise multiplication operations.
11. The communication system of claim
10 wherein the circuitry for determining the location of the plurality of synchronization word bits within the bitstream packet determines that the synchronization word bits are located in a position within the bitstream packet corresponding to the largest of the stored measures of accuracy.12. The communication system of claim
9 wherein the circuitry for determining the location of the plurality of synchronization word bits within the bitstream packet determines that the synchronization word bits are located in a position within the bitstream packet corresponding to the largest of the stored measures of accuracy.13. The communication system of claim
1 wherein the second portion of the plurality of preamble prefix bits immediately follows the first portion of the plurality of preamble prefix bits.14. The communication system of claim
1 wherein the circuitry for determining the location of the plurality of synchronization word bits within the bitstream packet further comprises circuitry for correcting the circuit,y for performing a number of comparisons, wherein the correcting circuitry is responsive to a normalized variance of additive Gaussian noise signal in the bitstream packet.15. The communication system of claim
1 wherein the bitstream packet comprises a time division multiple access bitstream packet.16. The communication system of claim
9 wherein t he circuitry for receiving and the circuitry for determining form a first receiver unit, and wherein the system further comprises a transmitter unit for transmitting the bitstream packet to the first receiver unit.17. The communication system of claim
16:wherein the bitstream packet is one packet in a plurality of bitstream packets;
wherein the first receiver unit receives each of the plurality of bitstream packets; and
wherein for each of the plurality of bitstream packets, the circuitry for determining determines a location of a plurality of synchronization word bits within the corresponding one of the plurality of bitstream packets.
18. The communication system of claim
17 wherein, for each of the plurality of bitstream packets, the circuitry for performing performs a number of comparisons between a test pattern vector and a sample vector of bits from the bitstream packet corresponding to the bitstream packet;wherein, for each of the plurality of bitstream packets, the bit test pattern vector and the sample vector of bits both change for each of the number of comparisons corresponding to the bitstream packet;
wherein, for each of the plurality of bitstream packets, for at least one of the number of comparisons corresponding to the bitstream packet the sample vector of bits comprises a second portion of the plurality of preamble prefix bits following the first portion of the plurality of preamble prefix bits; and
wherein, for each of the plurality of bitstream packets, for at least some of the number of comparisons corresponding to the bitstream packet the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises one or more bits matching the synchronization word bits.
19. The communication system of claim
17:and further comprising a plurality of receiver units in addition to the first receiver unit; and
wherein each of the plurality of bitstream packets is directed to a different one of either the first receiver unit or one of the plurality of receiver units.
20. The communication system of claim
16:wherein the bitstream packet further comprises a code for identifying the first receiver unit;
wherein the code immediately follows the plurality of synchronization word bits; and
wherein the plurality of data bits immediately follows the code.
21. A method of operating a communication system, comprising:
receiving a bitstream packet, the bitstream packet comprising:
a plurality of preamble prefix bits having a predetermined bit pattern;
a plurality of synchronization word bits following the plurality of preamble prefix bits; and
a plurality of data bits following the plurality of synchronization word bits;
completing a carrier and clock recovery operation in response to receiving a first portion of the plurality of preamble prefix bits;
determining a location of the plurality of synchronization word bits within the bitstream packet by performing a number of comparisons between a bit test pattern vector and a sample vector of bits from the bitstream packet;
wherein the bit test pattern vector and the sample vector of bits both change for each of the number of comparisons;
wherein for at least one of the number of comparisons the sample vector of bits comprises a second portion of the plurality of preamble prefix bits following the first portion of the plurality of preamble prefix bits; and
wherein for at least some of the number of comparisons the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises one or more bits matching the synchronization word bits.
22. The method of claim
21 wherein the performing step comprises, for all of the number of comparisons except one of the comparisons, performing the number of comparisons such that the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises one or more bits matching at least a portion of the synchronization word bits.23. The method of claim
22 wherein the performing step comprises, for the except one of the comparisons, performing the one comparison such that the bits in the bit test pattern vector match the bits in the synchronization word bits.24. The method of claim
23 wherein for at least some of the step of performing a number of comparisons the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises a number of bits matching all of the synchronization word bits.25. The method of claim
24 wherein the performing step comprises, for all of the number of comparisons except one of the comparisons, performing the number of comparisons such that the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises a number of bits matching all of the synchronization word bits.26. The method of claim
25 wherein the performing step comprises, for the except one of the comparisons, performing the one comparison such that the bits in the bit test pattern vector match the bits in the synchronization word bits.27. The method of claim
21 wherein the step of for determining the location of the plurality of synchronization word bits within the bitstream packet further comprises:providing a measure of accuracy for each of the number of comparisons; and
storing the measure of accuracy for each of the number of comparisons.
28. The method of claim
24:wherein the bit test pattern vector is represented by a positive one for each bit of a first logical state and by a negative one for each bit of a second logical state different than the first logical state;
wherein the sample vector of bits is represented by a positive one for each bit of the first logical state and by a negative one for each bit of the second logical state; and
wherein the step of performing a number of comparisons between the bit test pattern vector with the sample vector of bits comprises:
performing a bitwise multiplication of the bit test pattern vector with the sample vector of bits; and
summing a product of each of the bitwise multiplication operations.
29. The method of claim
26 wherein the step of determining the location of the plurality of synchronization word bits within the bitstream packet determines that the synchronization word bits are located in a position within the bitstream packet corresponding to the largest of the stored measures of accuracy.30. The method of claim
21 wherein the second portion of the plurality of preamble prefix bits immediately follows the first portion of the plurality of preamble prefix bits.31. The method of claim
21 wherein the step of determining the location of the plurality of synchronization word bits within the bitstream packet further comprises correcting the circuitry for performing a number of comparisons, wherein the correcting step is responsive to a normalized variance of additive Gaussian noise signal in the bitstream packet.32. The method of claim
21 wherein the bitstream packet comprises a time division multiple access bitstream packet.Description Not Applicable. Not Applicable. The present embodiments relate to data communications, and are more particularly directed to circuits, systems, and methods for synchronization word detection in bitstream communications apparatus. By way of example, therefore, the background and embodiments are discussed below in the context of time division multiple access (“TDMA”) apparatus. TDMA bitstream systems are typically implemented in the context of wireless communications, and also may exist in other environments where it is desirable to communicate a common bitstream to various receivers where each receiver is able to distinguish information intended for it versus information intended for a different receiver. In this regard and as detailed later, a TDMA bitstream includes packets of information. Each information packet generally includes user data which is preceded in the packet by what is referred to in this document as a synchronization word. The synchronization word is a bit pattern known to each receiver. Thus, a receiver may detect the synchronization word as a basis for defining the boundaries of other information in the packet. More specifically, typically following the synchronization word is a receiver identifier, which itself is followed by user data intended for the identified receiver. Consequently, by detecting the synchronization word, the receiver may then determine the boundary of the synchronization word itself. Typical systems detect the synchronization word after having received a portion, but not all, of the synchronization word. Thus, once a sufficient portion of the synchronization word has been received and determined to be a part of the synchronization word, the receiver may then determine the end of the synchronization word and thereby define the beginning and end of the other information within the packet (i.e., the receiver identifier and the user data). Given the above, one skilled in the art will appreciate the need to accurately and efficiently identify the synchronization word in TDMA communications. Accuracy in detecting the synchronization word is critical because a failure to identify the synchronization word will cause a failure of communication with respect to the remainder of the information packet. Efficiency in detecting the synchronization word manifests itself in various manners. For example, one factor affecting the ability to detect the synchronization word is based on the power of the transmitted signal. In this regard, a higher power output provides a larger amplitude in transmitted signal. This increased amplitude may be used to overcome any noise in the signal, thereby improving the ability to properly detect the synchronization word by the receiver(s). However, as is common in electronic circuit implementation, an increased power requirement is often considered inefficient. Thus, efficiency suggests or may require reducing the power output signal while still obtaining a satisfactory probability of proper detection of the synchronization word. Another efficiency example arises in the timing of synchronization word detection. Particularly, note that an amount of elapsed time may be measured from the time the beginning of the synchronization word is received by a receiver and the time the receiver thereafter detects that the incoming information constitutes the synchronization word. If this elapsed time becomes too large, it may be considered a delay on the operation of the receiver. Such a delay also may be considered in evaluating the efficiency of the receiver. As yet another example, some prior art systems provide impressive levels of accuracy in synchronization word detection, but do so by requiring specific attributes of the signal to be known to the receiver. For example, one such system, as described below, requires that the receiver have access to the variance of the signal-to-noise ratio (“SNR”) of the incoming signal in order to identify an incoming synchronization word. This SNR variance may be difficult and complex to ascertain. Additionally, greater computational ability is likely to be required of the receiver to detect the incoming synchronization word even given the SNR variance. In some systems, therefore, these additional demands may be deemed inefficient given design or other criteria considered for the system. In view of the above, there arises a need to address the drawbacks of the prior art. Thus, the inventive embodiments below contemplate such drawbacks and provide improved circuits, systems, and methods for synchronization word detection, such as in TDMA apparatus. In one embodiment, there is a communication system comprising circuitry for receiving a bitstream packet. The bitstream packet comprises at least three groups of bits: (1) a plurality of preamble prefix bits having a predetermined bit pattern; (2) a plurality of synchronization word bits following the plurality of preamble prefix bits; and (3) a plurality of data bits following the plurality of synchronization word bits. The system further includes circuitry for completing a carrier and clock recovery operation in response to receiving a first portion of the plurality of preamble prefix bits. Still further, the system includes circuitry for determining a location of the plurality of synchronization word bits within the bitstream packet. The circuitry for determining comprises circuitry for performing a number of comparisons between a bit test pattern vector and a sample vector of bits from the bitstream packet. The bit test pattern vector and the sample vector of bits both change for each of the number of comparisons. For at least one of the number of comparisons the sample vector of bits comprises a second portion of the plurality of preamble prefix bits following the first portion of the plurality of preamble prefix bits. Further, for at least some of the number of comparisons, the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises one or more bits matching the synchronization word bits. Other circuits, systems, and methods are also disclosed and claimed. FIG. 1 illustrates a communication system as an example of a configuration in which both the prior art and the present inventive embodiments may be implemented; FIG. 2 illustrates a time division multiple access (“TDMA”) bitstream; FIG. 3 illustrates the breakdown of information in a single packet of the bitstream of FIG. 2; FIG. 4 FIG. 4 FIG. 4 FIG. 5 illustrates a prior art system for comparing bits in a known synchronization word to corresponding bits in a bit window which shifts along the incoming TDMA bitstream; FIG. 6 illustrates an example of the bits which are compared according to the system of FIG. 5 over a total of five successive shifts of the bit window; FIG. 7 illustrates a first inventive embodiment for comparing bits in a test pattern vector to corresponding bits in an incoming bitstream, where the test pattern vector includes only the synchronization word for a first comparison and for each successive comparison the test pattern vector adds a bit of the preamble prefix and removes a bit of the synchronization word; FIG. 8 illustrates an example of the bits which are compared according to the system of FIG. 7 over a total of seven successive comparisons; FIG. 9 illustrates a graph of the results of two prior art approaches and two of the present inventive embodiments; FIG. 10 illustrates a second inventive embodiment for comparing bits in a test pattern vector to corresponding bits in an incoming bitstream, where the test pattern vector includes only the synchronization word for a first comparison and for each successive comparison the test pattern vector adds a bit of the preamble prefix and; FIG. 11 illustrates an example of the bits which are compared according to the system of FIG. 10 over a total of seven successive comparisons. Before proceeding with a detailed discussion of the preferred inventive embodiments and by way of presenting a more extensive introduction, FIGS. FIG. 1 illustrates a diagram of a wireless system designated generally at FIG. 2 illustrates a sequence of binary packets which as a whole form a TDMA bitstream as communicated from transmnitter TR to receivers RCVR Given the conventions established thus far, one skilled in the art may appreciate the terms “time division multiple access.” Specifically, for a given time period such as is required to communicate a single group of packets, that time period is divided into slots (i.e., packets) so that multiple receivers may each access meaningful information during a part of that time period. In other words, for the N receivers, each is designated a slot in the time period, and that slot repeats for each group of successive packets transmitted by the receiver. Again by way of example, receiver RCVRM is allotted the first slot in the time divided sequence of FIG. 2, so the first packet in each group is directed to receiver RCVR FIG. 3 illustrates a breakdown of the various portions of serial information implemented in each of packets P The preamble may be referred to in the art in other manners such as a header, but for purposes of consistency is referred to as the preamble for the remainder of this document. The preamble includes two portions of binary information which are further illustrated in FIG. The preamble prefix typically consists of an alternating bit sequence, such as a 1 followed by a 0 followed by a 1 and so forth as shown by way of example in FIG. The synchronization word consists of a binary sequence which is distinguishable from the preamble prefix, and is further distinguishable from the remainder of the packet bits as explored later. The synchronization word may vary in length for different systems, but for a given system is fixed and is commonly on the order of 16 to 80 bits. For example, the Digital European Cordless Telephone (“DECT”) system implements a synchronization word of 16 bits, while the MIL-STD-188-183 standard implements a synchronization word of 74 bits. In any event, note that the synchronization word may be any set of bits which serves the purpose of distinguishing itself from both the preamble prefix as well as the information to follow the synchronization word. Accordingly, once the CCR function is accomplished by a receiver in connection with a first part of the prefix bits, the beginning of the synchronization word will follow at some number of zero or more bits thereafter and provide a separator which defines the end of the sequence of prefix bits. Thus, and as appreciated later, each receiver of FIG. 1 operates to detect the synchronization word and, in doing so, is able to conclude that the preamble prefix is complete. Moreover, by determining the location of the last bit (i.e., the end) of the synchronization word, each receiver is therefore notified, by definition, that the preamble is complete and that the remaining two portions (i.e., the receiver identifier and the user data) of the packet are the next presented bits in the packet. Before proceeding, note further that the preferred embodiments discussed later are particularly directed to detecting the synchronization word. Thus, by way of example, a random pattern of bits is shown in FIG. 3 for the synchronization word, where this pattern is used for the remainder of the document to demonstrate the preferred embodiment aspects for detecting a synchronization word. Clearly, however, other patterns of bits may be used for the synchronization word. The receiver identifier of packet P in FIG. 3 performs the simple function its name suggests, that is, it identifies to which of the receivers the particular packet is directed. By way of example and returning to FIG. 1, if packet P The user data of packet P in FIG. 3 merely represents any type of data which may be transmitted using a serial data stream. Thus, such data may be representative of a type of signal where complete binary precision is not required. Examples of these systems may include audio or video signals. On the other hand, the user data may be exact binary representations of digital characters or the like, where clearly a higher measure of integrity is required of the data. In any event, once a receiver has performed its CCR, located the synchronization word, and determined that it is identified in the receiver identifier of a packet, the receiver may then process the user data in whatever manner is consistent with the function of such data. Having explained the various portions of each TDMA packet, recall that it was earlier introduced that the present embodiments are directed to the detection of the synchronization word in each such packet. In this regard and by way of further introduction, note that the format of the preamble suggests that at some point while the preamble prefix is being received, the CCR function will be complete. However, to ensure proper CCR operation, it is likely the case that additional preamble prefix bits will be received after this point. In other words, it is expected that the number of preamble prefix bits is sufficiently large so that CCR completes before the beginning of the synchronization word is encountered. Given this expectation, it is then required that the receiver determine which of the bits in the incoming packet are still part of the latter portion of the preamble prefix, or in other words to determine the location of the beginning portion of the synchronization word. To further demonstrate these principles, FIG. 4 FIG. 4 By way of further example, FIG. 4 FIG. 5 illustrates a prior art system System Storage register
Storage register It is known in the TDMA art that a TDMA bitstream is transmitted using pulse shaping, where each transmitted bit is sent via an analog synch pulse. Typically, such a synch pulse has a considerable amplitude peak (either positive or negative for either a binary 1 or 0, respectively) but is both preceded and followed by lesser amplitude variations. A receiver receiving each such pulse samples the analog signal and based on its timing recover measures a sample at the expected location of the peak of the pulse. Moreover, this same, through filtering and analog-to-digital conversion, produces an integer number K bits. Thus, for an example where K equals eight, then a given synch pulse is represented by an eight-bit number having a value between −128 and 127. For known “soft decision based receivers”, they continue to process each K bit group, thereby increasing complexity but typically also increasing accuracy. Accordingly, for the bit group convention y Given the preceding, note that the present embodiments have equal applicability to both hard and soft decision receivers, and indeed may apply to other types of receivers as will be ascertainable by one skilled in the art. In any event, as introduced above, it should now be appreciated that a bit group for either approach is represented in this document by y
System A first technique which may be achieved by system where the variables not already-defined are: {circumflex over (m)} is the predicted value of the in remaining preamble prefix bits following the preamble prefix bit which completed CCR, and where 0 <{circumflex over (m)}<M; and τ is a threshold established as discussed below. The details of the application of Equation 1 are shown by way of example below. At this point, however, note as a preliminary observation that Equation 1 repeats for each value of it until the threshold τ is either reached or exceeded. Each repetition corresponds to a shift in the bits in storage register FIG. 6 provides an alternative illustration of the bits at issue, as well as the iterative operation for successive increments of {circumflex over (m)}. The top row of FIG. 6 illustrates, from the information of FIGS. 3 and 4 Looking to the third row of FIG. 6, it illustrates the location of window W for a first analysis of Equation 1, that is, where {circumflex over (m)}=0. Recall that {circumflex over (m)} is the predicted value of the m remaining preamble prefix bits which follow the preamble prefix bit which completed CCR. Thus, the location of the window in the third row of FIG. 6 is based on a prediction that there are no remaining preamble bits after the bit which completed CCR (i.e., in {circumflex over (m)}=0). In this case, the prediction is that the next bit after the bit which completed CCR is the first bit in the synchronization word. The application of Equation 1 acts to derive of measure of this prediction. Specifically, in this instance, Equation 1 reads as shown below in Equation 1.1: According to Equation 1.1, each bit representation of the incoming bitstream y Thus, the result of 0 is less than τ=12. Note further that the low result of Equation 1.1 suggests that the {circumflex over (m)}=0 prediction was inaccurate, that is, the next bit following the bit which concluded CCR was determined not to be the first bit of the synchronization word. Consequently, the process repeats for the next iteration of {circumflex over (m)}, as discussed immediately below. Looking to the fourth row of FIG. 6, it illustrates the location of bit window W for a second analysis of Equation 1, that is, where {circumflex over (m)}=1. Thus, the fourth row of FIG. 6 is based on a prediction that there is one preamble prefix bit after the bit which completed CCR; in other words, for {circumflex over (m)}=1 it is predicted that there is one additional preamble prefix bit, and after that additional bit is the first bit in the synchronization word. The application of Equation 1 once again acts to derive of measure of this prediction, and reads as shown below as Equation 1.2: From the subscript of y in Equation 1.2 one skilled in the art should now appreciate its effect in shifting the comparison analysis of the values in storage registers Once again, the result of −2 is less than τ=12 and the low result of Equation 1.2 suggests that the {circumflex over (m)}=1 prediction was inaccurate. In other words, the assumption that there was one bit left in the preamble prefix before reaching the synchronization word was not the case. Consequently, yet again the process repeats for the next iteration of {circumflex over (m)}, as discussed immediately below. Looking to the fifth and sixth rows of FIG. 6, one skilled in the art should now appreciate from the previous examples how these additional rows illustrate the location of bit window W for a third and fourth analysis of Equation 1, that is, where in {circumflex over (m)}=2 and {circumflex over (m)}=3, respectively. Thus, for the fifth row Equation 1 reads as shown in Equation 1.3 below and for the sixth row Equation 1 reads as shown in Equation 1.4 below: From the subscripts of y in Equations 1.3 and 1.4, once again it should be appreciated how bit window W is shifting to include different bits in storage register For both Equations 1.3 and 1.4, the corresponding results are less than τ=12, thereby suggesting that predictions of {circumflex over (m)}=2 or {circumflex over (m)}=3 are inaccurate. As still another iteration, therefore, the process repeats for a value of {circumflex over (m)}=4 which, as shown below, ends the analysis of Equation 1 for the current example. Looking to the seventh row of FIG. 6, its location of bit window W represents the instance where {circumflex over (m)}=4. Before reaching the actions of Equation 1 in this context, note that each bit y Consequently, Equation 1.5 yields: As anticipated from the seventh row since each entry in bit window W matches a corresponding bit of the representation of the synchronization word, Equation 1.5 produces a result equal to τ, that is, equal to 12. In other words, it is now determined that the prediction of {circumflex over (m)}=4 is accurate. Accordingly, there were four bits (i.e., {circumflex over (m)}=4) left in the preamble prefix once CCR was complete, after which was located the synchronization word. Thus, once the iteration of Equation 1.5 is complete, then the prior art process has identified the synchronization word. As a result, it may determine the location of the end of that word, thereby further defining the beginning and end of the remaining portions of the TDMA packet. Having presented one prior art technique for synchronization word detection, the reader is now directed to a discussion of the threshold of Equation 1 as represented by τ. Specifically, the preceding example illustrates that Equation 1 reaches a maximum value at the point in which bit window W encloses bits which match the synchronization word. Moreover, the above demonstrates that the maximum result of Equation 1 equals L (i.e., the number of bits in the synchronization word). In other words, at this maximized point, each product y As each bit is received in the incoming TDMA bitstream, note that its amplitude may be affected by an additional noise signal. Consequently, this noise may cause the binary value of each such bit to be misinterpreted. In the case of the representation technique mentioned above, therefore, a binary 0 which is tainted by noise may be erroneously represented as a +1 rather than a −1. Similarly, a binary 1 which is tainted by noise may be erroneously represented as a −1 rather than a +1. If such an erroneous representation occurs, then the result of Equation 1 will not reach L. Thus, the addition of noise increases the complexity of the considerations for synchronization word detection. One approach to accommodate this noise effect is to use the system described above with respect to Equation 1, but to set τ to some level lower than L, with the difference therefore taking into account this noise contribution. By reducing τ, however, the accuracy of the Equation 1 approach is reduced. Other approaches to compensate for this noise effect are also presented below. Such approaches may provide better results, but for various reasons provide drawbacks as well. One approach to compensate for the above-described noise effect is to increase the power requirements of transmitter TR. In other words, by amplifying the transmission signal, the signal-to-noise ratio (“SNR”) of the received signal is reduced, assuming the noise is not amplified to a comparable level. Under such an approach, ideally the amplitude of each transmitted bit is raised to a level to sufficiently overwhelm any contribution of an added noise signal. Consequently, any receiver of the signal properly interprets each incoming bit during synchronization word detection. Thus, τ may be set at or near L with a fair amount of confidence in the accuracy of the ability to detect an incoming synchronization word. While this technique may further enhance the effectiveness of Equation 1, it also provides drawbacks. For example, it is often the case that power requirements are limited for various reasons. Thus, a technique which seeks to raise those power requirements may not be acceptable. Even if deemed acceptable, such a technique may not be considered efficient. For example, the added power requirements may affect other considerations in the design. Still other examples will be ascertainable by one skilled in the art. Another approach to compensate for the above-described noise effect is to modify Equation 1 in a manner which eliminates the threshold value τ. This alternative approach repeats iterations of the calculations of Equation 1 and, after all calculations are complete, determines that the synchronization word was encompassed within a window W for the iteration of the Equation which provided the maximum result. Mathematically stated, this alternative is represented by the following Equation 2: Equation 2 indicates that, for each value of {circumflex over (m)} between 0 and M (i.e., for M+1 iterations), the summation is performed with each summation being of L products of y While the approach of Equation 2 detects a synchronization word in a manner to alleviate the noise effects described above, note that it also provides certain drawbacks. For example, the approach of Equation 2 requires iterations over the entire range of zero through M. In contrast, recall that the approach of Equation 1 stops once the threshold τ is reached and, therefore, may reach its result sooner. In other words, the Equation 2 technique requires a greater delay before it reaches its determination. In addition, to accomplish the entire analysis over all iterations for Equation 2, there must be some technique directed to saving the history over all iterations, so that the iteration corresponding to the maximum result may be identified from that history. This history requirement may be considered a drawback in some situations as it may increase circuit and processing demands. As a final prior art approach, Mr. Massey derived the following Equation 3 as a technique for synchronization word detection which utilizes the same sliding bit window approach described above, but further compensations for noise effects as described below: where, y, c, and L are the same as defined for the earlier approaches; and σ is the normalized variance of additive Gaussian noise signal in the incoming TDMA stream. Intuitively, the larger the SNR, the smaller the value of σ. Equation 3 has been shown in the art to provide improved results over the approaches of Equations 1 and 2. However, it too has drawbacks. For example, note that Equation 3 requires an additional value of variance (i.e., σ) and further requires a hyberbolic cosine evaluation given the effect of that variance. As a practical matter, therefore, this variance must be determined, and ideally is constantly updated as TDMA communications occur. Naturally, therefore, and as known in the art, there is considerable extra complexity involved due to these requirements. Given these drawbacks as well as the various considerations set forth above, the present inventor provides below improved embodiments which achieve results which in efficiency either exceed or approximate those of the above-discussed prior art, and which may be implemented in manners which are less complex as compared to the corresponding prior art technique which achieves comparable or even less efficient results. Having detailed the prior art, the discussion now turns to the preferred embodiments. In this regard, FIG. 7 illustrates a system System Storage register After the preamble prefix bit which completes CCR is encountered, then the goal of the preferred embodiments is to detect the synchronization word. However, in this endeavor, there are between 0 and M bits remaining of the preamble prefix before the synchronization word (i.e., vector C) is encountered. Let these preamble prefix bits be defined by the vector B as in Equation 4 below: Recall that the preamble prefix bits are a sequence of bits which, for a given system, alternate in some known manner. As recognized by the present inventor, however, the prior art techniques described above discard the known information provided by these bits when detecting a synchronization word. In sharp contrast, and as detailed below, the inventive embodiments presented in this document use this information to achieve efficient and improved synchronization word detection. In this regard, and returning to the definition of the test pattern vector S as stored in storage register
Given Equations 5.1 through 5.5, as well as the illustration of FIG. 7, one skilled in the art should appreciate now that storage register Turning now to storage register System The details of the application of Equation 6 are shown by way of example below. At this point, note that Equation 6 repeats for all values of {circumflex over (m)} and the solution is that iteration which presents the maximum result. Each repetition after the first corresponds to a shift in the test pattern vector S in storage register FIG. 8 provides an illustration of the successive operations for successive steps of incrementing {circumflex over (m)} to implement Equation 6 using system Looking to the third row of FIG. 8, it first illustrates the fixed bits in storage register According to Equation 6.1, for the length L (e.g., 12) of the synchronization word, each bit representation of the incoming stream y Since Equation 6 repeats to determine a maximum over M+1 results, then the remaining illustrations of FIG. 8 (i.e., rows 4 through 9) depict each of those instances. For purposes of the present example, note that M is assumed to be six, thereby giving rise to the total of seven different scenarios illustrated in FIG.
Having determined the values in Table 3, the solution to Equation 6 is completed by identifying that value of {circumflex over (m )} which produced the highest result. Given the results of Table 3, the entry corresponding to {circumflex over (m)}=4 produces this solution, and thus, system Having demonstrated the operation of one of the present inventive embodiments, FIG. 9 illustrates a graph Before discussing the specific plots of graph In addition to the plots described above, note that graph Introducing a distinction between the following inventive embodiment and the one described above, let us now look to an alternative definition of the vector S which, recall, is the test sample pattern used for comparison with the incoming TDMA bitstream. Specifically, recall in connection with the introduction to Equations 5.1 through 5.5 that it was stated that vector S is altered for each iteration to include a portion of the vector B concatenated with either a portion or all of the synchronization word vector C. The earlier discussion presented the former instance where the concatenation was only with a portion of the synchronization word vector. Note now, however, than an alternative inventive embodiment is obtained by concatenating the same portion of B (i.e., those bits which follow the preamble prefix bit which completed CCR) with the entire synchronization word vector C. Thus, for this alternative embodiment, the successive vectors S
Thus, S Let D
where, D is a vector of dimension i, consisting of random data, with P(d If A=(a
where, p N models the additive white Gaussian noise, that is, N=(n n Upon receiving the random sample vector Y, the task of the receiver is to determine where the synchronization word lies, or equivalently, to estimate m. An optimal receiver estimates Y to be Y In view of Equation 8 then Equation 9 is the same as the following Equation 10: Since the random variables n Now, recalling that d Since n are (0,σ) Gaussian random variables, P(n=η) is the Gaussian probability density function f(η) of Equation 13: Substituting Equation 12 into Equation 13, yields Equation 14: Similarly, noting that (s Substituting Equations 14 and 15 into Equation 11 yields the following Equation 16: Eliminating terms independent of {circumflex over (m)} and taking the logarithm, the maximum likelihood criterion of Equation 8 becomes Since is independent of {circumflex over (m)}, it may be subtracted from the maximization on the right hand side without changing the result and thereby presents the optimal solution for the preferred embodiment as shown in the following Equation 18: Given the above presentation by the present inventor, an optimal solution embodiment for synchronization word detection is now presented to implement Equation 18 in accordance with the present inventive scope. Before proceeding with, and by way of introduction to, an example of such an embodiment, note some observations regarding the operation of Equation 18. First, note the contrast of Equation 18 to that of Massey as shown by Equation 3. For example an embodiment implementing Equation 18, through its definition of the vector S, takes into account the {circumflex over (m)} known preamble prefix bits preceding the synchronization word. On the other hand, Massey ignores the preamble prefix bits. As another example, an embodiment implementing Equation 18, performs a correlation with L+{circumflex over (m)} received values from the TDMA bitstream. In contrast, Masseys' criterion takes into account only the L bits of the synchronization word and further implements a sliding window across the incoming TDMA bitstream. Second, note a common aspect of Equations 18 and 3 in that both techniques implement the non-linear hyperbolic cosine element, and for each this may be looked upon as a normalization factor that accounts for random data and noise surrounding the synchronization word. FIG. 10 illustrates a system Looking to system Looking to register Lastly with respect to system FIG. 11 provides an illustration of the successive operations for successive steps of incrementing {circumflex over (m)} to implement Equation 18 using system Looking to the third row (from the top) of FIG. 11, it first illustrates the fixed L+M bits in storage register According to the first summation of Equation 18.1, each of the L bits in storage registers Since Equation 18 repeats to determine a maximum over L+M results, then the remaining illustrations of FIG. 11 (i.e., rows 4 through 9) depict each of those instances. For purposes of the present example, again M is assumed to be six, thereby giving rise to the total of seven different scenarios illustrated in FIG. Given the above, one skilled in the art will appreciate that system From the above, it may be appreciated that the above embodiments provide for improved apparatus and methodology for synchronization word detection in binary communication systems, such as TDMA systems by way of example. The various embodiments described above further demonstrate the flexibility of the present inventive teachings and, from this, one skilled in the art should be able to appreciate alternative configurations which may implement various of the principles discussed. For example, while the approaches described above perform bitwise comparison using the technique of a +1/−1 bit representation in combination with multiplication and summing, alternative techniques could be used where each pair of bits are compared to one another to determine if the bits match one another. In this regard, various logic operations (e.g., summing the true results of a bitwise logical AND) could be used as are known in the art. As another example of the inventive flexibility, while system Patent Citations
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