Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS6337218 B1
Publication typeGrant
Application numberUS 09/321,921
Publication dateJan 8, 2002
Filing dateMay 28, 1999
Priority dateMay 28, 1999
Fee statusLapsed
Publication number09321921, 321921, US 6337218 B1, US 6337218B1, US-B1-6337218, US6337218 B1, US6337218B1
InventorsCyprian E. Uzoh, Stephen A. Cohen, Arnold Halperin
Original AssigneeInternational Business Machines Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method to test devices on high performance ULSI wafers
US 6337218 B1
Abstract
An apparatus for testing structures in semiconductor wafers. The apparatus includes at least one test probe. At least one tool measures and controls deceleration of the at least one test probe as it approaches a surface of a structure in the semiconductor wafer.
Images(7)
Previous page
Next page
Claims(12)
We claim:
1. An apparatus for testing structures in semiconductor wafers, comprising:
at least one test probe;
means coupled to said at least one test probe for measuring impedance of said structures; and
at least one tool for measuring and controlling deceleration of the at least one test probe as it approaches a surface of a structure in the semiconductor wafer.
2. The apparatus according to claim 1, wherein the structure being tested is metallic.
3. The apparatus according to claim 1, wherein the at least one tool includes at least one member selected from the group consisting of infrared optics and a capacitance gauge.
4. The apparatus according to claim 1, wherein a surface of the test probe contacts the surface of the structure to be tested, and wherein the contact surface of the test probe is coated with at least one electrically conducting polymer.
5. The apparatus according to claim 1, wherein a surface of the test probe that contacts the surface of the structure to be tested is planar.
6. The apparatus according to claim 1, wherein the at least one test probe tests the structures in the semiconductor wafers without contacting them.
7. A method of testing structures in semiconductor wafers, the method comprising the steps of:
directing at least one test probe towards a semiconductor wafer;
detecting deceleration of the at least one test probe with at least one tool for measuring and controlling deceleration of the at least one test probe as it approaches a surface of a structure in the semiconductor wafer; and
measuring the impedance, at least one frequency, of at least one structure in said semiconductor wafer.
8. The method according to claim 7, wherein the structure being tested is metallic.
9. The method according to claim 7, wherein the at least one tool includes at least one member selected from the group consisting of infrared optics and a capacitance gauge.
10. The method according to claim 7, wherein a surface of the test probe contacts the surface of the structure to be tested, and wherein the contact surface of the test probe is coated with at least one electrically conducting polymer.
11. The method according to claim 7, wherein a surface of the test probe that contacts the surface of the structure to be tested is planar.
12. The method according to claim 7, wherein the at least one test probe tests the structures in the semiconductor wafers without contacting them.
Description
FIELD OF THE INVENTION

The invention relates to a method and apparatus for testing structures in semiconductor wafers.

BACKGROUND OF THE INVENTION

Typically, during the production of semiconductor chips and other electronic devices, testing is carried out to ensure proper functioning of the chips or other devices. In some cases, only particular portions of the chips or other devices may be tested. For example, various structures formed in a semiconductor chip may be tested to ensure proper electrical functioning.

Often, during testing, a probe contacts a structure formed on a semiconductor wafer. Electrical current may then flow through the probe into the structure. As the testing device contacts the structure on the semiconductor wafers, it may actually generate defects in the structures. For example, test probes may impact with a force sufficient to indent and/or scratch test pads on the semiconductor wafers. Also, depending upon the force of the probe tip, insulator cracking may occur. These problems are particularly bad when testing uncapped copper and aluminum structures.

Damage to a test pad or other structure on a semiconductor wafer as a result of contact by a testing probe is often severe enough to cause yield losses at subsequent levels of build. Approaches for addressing damage to structures in semiconductor wafers may involve treating the defects generated by the testing process rather than preventing the defects. According to one method to address test probe related defects, post-test brush cleaning is utilized. According to another method, post-test mild kiss polishing is utilized. According to a third method, the decision is not to test at the intermediate levels, but to defer testing to the final metal level.

Each of the above-described methods for addressing test probe generated defects has associated penalties. Along these lines, deferring testing until the final metal level may result in missing defects that could have permitted the product wafer to be discarded prior to further processing. Alternatively, both cleaning and polishing may result in further damage to the structures that have been damaged during testing as well as to create defects in previously pristine surrounding structures. At a minimum, time and money must be expended to address the above-described problems. Also, the defects can result in waste through their inclusion in the products being tested.

SUMMARY OF THE INVENTION

The present invention provides methods and apparatuses for reducing test related defects. In accordance with these and other objects and advantages, the present invention provides an apparatus for testing structures in semiconductor wafers. The apparatus includes at least one test probe. The apparatus also includes at least one tool for measuring and controlling deceleration of the at least one test probe as it approaches the surface of a structure in the semiconductor wafer.

The present invention also provides a method of testing structures in semiconductor wafers. The method includes directing at least one test probe toward a structure in a semiconductor wafer to retest it. Deceleration of the at least one test probe is detected with at least one tool for measuring and controlling deceleration of the at least one test probe as it approaches a surface of a structure in the semiconductor wafer.

Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-mentioned objects and advantages of the present invention will be more clearly understood when considered in conjunction with the accompanying drawings, in which:

FIG. 1a represents a cross-sectional view of a test pad in a semiconductor wafer prior to testing;

FIG. 1b represents a cross-sectional view of the test pad illustrated in FIG. 1a after testing with a conventional test probe;

FIG. 2 represents an embodiment of an apparatus according to the present invention and a cross-sectional view of a portion of a semiconductor wafer that is to be tested by the apparatus;

FIG. 3 represents a perspective view of portions of a small section of a semiconductor wafer showing a conduction net;

FIG. 4 represents a schematic illustrating an electrical equivalent circuit of the elements shown in FIG. 3;

FIG. 5 represents a perspective view of portions of a small section of a semiconductor wafer showing a conduction net with a grounded plane that couples electrically to power planes in the semiconductor wafer;

FIG. 6 represents a schematic illustrating an electrical equivalent circuit of the elements of the semiconductor wafer with the grounded plane shown in FIG. 3;

FIG. 7 represents a perspective view of portions of a small section of a semiconductor wafer showing a second conducting line, an impedence meter and a grounded plane, as well as schematic elements representing an electrical equivalent circuit; and

FIG. 8A and FIG. 8B represent schematics of reduced electrical equivalent circuits of a circuit under test in FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides an apparatus and method for testing structures in semiconductor wafers. The present invention is particularly useful for electrically testing structures made of soft conductors, such as copper, gold, and/or aluminum. However, the present invention may be utilized with any type of structure.

Generally speaking, the present invention may utilize at least one position sensor to detect the location of a probe approaching the surface of the structure to be tested. The present invention may then adjust the deceleration based upon the data detected by the at least one sensor. Additionally or alternatively, the present invention may utilize test probes having planar surfaces that contact the structure to be tested. Whether or not the test probes include a planar surface, the surface of the test probe that contacts the structure to be tested may be coated with a conductive polymer to further avoid damaging soft metal pads or other structures to be tested.

By incorporating the above-described elements into an apparatus, the present invention helps to avoid damage to structures, such as probe pads, during electrical tests. The present invention may also lengthen probe life. Often material is generated when other types of probes push up the surface of the contact, producing loose particles that can move around and cause defects.

By reducing defect generation, the present invention may also extend equipment life and eliminate the need for post-test cleaning, such as the polishing referred to above. Additionally, by preventing the above described problems associated with testing structures in semiconductor wafers, the present invention may increase yield in semiconductor device production processes. Furthermore, the present invention may also decrease cost and time associated in semiconductor manufacturing processes by eliminating the need for additional processes to correct defects generated by testing.

The present invention provides methods and apparatus for reducing test related defects while testing structures in semiconductor wafers using probes that either do not contact the wafer or contact it in such a manner as to cause no damage. It also provides methods and apparatus for making an impedance measurement of a test structure on the wafer.

The distance of the probe to the surface of the wafer may be determined and the distance information used to control the speed at which the probe is moved. This may be accomplished by using an optical sensing method for longer distances and the impedance signal itself for shorter distances. Typically, when the probe is greater than about 1 μm from the surface of the wafer, the capacitance (Cp.) from the probe to the wafer is very small. This very small capacitance dominates the impedance measurement and is directly proportional to the distance of the probe to the surface of the wafer.

This impedance measurement, proportional to the probe distance, may be utilized to control the speed at which the probe is moved in proximity to the wafer. At large distances, the probe may be moved fast. However, at close distances, the speed may be reduced to accurately position the probe.

Two impedance measurements at two different frequencies may be made on the test structure. By employing the real and complex component values of these two measurements, the test structure resistance and capacitance may be determined. Also, the probe to wafer capacitance may be determined.

The present invention may utilize an optical measurement at longer probe distances and an impedance measurement at shorter distances to measure the probe location with respect to the wafer. Impedance measurements may be made at two frequencies to determine the real and complex values of the electrical circuit under test. The probe contacts may be planar and do not damage the pads on the semiconductor wafer.

FIG. 1a illustrates an example of a test pad 1 arranged in a substrate 3 prior to testing, where the testing includes contacting the test pad surface 2 with a test probe. As described above, contact of the probe with the test pad 1 may damage the test pad. FIG. 1b illustrates a cross-sectional view of an example of damage to a test pad 1 as a result of contact with a test probe tip. As can be seen in FIG. 1b, material 7 has been gouged out of the surface 2 of the test pad 1, leaving a depression 5 in the test pad. In this example, the material 7 gouged out of the test pad 1 remains on the surface 2 of the test pad.

To help prevent damage to the structures in the semiconductor wafer as a result of testing, the present invention includes at least one tool for measuring and controlling deceleration of at least one test probe as it approaches the surface of the structure in the semiconductor wafer.

A probing station according to the present invention may utilize optical sensing, such as an optical interferometer, to bring the probe down to within about 30 μm of the surface. At that point, with the impedance meter operating at about 1 MHz, the probe to wafer capacitance can be measured. This measurement relates to the distance (dp-p) of the probe to the wafer pad.

According to one example, a distance dp-p of about 30 μm from the probe to the pad relates to a Cp (capacitance from probe to pad) of about 3 fF (femto Farads) when the pad size is about 100 μm by about 100 μm and the probe size is comparable. Two probes give a Cp/2 of about 1.5 fF which relates to a capacitive reactance of about 100 Mω at about 1 MHz. and can be resolved by the impedance meter.

According to another example, a dp-p of about 0.1 μm, resolves to a Cp/2 of about 0.5 fF and a capacitive reactance of 350 about kω. At the distance dp-p of about 0.1 μm or less, the operating frequency can be lowered to about 10 kHz and measurements of R1 and C1 can be made. Thus, using the circuitry schematically illustrated in FIG. 8B, the reactance of Cp/2 would be about 35 Mω at a dp-p of about 0.1 μm and an operating frequency of about 10 kHz.

The probe can be driven at high speeds down to about 30 μm of the surface at which time the probe speed may be reduced and the capacitive sensor will take control of the probe position height sensing.

In addition to altering the rate at which the test probe contacts the structure to be tested, the present invention may include a test probe designed to reduce damage to the structure being tested by the test probe. Along these lines, the surface of the test probe that contacts the structure to be tested may be planar. By including a planar structure rather than a structure that includes a pointed tip or tip that includes at least two surfaces that meet at an angle that contacts the structure being tested, the present invention may help to eliminate gouging of the surface of the structure being testing and the problems associated therewith.

In addition or alternatively to including a planar contact tip, the surface of the test probe that contacts the structure being tested in the semiconductor wafer may be at least partially coated with at least one electrically insulating polymer. The at least one electrically insulating polymer may be softer than the test probe. As a result, the polymer coated test probe may help to prevent damage to the structure being tested.

To control the deceleration of the at least one test probe, the present invention may include an optical and/or a capacitance gauge. The probe can be driven at high speeds down to about 30 μm of the surface. At that point, the probe speed may be reduced and the capacitive sensor will take control of the probe position height sensing.

Regardless of whether the present invention tests the structures in the semiconductor wafer by contacting them, the present invention may include infrared optics and/or a capacitance gauge to control deceleration of the probe tip into the test pad. Because the distance between the probe and the semiconductor wafer is so small, the position of the probe is near contact. The contact may be so close that it is just in contact with the surface, but with very low pressure, in other words mere contact.

The probe may have an insulating, soft coating that will cause no damage. Also, since the contact may be planar, the force on the wafer surface may be distributed over a wider area. This is not a point contact method. The near contact and non-contact methods can utilize distances below about 0.1 μm. When an insulating layer is used on the flat side of the probe, the insulation thickness is part of the approximately 0.1 μm thickness and the probe insulation may be in contact with the wafer pad.

FIG. 2 illustrates an example of an embodiment of a device according to the present invention. FIG. 2 illustrates two structures to be tested 9 and 11 in a substrate 13, such as a semiconductor wafer.

The embodiment of the present invention illustrated in FIG. 2 includes the apparatus for testing structures in semiconductor wafers 15. The apparatus includes two test probes 17 and 19.

The apparatus 15 also includes a capacitance positioning sensor 21 for measuring the position of the apparatus 15 and the rate at which it approaches the structures to be tested 9 and 11. The capacitance positioning sensor may sense the gap between the tips of probes 17 and 19 and the top surface of the structures to be tested 9 and 11. The capacitance positioning sensor may also detect the lateral position of the apparatus 15 with respect to the semiconductor wafer that includes the structures to be tested.

The tester may include a ground plane to reduce capacitance between neighboring pads. The reason to use a grounded plane 6 in close proximity to the module is to lower the effective capacity of C1-2. Normally, the capacity of the various parts of the net to the other parts in the module such as C1-3 and then back to another part of the net such as C2-3 add to the value of C1-2. The capacity C3-6 may be much larger than the net capacities C1-3 and C2-3. This may act like a divider of the capacities and reduce the effective capacity across the net.

The apparatus may be supported on a support 22. Also, the apparatus may include a connection 25 for connecting the apparatus to a power source and/or a processor, among other things.

FIG. 3 illustrates a conductive net and an insulated power plane in a semiconductor wafer. Surface pads 10 and 12 at the end of the conducting net are exposed. Other parts of the net and wafer including the power/ground planes 23 are covered with insulation 29 to protect the devices and lines and prevent shorting. A via 14 connects the surface pad 10 to the conducting line 25.

FIG. 4 shows a schematic drawing illustrating the electrical equivalent for the simplified view shown in FIG. 3. As such, FIG. 4 illustrates a conducting path between pad 10 and pad 12 shown by resistor R1-2. There is a stray, or undesired, capacitance across these pads and resistance as shown by capacitance C1-2. C1-3 and C2-3 represent the capacitance from each pad to the power planes in the wafer.

FIG. 5 shows a simplified view of the wafer under test with probes 27 and 28 coming to close proximity to the surface pads 10 and 12. A grounded external plane 26 is shown in proximity to the wafer under test. The ground plane 26 will have a large capacitance to the power plane 23 inside the wafer.

A reason to use a grounded plane 26 in close proximity to the module is to lower the effective capacity of C1-2. Typically, the capacity of the various parts of the net to the other parts in the module, such as C1-3 and then back to another part of the net, such as C2-3, adds to the value of C1-2. The capacity C3-6 is much larger than the net capacities C1-3 and C2-3. This acts like a divider of the capacities and reduces the effective capacity across the net.

FIG. 6 shows the electrical circuit equivalent for the arrangement illustrated in FIG. 5. As such, FIG. 6 shows the probe to pad capacitance C7-1 and C8-2 and the power plane to external ground capacitance C3-6.

FIG. 7 shows an embodiment of an arrangement according to the present invention where an impedance meter 31 is connected to two probes 27 and 28. The probes are shown in proximity to the circuit pads 10 and 12, which are part of the net under test. FIG. 7 also shows another circuit line 30 and the capacities from the circuit under test to that line 30 and the power plane 23. The capacity from the power plane 23 to the externally grounded plane 26 is shown as C3-6.

FIG. 8A shows a simplified schematic electrical equivalent circuit of the arrangement illustrated in FIG. 7, where C1 includes C1-2 and all the shunt capacities, such as C1-3 and C2-3. C7-1 and C8-2 are the probe to pad capacitance. R1 is the equivalent of R1-2 from the previous figures.

FIG. 8B shows an equivalent of the simplified network illustrated in FIG. 8A where the probe to pad capacities are combined into an equivalent capacitance Cp/2. These circuit equivalents may make the mathematical equations easier to work with.

The present invention may utilize an impedance method for testing the structures in the semiconductor wafers. According to an impedance method, multiple frequencies typically should be utilized in testing the structures. Along these lines, frequencies of about 10 kHz, about 20 kHz, and about 5 kHz may be utilized.

Because the distance is so small, the position of the probe is near contact. It may be so close that it is just in contact with the surface, but with very low pressure (mere contact). The probe may have an electrically insulating soft coating that will cause no damage. Also, since the contact may be planar, the force on the wafer surface may be distributed over the wider area. The present invention typically is not thought of as a point contact method. The near contact and non-contact methods according to the present invention utilize distances below about 0.1 μm. When an insulating layer is used on a flat side of a probe, the insulation thickness may be considered to form a part of the about 0.1 μm thickness. Therefore, the probe insulation may be in contact with the wafer pad.

Measurements taken during the testing have been plugged into the following equations. In considering the circuitry represented in FIG. 8B, in order to resolve the net resistance R1, the composite capacitance C1, and the probe to net capacitance Cp, three equations typically are needed because there are three unknown values to be determined. When an impedance meter having a real and complex value is used to take measurements, only two measurements typically are needed to produce the three values for the three equations. The equations may be derived from the simplified circuit shown in FIG. 8B. This circuit impedance is: Z 1 = R 1 1 + ( ω C 1 R 1 ) 2 - j 1 1 + ( ω C 1 R 1 ) 2 [ ( R 1 ) 2 ω C 1 ( 1 + 2 C 1 C P ) + 2 ω C P ]

This equation includes a real part A and a complex part B as shown below:

Z=A−jB

When a frequency is applied to the circuit through an impedance meter such as an H.P. precision LCR meter, the real part A and the complex part B values are obtained. For a frequency f1 giving an angular frequency ω1=2πf1, the real part of the impedance is: Re Z f 1 = A 1 = R 1 1 + ( ω 1 R 1 C 1 ) 2

The complex part is: Im Z f 1 = B 1 = ( R 1 ) 2 ω 1 C 1 ( 1 + 2 C 1 C P ) + 2 ω 1 C P 1 + ( R 1 ω 1 C 1 ) 2

If a frequency f2 is used, the real part of the impedance is: Re Z f 2 = A 2 = R 1 1 + ( ω 2 R 1 C 1 ) 2

Thus, three equations are obtained by using two angular frequencies, ω1 and ω2 and the three unknowns, R1, C1, and Cp, can be determined when these three equations are solved and are shown as: R 1 = A 1 A 2 [ ( ω 2 ) 2 - ( ω 1 ) 2 ] A 2 ( ω 2 ) 2 - A 1 ( ω 1 ) 2 C 1 = [ ( A 1 - A 2 ) ( A 2 ( ω 2 ) 2 - A 1 ( ω 1 ) 2 ) ] 1 / 2 A 1 A 2 [ ( ω 2 ) 2 - ( ω 1 ) 2 ] C P = 2 [ ( ω 1 R 1 C 1 ) 2 + 1 ] ω 1 B 1 + ( ω 1 R 1 ) 2 C 1 ( ω 1 B 1 C 1 - 1 ) , ( In terms of R 1 and C 1 )

The test typically should then be repeated. The test typically requires obtaining the real value acquired by the impedance test at two frequencies and the complex value of the impedance test at one frequency.

Advantages of the present invention include the ability to detect “opens” and shorts in structures in semiconductor wafers without contacting the structures to be tested. The present invention also provide maze resistance data where convoluted comb and serpentine structures are used to test wiring reliability. The present invention may eliminate probe damage to structures in semiconductor wafers as well as to structures in the wafers other than the structures being tested.

The present invention may also increase probe life by limiting contact or altering the nature of the contact between the test probe and the structures to be tested in a semiconductor wafer. Along these lines, the present invention may also minimize probe tip resurfacing as required to compensate for probe wear. The present invention may also be utilized for chip level or package level platform testing. The present invention may also simplify the process of testing the structures in semiconductor wafers.

The foregoing description of the invention illustrates and describes the present invention. Additionally, the disclosure shows and describes only the preferred embodiments of the invention, but as aforementioned, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings, and/or the skill or knowledge of the relevant art. The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4158171Sep 14, 1977Jun 12, 1979Ade CorporationWafer edge detection system
US4467281Feb 29, 1980Aug 21, 1984Electric Power Research Institute, Inc.Multi frequency eddy current test apparatus with intermediate frequency processing
US4766368Sep 30, 1986Aug 23, 1988Cox Harold ACapacitive sensor
US4958129Mar 7, 1989Sep 18, 1990Ade CorporationPrealigner probe
US5182513Apr 6, 1991Jan 26, 1993General Electric CompanyMethod and apparatus for a multi-channel multi-frequency data acquisition system for nondestructive eddy current inspection testing
US5189377 *Sep 4, 1990Feb 23, 1993Extrude Hone CorporationMethod and apparatus for co-ordinate measuring using a capacitance probe
US5237271May 6, 1991Aug 17, 1993General Electric CompanyApparatus and method for non-destructive testing using multi-frequency eddy currents
US5321352Jul 31, 1992Jun 14, 1994Tokyo Electron Yamanashi LimitedProbe apparatus and method of alignment for the same
US5489888Aug 10, 1994Feb 6, 1996Precitec GmbhSensor system for contactless distance measuring
US5615006 *Jun 6, 1995Mar 25, 1997Nikon CorporationImaging characteristic and asymetric abrerration measurement of projection optical system
US5719495 *Jun 5, 1996Feb 17, 1998Texas Instruments IncorporatedApparatus for semiconductor device fabrication diagnosis and prognosis
US5883437 *Dec 28, 1995Mar 16, 1999Hitachi, Ltd.Method and apparatus for inspection and correction of wiring of electronic circuit and for manufacture thereof
US6210981 *Feb 12, 1999Apr 3, 2001Advanced Micro Devices, Inc.Method for etching a flip chip using secondary particle emissions to detect the etch end-point
US6239481 *Jun 5, 1998May 29, 2001Advanced Micro Devices, Inc.Device for removing a flip chip die from packaging
US6255599 *Aug 18, 1997Jul 3, 2001IbmRelocating the neutral plane in a PBGA substrate to eliminate chip crack and interfacial delamination
US6265782 *Oct 8, 1997Jul 24, 2001Hitachi Chemical Co., Ltd.Semiconductor device, semiconductor chip mounting substrate, methods of manufacturing the device and substrate, adhesive, and adhesive double coated film
JPS6473632A Title not available
JPS61171145A Title not available
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6610550 *Apr 3, 2002Aug 26, 2003Advanced Micro DevicesMethod and apparatus for correlating error model with defect data
US6856849 *Dec 6, 2000Feb 15, 2005Advanced Micro Devices, Inc.Method for adjusting rapid thermal processing (RTP) recipe setpoints based on wafer electrical test (WET) parameters
US8766658 *Apr 1, 2009Jul 1, 2014Tokyo Electron LimitedProbe
US20020095278 *Dec 6, 2000Jul 18, 2002Riley Terrence J.Method for adjusting rapid thermal processing (RTP) recipe setpoints based on wafer electrical test (WET) parameters
US20090289646 *Nov 26, 2009Ipworks Technology Corp.Test probe
US20110115514 *Apr 1, 2009May 19, 2011Tokyo Electron LimitedProbe
Classifications
U.S. Classification438/14, 257/780
International ClassificationG01R31/311, G01R31/312, G01R31/28, G01R1/067
Cooperative ClassificationG01R31/2831, G01R31/311, G01R1/06705, G01R31/312
European ClassificationG01R1/067B
Legal Events
DateCodeEventDescription
May 28, 1999ASAssignment
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:UZOH, CYPRIAN E.;COHEN, STEPHEN A.;HALPERIN, ARNOLD;REEL/FRAME:010006/0586;SIGNING DATES FROM 19990524 TO 19990526
Jul 7, 2005FPAYFee payment
Year of fee payment: 4
Jul 20, 2009REMIMaintenance fee reminder mailed
Jan 8, 2010LAPSLapse for failure to pay maintenance fees
Mar 2, 2010FPExpired due to failure to pay maintenance fee
Effective date: 20100108