|Publication number||US6342718 B1|
|Application number||US 09/694,258|
|Publication date||Jan 29, 2002|
|Filing date||Oct 24, 2000|
|Priority date||Nov 18, 1998|
|Also published as||US6316305|
|Publication number||09694258, 694258, US 6342718 B1, US 6342718B1, US-B1-6342718, US6342718 B1, US6342718B1|
|Inventors||Wendell P. Noble|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Non-Patent Citations (6), Referenced by (13), Classifications (13), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of copending application Ser. No. 09/195,163, filed Nov. 18, 1998 and as such claims priority to the copending application.
1. Field of the Invention
The present invention relates generally to the field of integrated circuit fabrication, and more specifically to a structure for static random access memory cells with tunnel diodes and a method for making the same.
2. Description of the Related Art
The traditional SRAM cell consists of six transistors configured as cross-coupled inverters to form a flip-flop. The minimum attainable cell size has remained at approximately 120 F2 (where F denotes the feature size—the minimum line width and/or minimum space between lines) using standard planar technology. The drive to achieve further reductions in cell size has led to the use of vertical transistors, but even with this technology, which is more complicated and hence more costly, the feature size cannot be reduced to below 32 F2. Thus, although absolute SRAM cell size can be improved with reductions in feature size corresponding to advances in lithography technology, further reductions in SRAM cell size require changes in cell configuration. As used herein, cell configuration refers to the components (e.g. transistors, diodes) of the cell and their interconnection. Configuration has a different meaning from structure. Structure, as used herein, refers to the physical topography of the fabricated cell.
Several different SRAM cell configurations have been proposed. Some of these new structures exploit latchup as a mechanism of cell operation. Other new SRAM cell configurations make use of bipolar base current reversal. Examples of such configurations can be found in Koji Sakui et al., A New Static Memory Cell Based on Reverse Base Current (RBC) Effect of Bipolar Transistors, 1988 IEDM Digest of Technical Papers, pp. 44-47, and in U.S. Pat. No. 5,594,683. These and other new SRAM cell configurations do achieve smaller cell size.
Each of these alternative configurations, however, suffers from an important drawback—high standby power consumption. Standby power consumption is the amount of power used by a cell when neither read nor write accesses are occurring. This drawback is especially problematic in situations such as BBRAM (battery backed-up RAM) where low standby power consumption is crucial.
Another alternative configuration is disclosed in van der Wagt et al., RTD/HFET Low Standby Power SRAM Gain Cell, IEEE Electron Device Letters, vol. 19, No. 1 (January, 1988). This configuration uses only two tunnel diodes and a single FET, but still suffers from relatively high standby power consumption (approximately 50 nanowatts per cell). The high standby power consumption is partially due to the fact that the cell described in van der Wagt is fabricated using III-V technology (integrated circuits fabricated on substrates such as GaAs comprising combinations of elements from groups III and V of the periodic table).
A circuit diagram of this SRAM cell 10 is shown in FIG. 1. Two tunnel diodes 14, 16 are connected in series between a voltage source 12 and ground such that the diodes 14, 16 are both forward biased. The storage node 15 between the diodes 14, 16 is connected to the drain 18 a of a field effect transistor 18. The source 18 b of transistor 18 is connected to the bit line 20, while the gate 18 c of transistor 18 is connected to the word line 22. In this configuration, the transistor 18 allows access to the storage node 15 much as a transistor controls access to a storage capacitor in a conventional DRAM cell.
FIG. 2 is a plot of the current vs. voltage characteristic curve 40 of the tunnel diodes 14, 16. The vertical axis 42 is in milliamps, while the horizontal axis 44 is in volts. The curve 40 exhibits a relative minimum, or valley, current at approximately 0.3 volts (point A in FIG. 2). As can be seen from line 46, this same current also occurs at a forward bias of approximately 0.02 volts (point B in FIG. 2). Thus, a combination of two diodes 14, 16 forward biased in series with a total bias of 0.32 volts will have a current equal to the valley current indicated by line 46, with 0.3 volts across one diode and 0.02 volts across the other. Since either diode can have either voltage, two stable states for the diode 14, 16 combination exist. The node 15 thus acts as the storage node, which can remain stable at either 0.3 or 0.02 volts. The stability of the cell states is determined by the value of the voltage across the diode pair 14, 16 as illustrated in FIG. 3. The node 15 can be set to either of these states by applying the desired voltage to the bit line 20 and raising the word line 22 voltage to turn on the access transistor 18. Reading may be accomplished as in a DRAM cell by using voltage sense amplifier to sense the voltage on the bit line 20 after raising the word line 22 voltage to connect the node 15 to the bit line 20. Because the node 15 is in a self-sustaining stable voltage state, current sensing may also be used to read the cell state.
What is needed is a compact cell structure and corresponding fabrication method that realizes the above-discussed SRAM circuit configuration in a small amount of space while improving standby mode power consumption.
The present invention provides a compact structure for the above-discussed SRAM cell as well as a method for fabricating the structure. The structure is implemented in silicon (rather than III-V) technology which results in a reduced standby power consumption of only approximately 0.5 nanowatts. The cell structure realizes an SRAM cell with only a 16 F2 area using planar technology. The structure of the cell according to one embodiment of the present invention is comprised of first and second voltage bus bars of approximately minimum feature size width, each of which has a tunnel diode formed therein, and an elongated center land area (also of minimum feature size width) between the two bus bars. The transistor is constructed along the elongated center land area. In a preferred embodiment, transistors of neighboring cells share a common drain area and bit line contact. A corresponding method for fabricating the structure is also disclosed.
The foregoing and other advantages and features of the invention will become more apparent from the detailed description of the preferred embodiments of the invention given below with reference to the accompanying drawings in which:
FIG. 1 is circuit diagram of an SRAM cell;
FIG. 2 is a characteristic curve of a silicon tunnel diode used in the circuit of FIG. 1;
FIG. 3 is a load line diagram of the diodes included in the circuit of FIG. 1;
FIG. 4 is a perspective view of a silicon wafer with a structure corresponding to a pair of SRAM cells according to one embodiment of the present invention thereon;
FIG. 5 is a mask used in the fabrication of the structure of FIG. 4;
FIG. 6 is a top view of the wafer of FIG. 4 at an early stage of processing according to one embodiment of the present invention;
FIG. 7 is a cross-sectional view taken along the line VII—VII from FIG. 4 of the wafer of FIG. 6 at a later stage of processing;
FIG. 8 is a cross-sectional view of the wafer of FIG. 7 at a later stage of processing;
FIG. 9 is a cross-sectional view of the wafer of FIG. 8 at a later stage of processing;
FIG. 10 is a cross-sectional view of the wafer of FIG. 9 taken along the line X—X;
FIG. 11 is a cross-sectional view of the wafer of FIG. 10 at a later stage of processing;
FIG. 12 is a cross-sectional view of the wafer of FIG. 11 at a later stage of processing;
FIG. 13 is a perspective view of the wafer of FIG. 12 at a later stage of processing; and
FIG. 14 is a diagram of a computer system incorporating memory cells according to the present invention.
The present invention will be illustrated through a description of a two-cell SRAM structure and corresponding method for fabricating said structure. Numerous specific details, such as materials, thicknesses, etc., are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention is capable of many different embodiments and that the present invention may be practiced without the specific details set forth herein. Accordingly, the drawings and description herein are to be regarded as illustrative in nature and not as restrictive.
The term “wafer” is to be understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, or gallium arsenide.
A perspective view of a two-cell SRAM structure 100 according to one embodiment of the present invention is illustrated in FIG. 4. The structure 100 is formed on a wafer 102. The wafer 102 is preferably comprised of p-type silicon. The structure 100 comprises a first voltage bus 104 (which is at approximately +0.32 volts in the preferred embodiment) and a second voltage bus 106, which is at ground in the preferred embodiment. The width of each bus 102, 104 is either approximately or exactly the minimum feature size. The structure 100 also comprises a device land 108 located between the buses 104, 106, which also has a width approximately equal to the minimum feature size. The buses 104, 106 and device lands 108 are formed from wafer 102 using an STI (shallow trench isolation) process. In contrast to the buses 104, 106, which arc continuous between many cells, the device land 108 extends only the length of the two cells illustrated in FIG. 4. The space between the first voltage bus 104 and the device land 108, as well as the space between the device land 108 and the second voltage bus 106 is also approximately equal to the minimum feature size. Although not shown in FIG. 4, these spaces are filled in with oxide insulators to isolate the buses 104, 106 and device land 108.
The first voltage bus 104 is comprised of p-type silicon, which is separated from the p-type silicon wafer by a thin n-type layer 110 beneath the first voltage bus 104 to isolated it from the p-type silicon wafer substrate 102. The second voltage bus 106 is formed of n-type material. The device land 108 is formed of the same p-type material as the wafer 102. Source regions 112 and drain regions 114 are formed in device land 108. The drain region 114 is common to both cells illustrated in FIG. 4. An n-type region 116 is formed in the p-type material of first voltage bus 104 to form a first p-n junction tunnel diode. A p-type region 118 is formed in the n-type second voltage bus 106 to form a second p-n junction tunnel 10 diode. The first tunnel diode corresponds to diode 14 from FIG. 1, while the second tunnel diode corresponds to diode 16 of FIG. 1. The n-type region 116 of the first tunnel diode is connected to the p-type region 118 of the second tunnel diode (such that both diodes are forward-biased) by a metal node strap 120 (corresponding electrically to node 15 of FIG. 1), which is also connected to the source region 112. A word line 126 includes a gate region 128 between the source region 112 and drain region 114 such that a field effect transistor (corresponding to transistor 18 in FIG. 1) is formed. Not shown in FIG. 4 for the sake of clarity, but shown in FIG. 12, are nitride insulators 160 along the sides of the word line 126 that electrically isolate the word line 126 from neighboring node straps 120. Also shown in FIG. 4 are portions of node straps 122, p-type regions 124 and n-type regions 126 from neighboring SRAM cells. Finally, shown schematically in FIG. 4 is a bit line 130 and a bit line contact 132. The structure on the right side of the bit line contact 132 forms a first SRAM cell 136 while the structure on the left side of the bit line contact 132 forms a second SRAM cell 134.
FIG. 5 illustrates a portion 200 of a mask used to form the buses 104, 106 and device lands 108 in the wafer 102 of FIG. 4. Mask regions 208 correspond to device lands 108 from FIG. 4. Mask regions 204 correspond to the first voltage bus 104 of FIG. 4. Mask region 206 corresponds to the second voltage bus 106 of FIG. 4. As will be explained in further detail below, the spaces between mask regions 204, 206 and 208 are etched away from the substrate 102 and filled in with oxide insulators using a standard STI process as mentioned above. Mask regions 204, 208 and 208, as well as vertical spaces 240 and horizontal spaces 242 between them are all 1F in width.
FIG. 6 illustrates a top view (in reduced detail) of the wafer 102 of FIG. 4. The portion of the wafer 102 illustrated in FIG. 6 is larger than the portion illustrated in FIG. 4. Several SRAM cell pair structures 100 a, 100 b, 100 c are contained on the wafer 102 portion of FIG. 6. The wafer 102 portion includes several device lands 108 as well as two first voltage bus bars 104 and a second voltage bus bar 106. Referring now to the SRAM cell pair designated 100 a, two node straps 120, two word lines 128, and several node strap portions 122 are shown. It is evident from FIG. 6 that first voltage buses 104 and second voltage buses 106 are shared by neighboring pairs of SRAM cells, such that horizontally neighboring cell pairs have “mirror image” structures (e.g. cell pair 100 a has its second voltage bus 106 to the left, while that same second voltage bus 106 is on the right for cell pair 100 c).
The SRAM cell size can also be determined from FIG. 6. As shown for the top cell of cell pair 100 a, the cell size is 4F×4F=16 F2. The horizontal dimension includes the width of one half of bus bar 106 (only one half of the width is counted for a particular cell because the bus bar 106 is shared with horizontal neighbors as well as the other cell in the cell pair sharing the same device land 108), a spacer region 140, device land 108, another spacer region 140, and one half of bus bar 104. Since the bus bars 104, 106, the spacer regions 140 and the device land 108 are all 1F (or approximately 1F) wide, the total approximate horizontal width is ½F+1F+1F+½F=4F. The vertical dimension of the cell includes the width of the node strap 120, the word line 126, the node strap portion 122 from a neighboring cell, ½ of the isolation region 142 between the device lands 108, and ½ of the 1F center of the device land 108 corresponding to location of the bit line contact 132 (not shown in FIG. 5). Thus, the approximate total vertical width of the cell is also ½F+1F+1F+1F+½F=4F. It can also be seen from FIG. 6 that the length of each device land 108 is approximately 7F. This includes the width of 2 word lines, 4 node straps (2 for the each cell of the pair and 2 for neighboring cells) and a center region of approximately one feature width to allow for the bit line contact 132.
A method for producing the structure 100 shall now be described. FIG. 7 illustrates a cross sectional view taken along the line VII—VII of the silicon wafer 102 of FIG. 4 at an early stage of processing. Buses 104, 106 and device land 108 are formed using an STI (shallow trench isolation process). Specifically, a pad layer 150 (comprising a thin oxide plus a thick nitride) is deposited on the wafer 102. A photomask 200 in the pattern of FIG. 5 is then placed over the pad layer 150. Next, the portions of the wafer and pad layer 150 not covered by the mask 200 are etched to a depth of approximately 0.7 microns to form isolation trenches 140. The resist is then removed. Next the isolation trenches 140 are filled by an oxide using a chemical vapor deposition (CVD) process and the wafer is chemical-mechanical planarized, resulting in the structure shown in FIG. 7. The pad layer 150 is then removed to expose the buses 104, 106 and the device lands 108.
Next, a mask is applied such that only the first voltage bus 104 is exposed. A deep (approx. 0.6 micron) n+ implant (e.g. As or Phos.) is then performed to form region 110 to isolate the first voltage bus 104 from the substrate 102. A heavy Boron implantation of the first voltage bus 104 is then performed to dope the first voltage bus 104. The mask is then stripped and a new mask is applied to expose only the second voltage bus 106, which is then doped within an n+ type implant (e.g. As or Phos.). The mask is then stripped, resulting in the structure shown in FIG. 8.
A thick thermal oxide 151 (approx. 0.1 micron) is then grown or deposited on all exposed silicon. A mask is then applied to expose only the device lands 108. The thermal oxide 151 is then removed from the device lands 108. Then a gate oxide layer 152 is grown or deposited over all exposed silicon areas. A gate conductor layer 154 and nitride cap layer 156 are then deposited as shown in FIG. 9.
FIG. 10 is a cross-sectional view, at a larger scale, taken along the line X—X of FIG. 9, of the wafer 102 at the stage of processing shown in FIG. 9. The structure shown in FIG. 10 is then masked to define the gate conductors. The exposed portions of the nitride cap and gate conductor layers 156, 154 are then etched, resulting in the gate stacks 158 shown in FIG. 11. A layer of nitride is then deposited and directionally etched to leave nitride spacers 160 on the vertical walls of the gate stacks 158. The source/drain 112, 114 regions are then formed using any conventional technique such as ion implantation. The resulting structure is shown in FIG. 12. Then a thermal oxide layer is deposited (or grown) over the source/drain regions 112, 114.
It should be noted here for clarity that the structures shown in FIGS. 10-12 are located along the device land 108. Therefore the transistors formed by the gate stacks 158 and source/drain regions 112, 114 are oriented perpendicularly with respect to the node straps 120 and word lines 126.
After the thermal oxide layer is grown as discussed above, contact holes 112 a, 116 a and 118 a are etched through the thermal oxide layer as shown in FIG. 13. Contact holes 112 a correspond to the locations at which the node straps 120 (not shown in FIG. 13) will eventually contact the source region 112 of the field effect transistors formed on device land 108. Contact holes 116 a similarly correspond to the locations at which node straps 120 will eventually contact the n-type region 116 of the first tunnel diode 14 and contact holes 118 a correspond to the locations at which node straps 120 will eventually contact the p-type regions 118 of the second tunnel diode 16.
After the contact holes are formed, the structure 100 is then masked such that only the contact holes 116 a are uncovered and the exposed silicon is doped to form the n-type regions 116 a of the first tunnel diodes 14. The mask is then removed. This process is repeated to form the p-type regions 118 a of the second tunnel diodes 16. Then the wafer 102 is annealed to activate the dopants and form the diodes 14, 16. Then a conductive layer (comprising metal in the preferred embodiment) is deposited and etched to form the node straps 120. As in a conventional process, the mask is removed and an interlevel dielectric is deposited. Holes for the bit line contact 132 are then formed and another conductive layer (also comprising metal in the preferred embodiment) is added to form the bit line. The remainder of the processing (e.g. metallic interconnection, passivation, encapsulation, etc.) is conventional and dependent upon the specific application; therefore, the details of further processing will not be discussed further.
FIG. 14 illustrates a computer system 300 incorporating an SRAM memory cell according to the present invention. The computer system 300 comprises a processor 310, a memory 320 and an I/O device 330. The memory 320 comprises an array 322 of SRAM memory cells 324. The processor 310 may also include on-chip SRAM memory cell circuits fabricated according to the present invention.
While the invention has been described in detail in connection with the preferred embodiments known at the time, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.
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|U.S. Classification||257/369, 257/368, 257/25, 257/E21.661, 257/E27.098, 257/903, 257/350, 257/105|
|International Classification||H01L21/8244, H01L27/11|
|Cooperative Classification||Y10S257/903, H01L27/11|
|Jul 7, 2005||FPAY||Fee payment|
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|Jul 1, 2009||FPAY||Fee payment|
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|Sep 6, 2013||REMI||Maintenance fee reminder mailed|
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|Mar 18, 2014||FP||Expired due to failure to pay maintenance fee|
Effective date: 20140129