Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS6363015 B1
Publication typeGrant
Application numberUS 09/589,723
Publication dateMar 26, 2002
Filing dateJun 8, 2000
Priority dateJun 21, 1999
Fee statusPaid
Also published asDE69905699D1, DE69905699T2, EP1063654A1, EP1063654B1
Publication number09589723, 589723, US 6363015 B1, US 6363015B1, US-B1-6363015, US6363015 B1, US6363015B1
InventorsAntonio Barcella, Paolo Rolandi
Original AssigneeStmicroelectronics S.R.L.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Reading method for non-volatile memories with sensing ratio variable with the reading voltage, and device to realize said method
US 6363015 B1
Abstract
A reading method for non-volatile memory cells is which includes a first step in which a memory cell of the matrix is selected by the row decoder and by the column multiplexer, a second step of preload and equalization during which the voltage on the drain electrode of the selected memory cell reaches a defined value and a third step during which the selected cell is read with a sensing ratio depending on the reading voltage of said cell. Moreover a device for the reading of the cells is described, which comprises a modulation branch with at least one modulation transistor and a load generator associated with said modulation transistor in such a way to modulate analogous the transconductance of one of the two load transistors as a function of the reading voltage of the memory cell.
Images(9)
Previous page
Next page
Claims(9)
What is claimed is:
1. Method for reading non-volatile memory cells comprising a first step in which a memory cell of a matrix is selected by a row decoder and by a column multiplexer, a second step of preload and equalization during which a voltage on a drain electrode of the selected memory cell reaches a predefined value, and a third step during which the selected cell is read with a sensing ratio depending on a gate biasing voltage of said cell.
2. Method according the claim 1 wherein during said third step the sensing ratio is modulated by a load biasing generator that works in function of the reading voltage of the selected cell.
3. Sense amplifier for non-volatile memory cells, comprising at least one reference branch with at least one load transistor and a reading branch for reading a programmed memory cell and including at least one load transistor, including at least one modulation branch with at least one modulation transistor and a load biasing voltage generator associated with said modulation transistor in such a way to modulate analogously a transconductance of one of the two load transistors as a function of a gate biasing voltage of the memory cell.
4. Sense amplifier according a claim 3 wherein said load biasing voltage generator comprises two supply voltage transistors, linked to an unique control line of the modulation transistor, and in their turn controlled by a reading voltage of the memory cell so as to be turned on at different values by the gate biasing voltage of the memory cell.
5. Sense amplifier according to claim 3, comprising at least one parallel load, including transistors added to said one of two load transistors to change a dependence of the transconductance modulation on a reading voltage of the memory cell.
6. Sense amplifier for non-volatile memory cells, comprising at least one reference branch with at least one load transistor and a reading branch for reading a programmed memory cell and including at least one load transistor, including at least one modulation branch with at least one modulation transistor and a load biasing voltage generator associated with said modulation transistor in such a way to modulate analogously a transconductance of one of the two load transistors as a function of a reading voltage of the memory cell;
wherein said load biasing voltage generator comprises two supply voltage transistors, linked to an unique control line of the modulation transistor, and in their turn controlled by the reading voltage of the memory cell so as to be turned on at different values by a gate biasing voltage of the memory cell; and
wherein the supply transistors are biased by two voltage dividers respectively.
7. Sense amplifier according the claim 6, wherein said voltage dividers comprise a load transistor and, respectively, a transistor in transdiode configuration and two transistors in transdiode configuration.
8. Sense amplifier according to claim 7, wherein said voltage dividers further comprise transistors, and these further transistors that can be turned off as a function of a level of a logic signal carried by their control electrode lines.
9. Sense amplifier for non-volatile memory cells, comprising at least one reference branch with at least one load transistor and a reading branch for reading a programmed memory cell and including at least one load transistor, including at least one modulation branch with at least one modulation transistor and a load biasing voltage generator associated with said modulation transistor in such a way to modulate analogously a transconductance of one of the two load transistors as a function of a gate biasing voltage of the memory cell; and
further comprising a selector driven by a suitable logic signal to modify a dependence of the transconductance modulation on a reading voltage of the memory cell.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a reading method for non-volatile memory cells with a sensing ratio depending on the reading voltage and to a device to realize said method.

2. Discussion of the Related Art

Semiconductor memories are universally organized as arrays having cells of the capacitance of a single bit. These arrays are surrounded by an address decoding logic and by circuitry for interfacing with outside signals.

As known, the largest part of the memories works in a way that the row address enables all the cells along the selected line. The contents of these cells become available along the selected column line.

Additional circuitry, including sense amplifiers, control logic and input-output tri-state buffer is usually required to realize the functionality of the memory.

In memory devices like ROM (read only memory), EPROM (erasable programmable ROM), EEPROM (electrically erasable programmable ROM), etc. the reading of said memory cells occurs through the comparison of the current of the matrix cell (Ic) with a k fraction (with 0<k<1) of the current of a reference cell (Ir), that is technologically identical to the matrix cell. In said types of devices single ended sense amplifiers are usually used to perform reading and programming operation. The value of the current in the programmed memory cell must be lower than a k fraction of the value of the current of the reference memory cell, that is Icp<k*Ir. The value of the current in a virgin memory cell must be higher than a fraction of the current of the memory reference cell, that is Icv>k*Ir.

For the programmed cells a high sensing ratio k would be preferable to make necessary a lower jump of the threshold level in function of the maximum reading voltage, so as to allow a higher maximum reading voltage. For the virgin cells a low sensing ratio would be preferable because, when the reading operation happens with values of voltage near the values of the threshold voltage of the cell, a low k facilitates this kind of operation. The k ratio is called the sensing ratio and is determined by technological considerations, as the level of the threshold voltage of the virgin cell and the possible threshold jump after a programming operation, and by device features, like the supply voltage. Such choice constitutes a compromise between two contrasting demands.

Usually, in a typical sense amplifier with fixed current unbalance, a cell of the matrix memory is selected by the row decoder and by the column multiplexer and after a first preload and equalization operation of the two branches, one of which assigned to the transport of the current of the memory cell and the other to the transport of the current in the reference cell, the voltages that develop at the positive and negative terminal of the operational amplifier depend on the currents of the said two cells and on the transconductances of the transistors acting as loads. Therefore the sensing ratio k is in function of the transconductance ratio of the two load transistors and it results to be constant.

In view of the described state of the art, object of the present invention is to realize a system for reading the memory cells with a sensing ratio depending on the reading voltage.

SUMMARY OF THE INVENTION

In accordance with the present invention, this and other objects are achieved by a reading method for non-volatile memory cells comprising a first step in which a memory cell of the matrix is selected by the row decoder and the column multiplexer, a second step of preload and equalization during which the voltage on the drain electrode of the selected memory cell reaches a predefined value, and a third step during which the selected cell with a sensing ratio depending on the reading voltage of said cell is read.

According to another embodiment of the invention, a device is provided comprising at least a reference branch with at least one load transistor and a reading branch for reading the programmed memory cell and including at least one load transistor, including at least one modulation branch with at least one selection transistor and a load generator associated with said modulation transistor to modulate in an analogous way the transconductance of one of the two load transistors as a function of the reading voltage of the memory cell.

Thanks to the present invention it is possible to realize a reading system for the memory cells which has a sensing ratio k that varies as a function of the reading voltage of the memory cell.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and the advantages of the present invention will be evident form the following detailed description of an embodiment thereof, illustrated as a non limiting example in the enclosed drawings, in which:

FIG. 1 illustrates a sense amplifier according to the prior art with load transistors in transdiode configuration;

FIG. 2 illustrates a sense amplifier according to the prior art with fixed current unbalance;

FIG. 3 shows a sense amplifier with fixed current unbalance according to the prior art with a branch for verification and programming operation of the memory cell;

FIG. 4 shows a sense amplifier according to the invention with analogously modulated transconductance;

FIG. 5 illustrates an embodiment of the transconductance modulator associated with the sense amplifier of FIG. 4;

FIG. 6 shows a different embodiment of the transconductance modulator;

FIG. 7 illustrates a possible variant of the sense amplifier of FIG. 4;

FIG. 8 shows the trend of the sensing ratio k in the sense amplifier according to the invention.

DETAILED DESCRIPTION

In FIG. 1, there is indicated with 1, a simplified schematic diagram of a sense amplifier according to the prior art, including a reference branch “REF” and a reading branch “LET”.

As shown in such a figure there is a differential amplifier 2; two p-type transistors, M1 and M2; a plurality of n-type transistors, M3, M4, M5 and M6; a reference cell P1; a memory matrix 3; a column multiplexer 4; a row decoder 5; a memory cell P2 in the matrix 3; a plurality of vertical connection lines 6, outgoing from the matrix 3 and entering in the column multiplexer 4, a plurality of horizontal connection lines 7, outgoing from the row decoder 5 and entering in the matrix 3; biasing lines 8, called “vbias”; reading lines 10, called “vread”; an equalization line 12, called “eq”; a supply line 13, called “valim”; an output line 14 of the operational amplifier 2, called “out”.

The operational amplifier 2 has the positive terminal, called “loadr”, linked at the node 15 with the drain electrode of the transistor M1, with an electrode of the transistor M5 and with an electrode of the transistor M3, while the negative terminal, called “loadm”, is linked at the node 16 with the drain electrode of the transistor M2 with the other electrode of the transistor M5 and with an electrode of the transistor M4.

The load transistor M1 has the gate electrode short circuited with the drain electrode in a way to realize the transdiode configuration, the source electrode of the transistor M1 is linked with the supply line 13 as well as the transistor M2, also in a transdiode configuration.

The equalization transistor M5 has the gate electrode 18 in common with the transistor M6 and with the line 12.

The equalization transistor M6 has an electrode 19 in common with an electrode of the transistor M3 and with the drain electrode of the transistor P1, while the other electrode 20 is linked to the output line of the column multiplexer 4.

The transistor M3 has the gate electrode linked to the line 8 and the transistor M4 has the gate electrode linked to the line 8.

The reference cell P1 has the gate electrode linked to the line 10, while the source electrode is at ground.

The load transistors M1 and M2 are both linked in a transdiode configuration and therefore the resistance that offer at the nodes 15 and 16 is equal to the opposite of their transconductances, that is 1/g1 for the transistor M1, and 1/g2 for the transistor M2.

The memory cell P2 of the matrix 3 is selected by the row decoder 5 by the activation of a line of the plurality of lines 7 and by the column multiplexer 4 by activation of a line of the plurality of lines 6. After a first equalization operation in which the line 12 is at a high voltage and the voltage on the drain electrode of the memory cell P2 reaches the desider threshold value, the sensing operation occurs, during which the line 12 is at ground and the current of the cell P2 of the matrix 3 flows in the load transistor M2. In analogous mode the load transistor M1 carries the current coming from the reference cell P1.

In FIG. 2 there is illustrated a simplified schematic diagram of a sense amplifier according to the prior art with fixed current unbalance, including a reference branch “REF” and a reading branch “LET”.

According to that illustrated in such a figure it is noted that the load transistor M1 has the gate electrode in common at the node 17 with the load gate of the transistor M2; the source electrode of the transistor M1 is linked with the supply line 13 as well as the transistor M2, that is the transistor M2 is now connected like a mirror configuration.

The operational amplifier 2 has the positive terminal, called “loadr”, linked at the node 15 with the drain electrode of the transistor M1, with an electrode of the transistor M5 and with an electrode of the transistor M3, while the negative terminal, called “loadm”, is linked at the node 16 with the drain electrode of the transistor M2, with the other electrode of the transistor M5 and with an electrode of the transistor M4.

When M2 is connected in a mirror configuration, that is said transistor becomes a current generator, the output resistance of M2 continues to be 1/g2 and it is obtained that the differential voltage at the nodes 15 and 16 depends on the currents of the cells P1 and P2 and on the transconductances of the load transistors M1 and M2. These voltages are compared with each other in the operational amplifier 2, the output 14 of which will be high if the current of the reference cell P1 divided for the transconductance of the load transistor M1 is lower than the current in the memory cell P2 divided for the transconductance of the load transistor M2, that is (Ir/g1)<(Ic/g2); it will be low if the current of the reference cell P1 divided for the transconductance of the load transistor M1 is higher than the current in the memory cell P2 divided for the transconductance of the load transistor M2, that is (Ir/g1)>(Ic/g2). Therefore the sensing ratio is equal to the transconductance ratio of the load transistors M1 and M2.

In FIG. 3 there is shown a sense amplifier structure with fixed current unbalance according to the prior art with a verify branch, called VER, of the programming state of the cell. This branch is controlled by a horizontal line 21, called “{overscore (verify)}”, and two p type-transistors MV1 and MV2.

The MV1 transistor has the source electrode linked with the supply line 13 and the gate electrode with the line 21, and it has the drain electrode in common with the source electrode of the transistor MV2. The gate electrode of the transistor MV2 is in common with the gate electrode of the transistor M2 and the drain electrode in common with the gate of the transistor M1.

With the introduction of this verification branch, after the programming operation of the memory cell P2 has been performed, it is possible to modify the sensing ratio in a discrete way, by replacing one or both transistors M1 and M2, or adding one or more transistors M1 or M2 in parallel with that already present in the circuit schematic, according to outcoming logical signals.

In FIG. 4 there is shown a schematic embodiment of a sense amplifier with analogously modulated transconductance according to the present invention.

As shown in such a figure there is a reference line 22, called “ref”; a load bias voltage generator 23; two p-type transistors MV10 and MV11, making a branch called MOD.

The generator 23, as later described in detail with reference to FIG. 5, has the function to bias through the line 22 the transistor MV10 according to the reading voltage of the memory cell P2. In this way the transconductance of one of the two load transistors M1 and M2 is analogously modulated as a function of the reading voltage on the line 10. For example, by increasing the voltage on the line 10, it is possible that the current of the cell P1 increases and the value of the total transconductance G1, given by the parallel of the transconductances of the transistors M1 and MV11 respectively, lessens. This causes the increase of the sensing ratio value k (with k=g2/G1) and having an increasing k it is possible to extend the reading voltage value by which the device works, in comparison with the case where k is fixed.

In this way it is possible that the sensing ratio k follows a trend according to the desired reading voltage of the memory cell P2, that is k=f (Vread).

In FIG. 5 is shown an embodiment of the load voltage generator 23 or load transconductance modulator of the sense amplifier of FIG. 4.

As shown in such figure there are a plurality of p-type transistors M7, M9, M11, M12; a plurality of n-type transistors M8, M10, M13, M14; a first reference line 24, called “refa”, and a second reference line 25, called “refb”, distinct from each other.

The voltage on the line 22 is produced by a voltage divider made by the transistor M8 and the two transistors M7 and M11. The transistors M7 and M11 are modulated respectively by two voltage dividers M9, M10, indicated with A, and M12, M13, M14, indicated with B, respectively. The voltage dividers A and B are constituted by a p-type load transistor, M9 in the case of A and M12 in the case of B, and by one or two n-type transistors arranged by transdiode configuration, M10 in the case of A and M13, M14 in the case of B.

When the voltage on the line 10, that is the reading voltage of the memory cell P2, is less than the threshold value (“Vtn”) of the n-type transistor M10 of the voltage divider A, and than the threshold value (“2Vtn”) of the n-type transistors M13 and M14 of the voltage divider B, the voltages on lines 24 and 25 are equal to the voltage value present on the line 10. When, on the line 10, a larger voltage is present with respect of that of the previous case, the lines 24 and 25 of the respective voltage dividers will have, respectively, a voltage equal to 2*Vtn and a voltage equal to 2*Vtn, increased by a delta factor that depends on the size of the n-type transistors M10, M13, and M14. This increase factor of the voltage present on the lines 24 and 25 increases with the voltage on the line 10 and it will increase with the increase of this voltage.

When on the line 10 a low voltage is present, the two p-type transistors M7 and M11 are off and therefore the voltage on the line 22, on account of the presence of the transistor M8, that is also in the off zone, is at ground level.

This is the condition for which the load of the sense amplifier, made by transistors M1, MV10 and MV11, has the maximum transconductance and the sensing ratio is small.

When the voltage on the line 10 increases, the first transistor which goes into conduction zone will be the transistor M7, because the condition for which said transistor goes into conduction zone is that for which the existing voltage difference between the gate and source electrodes, that is the voltage present on the line 10 less the voltage present on the line 25, is higher than the threshold voltage Vtp of the p-type transistor being examined, that is: Vgs=Vdd−Vrefb>Vtp. Besides Vrefb is equal to the threshold voltage of the n-type transistor M10 plus a delta factor, that is: Vrefb=Vtn+delta. It is inferred that the voltage Vgs that turns on the transistor M7 increases with the voltage present on the line 10, that it increases with the reading voltage of the cell P2. The voltage present on the line 22 will be the partition between the transistors M7 and M8.

Equally for the p-type transistor M11. In fact the turn-on condition of said transistor is verified when the voltage difference between the gate and source electrodes, that is the voltage present on the line 10 less the voltage present on the line 24 is higher than the threshold voltage of the p-type transistor in examination, that is Vgs=Vdd−Vrefa>Vtp. Besides Vrefa is equal to twice the threshold voltage 2Vtn of the n-type transistors M13 and M14 plus the delta factor, that is: Vrefa=2Vtn+delta. It is inferred therefore that the transistor M11 also will enter in the voltage divider with the transistor M8 at higher reading voltages of the cell, so that the voltage on the line 22 is higher and so the transconductance value G1 is smaller and therefore the sensing ratio value raises with the increase of the reading voltage of the cell P2.

For enough high voltages present on the line 10, we will have that the voltage present on the line 10 less the voltage present on the line 22 is less than the threshold value of the p-type transistor, that is the load modulated by this circuit will be off.

In FIG. 6 there is shown another embodiment of the transconductance modulator.

As shown in such figure there is a plurality of transistors M15, M16 and M17, where the first two are of p-type and the third of n-type; a first control line 26, called “enable”; a second control line 27, called “{overscore (enable)}”.

The transistors M15, M16 and M17 are added because in stand-by mode power is not dissipated and therefore there is an energy saving. This is made by lines 26 and 27, that according to the transported signal, turn off the voltage dividers; in particular, when the logic signal is high on line 27, the transistors M15 and M16 are in the off zone, while, when the logic signal is low on the line 26, the transistor M17 is turned off. With the circuit off the voltage on the line 22 becomes Vdd, that is the reading voltage of the cell P2.

In FIG. 7 there is shown a circuit scheme of a further sense amplifier of the present invention.

Such figure is an elaboration of FIG. 2 and FIG. 3, that is the branch for the verifying operation after the programming operation of the cell P2 and the modulation branch of the sense amplifier load are simultaneously present.

With this layout it is possible to pass from a sensing ratio k depending on the reading voltage to another dependence type, by replacing the modulated load with another having different technical-physical features, by means of a switch controlled by a specific logic signal, or adding to the load one or more loads in parallel (modulated or not), that is adding more branches formed by transistors of MV10 and MV11 type.

This layout type is useful in the case where those devices are used for which it is demanded, during a verify step after programming operation, a reduced reading operation of the voltage unbalance of the two branches of the sense amplifier, in order to guarantee a reliability margin to the programmed cell P2. In fact, for such a demand, it is sufficient to add a branch a formed by transistors of MV10 and MV11 type, activated by a verify logical signal after the programming operation, in parallel with the existing ones, so as to obtain during reading a loss of balance, that is a sensing ratio, depending on the reading voltage of the cell like k=f(V) and during verify operation after the programming operation a dependence on the loss-of-balance reading voltage like k′=g(V)<f(V).

In FIG. 8 there is shown a trend of the sensing ratio k.

As shown in such figure there is an abscissae axis, representative of the voltage on the reading line 10, and an ordinate axis, representative of the sensing ratio k; two functions 28 and 29.

The line 29 shows a possible trend of the sensing ratio k in function of the voltage on the line 10, when the logic level of the line 21 is high; the line 28 shows a possible trend of the sensing ratio k in function of the voltage on the line 10 when the logic level on the line 21 is low. It is noted in this last case that the sensing ratio K is reduced in comparison with the case represented by line 29.

Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4713797Nov 25, 1985Dec 15, 1987Motorola Inc.Current mirror sense amplifier for a non-volatile memory
US5040148 *Jun 23, 1989Aug 13, 1991Kabushiki Kaisha ToshibaSemiconductor memory device with address transition actuated dummy cell
US5381374 *Dec 30, 1992Jan 10, 1995Kabushiki Kaisha ToshibaMemory cell data output circuit having improved access time
US5487045Sep 16, 1994Jan 23, 1996Philips Electroics North America CorporationSense amplifier having variable sensing load for non-volatile memory
US5528543 *Sep 16, 1994Jun 18, 1996Texas Instruments IncorporatedSense amplifier circuitry
US5559737 *Nov 10, 1994Sep 24, 1996Kabushiki Kaisha ToshibaNonvolatile semiconductor memory capable of simultaneously equalizing bit lines and sense lines
US5627790 *Mar 22, 1995May 6, 1997Sgs-Thomson Microelectronics S.R.L.Reading circuit for an integrated semiconductor memory device
US5864513 *Mar 27, 1997Jan 26, 1999Sgs-Thomson Microelectronics S.R.L.System for determining the programmed/non programmed status of A memory cell
US5917753 *Apr 29, 1997Jun 29, 1999Stmicroelectronics, S.R.L.Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells
US6038173 *Apr 13, 1998Mar 14, 2000Sgs-Thomson Microelectronics S.A.Memory read circuit with dynamically controlled precharging device
US6055187 *Dec 9, 1998Apr 25, 2000Stmicroelectronics S.R.L.Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells
EP0486743A1Nov 19, 1990May 27, 1992SGS-THOMSON MICROELECTRONICS S.r.l.Improved sense circuit for storage devices such as non-volatile memories, with compensated offset current
EP0487808A1Nov 19, 1990Jun 3, 1992SGS-THOMSON MICROELECTRONICS S.r.l.Memories with unbalanced loads and with compensation
EP0805454A1Apr 30, 1996Nov 5, 1997SGS-THOMSON MICROELECTRONICS S.r.l.Sensing circuit for reading and verifying the content of a memory cell
EP0814483A1Jun 18, 1996Dec 29, 1997SGS-THOMSON MICROELECTRONICS S.r.l.Read method and circuit for nonvolatile memory cells with an equalizing structure
Non-Patent Citations
Reference
1European Search Report from European Patent Application 99830382.0, filed Jun. 21, 1999.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6462987 *Aug 15, 2001Oct 8, 2002Stmicroelectronics S.R.L.Direct-comparison reading circuit for a nonvolatile memory array
US6535429 *Dec 20, 2001Mar 18, 2003Stmicroelectronics S.R.L.Reading circuit for a memory cell
US6775186 *Jul 3, 2003Aug 10, 2004Tower Semiconductor Ltd.Low voltage sensing circuit for non-volatile memory device
US7167395 *Jul 13, 2005Jan 23, 2007Infineon Technologies Flash Gmbh & Co. KgNon-volatile semiconductor memory
US7369450May 26, 2006May 6, 2008Freescale Semiconductor, Inc.Nonvolatile memory having latching sense amplifier and method of operation
US7995397 *Aug 9, 2011Cypress Semiconductor CorporationPower supply tracking single ended sensing scheme for SONOS memories
US8189409 *May 29, 2012Austriamicrosystems AgReadout circuit for rewritable memories and readout method for same
US8259505 *May 28, 2010Sep 4, 2012Nscore Inc.Nonvolatile memory device with reduced current consumption
US8279677Oct 2, 2012Cypress Semiconductor Corp.Power supply tracking single ended sensing scheme for SONOS memories
US8699275Sep 26, 2012Apr 15, 2014Cypress Semiconductor CorporationPower supply tracking single ended sensing scheme for SONOS memories
US20070014160 *Jul 13, 2005Jan 18, 2007Infineon Technologies Flash Gmbh & Co. KgNon-volatile semiconductor memory
US20100220532 *Sep 2, 2010Austriamicrosystems AgReadout Circuit for Rewritable Memories and Readout Method for Same
US20110292735 *Dec 1, 2011Nscore Inc.Nonvolatile memory device with reduced current consumption
Classifications
U.S. Classification365/185.21, 365/207, 365/185.2, 365/189.09
International ClassificationG11C16/28, G11C16/06, G11C16/02
Cooperative ClassificationG11C16/28
European ClassificationG11C16/28
Legal Events
DateCodeEventDescription
Jun 8, 2000ASAssignment
Owner name: STMICROELECTRONICS, S.R.L., ITALY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BARCELLA, ANTONIO;ROLANDI, PAOLO;REEL/FRAME:010857/0649
Effective date: 20000522
Aug 30, 2005FPAYFee payment
Year of fee payment: 4
Sep 28, 2009FPAYFee payment
Year of fee payment: 8
Jul 3, 2013ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS, S.R.L. (FORMERLY KNOWN AS SGS-THMSON MICROELECTRONICS S.R.L.);REEL/FRAME:031796/0348
Effective date: 20120523
Aug 28, 2013FPAYFee payment
Year of fee payment: 12
May 12, 2016ASAssignment
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001
Effective date: 20160426
Jun 2, 2016ASAssignment
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001
Effective date: 20160426