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Publication numberUS6363024 B1
Publication typeGrant
Application numberUS 09/716,871
Publication dateMar 26, 2002
Filing dateNov 20, 2000
Priority dateNov 18, 1999
Fee statusPaid
Also published asDE19955601A1, DE19955601C2
Publication number09716871, 716871, US 6363024 B1, US 6363024B1, US-B1-6363024, US6363024 B1, US6363024B1
InventorsHeiko Fibranz
Original AssigneeInfineon Technologies Ag
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for carrying out auto refresh sequences on a DRAM
US 6363024 B1
Abstract
The auto refresh sequence on a DRAM that is divided into memory banks is synchronized with the clock signal acting on the DRAM. A precharge pulse is transmitted during an NOP intermission or is derived from a precharge pulse of another memory bank.
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Claims(6)
I claim:
1. A method for carrying out auto refresh sequences on a DRAM having a plurality of memory banks, which comprises:
applying a clock signal to a DRAM divided into memory banks;
during an auto refresh sequence acting on a memory address, supplying an activation pulse for reading and rewriting and a precharge pulse indicating an original state from a command decoder;
synchronizing the auto refresh sequence with the clock signal, selecting at least one memory bank with a select signal, and feeding the activation pulse and the precharge pulse to the at least one memory bank selected by the select signal; and
forbidding further commands only for the at least one memory bank selected by the auto refresh sequence, and transmitting the precharge pulse during an operating intermission or deriving the precharge pulse from a precharge pulse of another memory bank.
2. The method according to claim 1, which comprises, in case of two memory banks, providing two auto refresh commands and respectively increasing a counter reading and leaving the counter reading unchanged with the two refresh commands.
3. The method according to claim 1, which comprises blocking the memory banks only during a clock cycle assigned to an auto refresh command for initiation of an auto refresh sequence.
4. The method according to claim 1, which comprises defining a given number of clock cycles for an auto refresh sequence.
5. The method according to claim 4, wherein the given number of clock cycles is six clock cycles.
6. An auto refresh method for a DRAM having a plurality of memory banks, which comprises:
applying a clock signal to a DRAM divided into memory banks;
synchronizing an auto refresh sequence with the clock signal;
selecting at least one of the memory banks with a select signal, and feeding, from a command decoder, an activation pulse for reading and rewriting and a precharge pulse indicating an original state to the at least one memory bank selected by the select signal; and
forbidding further commands only for the at least one memory bank selected by the select signal, and transmitting the precharge pulse during an operating intermission or deriving the precharge pulse from a precharge pulse of another memory bank.
Description
BACKGROUND OF THE INVENTION FIELD OF THE INVENTION

The present invention relates to a method for carrying out auto refresh sequences on a DRAM that is divided into memory banks. An activation pulse for reading and rewriting and a precharge pulse indicating the original state are supplied from a command decoder during an auto refresh sequence acting on a memory address, and a clock signal is applied to the DRAM.

In order to avoid a loss of data, it is known that the memory cells of DRAMs (dynamic random access memories) have to be regularly read and then have their contents rewritten, which is referred to as a “refresh” of the memory cells. In order to facilitate the use of DRAMs in practice, they have, therefore, a logic configuration for an auto refresh command: the latter initiates an operation in which a memory address is independently sought in the DRAM and the memory content of the memory cell associated with the memory address is read out; during this operation, the memory content is then written back to the memory cell and the memory cell is returned to its state prior to the auto refresh command. That state is referred to as the so-called “precharge state” or original state.

In order to process the above operation, in an auto refresh sequence after an auto refresh command, first of all an activation pulse is generated, in the case of which the memory cell assigned to the memory address sought is read and rewritten. After a period of time, the activation pulse is followed by a precharge pulse indicating the re-establishment of the original state of the memory cell.

Memory addresses which have been acted on by such an auto refresh sequence are generated in a counter. The counter is incremented by one at the end of each auto refresh sequence, so that all the memory cells of the memory are successively subjected to a refresh.

In the more recent synchronous DRAMs (SDRAMs), the individual commands are transmitted synchronously with a clock signal, although the auto refresh command proceeds without reference to the clock signal and it is based only on internal time delays.

FIG. 3 is a schematic illustration of the signal profile during such an auto refresh sequence ARS. The signals include a clock signal (CLK) a, an auto refresh command b, an activation pulse c, a precharge pulse d, and a counter reading e with values N and N+1 of an auto refresh counter.

As can be seen from FIG. 3, the auto refresh command b is followed by an activation pulse c, which causes the memory content of a memory cell to be read out and rewritten. The precharge pulse d finally re-establishes the original state of the memory cell. After this auto refresh sequence ARS has proceeded, the content e of the auto refresh counter is incremented from N to N+1.

In order to achieve faster memory access and thus optimization, DRAMs can be constructed from a plurality of memory banks A, B, C as is illustrated in FIG. 4. If this is the case, then, in addition to the commands that are otherwise customary in a DRAM, bank select signals bank sel.A, bank sel.B and bank sel.C are also transmitted, which select the respectively addressed memory banks A, B and C. All the memory banks A, B and C receive the same command signals from a command decoder 1, which is driven by an external command “command”, so that one command can in each case act on a plurality of memory banks A, B and/or C.

If an auto refresh command is transmitted in a DRAM, then no further command is allowed to be input owing to the ensuing complicated progression of the subsequent commands, such as activation pulse and precharge pulse. At an operating frequency of 200 MHz, these 40 ns correspond to about 8 clock cycles (CLK), which means at most 8 commands. The DRAM cannot be accessed during these 8 clock cycles. This also means, however, that even those memory banks which are not actually addressed by the auto refresh command cannot be accessed.

SUMMARY OF THE INVENTION

The object of the invention is to provide a method of carrying out auto refresh cycles in a DRAM which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which allows carrying out auto refresh sequences in which those memory banks which are currently not being subjected to an auto refresh sequence can be accessed by means of commands.

With the above and other objects in view there is provided, in accordance with the invention, a method for carrying out auto refresh sequences on a DRAM having a plurality of memory banks. The method comprises the following steps:

applying a clock signal to a DRAM divided into memory banks;

during an auto refresh sequence acting on a memory address, supplying an activation pulse for reading and rewriting and a precharge pulse indicating an original state from a command decoder;

synchronizing the auto refresh sequence with the clock signal, selecting at least one memory bank with a select signal, and feeding the activation pulse and the precharge pulse to the at least one memory bank selected by the select signal; and

forbidding further commands only for the at least one memory bank selected by the auto refresh sequence, and transmitting the precharge pulse during an operating intermission or deriving the precharge pulse from a precharge pulse of another memory bank.

In other words, the auto refresh sequence is synchronized with the clock signal, the activation pulse and the precharge pulse are fed to at least one memory bank selected by the select signal, and further commands are forbidden only for the at least one memory bank selected by the auto refresh sequence, and the precharge pulse is transmitted during an operating intermission or is derived from a precharge pulse of another memory bank.

In the case of the method according to the invention, therefore, during an auto refresh sequence, further commands which differ from the auto refresh command and the activation pulse are forbidden only for those memory banks which are currently selected by the auto refresh command.

If an auto refresh command is transmitted for a selected memory bank, then this auto refresh command is followed by an activation pulse for that memory bank with a corresponding refresh address supplied by the counter. In the example of FIG. 3, the memory address for the counter reading N+1 follows the memory address for the counter reading of N. An auto refresh logic configuration contained in the command decoder 1 or connected thereto registers the selected memory banks. In a following clock cycle CLK, it is already possible to process other memory banks with other commands. After 30 ns or 6 clock cycles, for example, the memory bank has experienced a refresh. Instead of 6 clock cycles, it is also possible to choose a number of clock cycles, for example 20 clock cycles. A precharge pulse must then also be transmitted to the memory bank. However, since there are only one command decoder 1 and also only one precharge line, said precharge pulse cannot be output immediately after the 30 ns or 6 clock cycles have elapsed. The system waits, therefore, until a user no longer outputs a command: the intermission occurring as a result of this is utilized internally in the DRAM to select the memory bank that is currently being subjected to the auto refresh and to supply a precharge pulse to said memory bank.

As an alternative, it is also possible to utilize the precharge pulse which, after an auto refresh sequence on one memory bank has ended, is subsequently fed to another memory bank. In other words, in this exemplary embodiment, both memory banks are supplied with the same precharge pulse.

The method according to the invention affords the advantage that the DRAM is only blocked for the one clock cycle in which the auto refresh pulse is present. During the following clock cycles, the DRAM can be fully utilized for other commands even though the auto refresh sequence is currently proceeding in the selected memory bank.

If a DRAM comprises two banks, for example, and if the latter are processed alternately with the synchronous auto refresh command, then, in the case of such a structure, only the even addresses would experience a refresh in one memory bank and only the odd addresses would experience a refresh in the other memory bank, since the auto refresh address counter is incremented upon each command. Therefore, it is expedient to implement two auto refresh commands from the command decoder 1, the counter being incremented in the case of one auto refresh command and not being incremented in the case of the other auto refresh command.

Other features which are considered as characteristic for the invention are set forth in the appended claims.

Although the invention is illustrated and described herein as embodied in a method for carrying out auto refresh sequences on a DRAM, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a timing diagram with a temporal sequence of commands in a first exemplary embodiment of the invention;

FIG. 2 is a timing diagram with a temporal sequence of commands in a second exemplary embodiment of the invention;

FIG. 3 is a similar timing diagram of a temporal sequence of commands in a prior art system; and

FIG. 4 is a simplified block diagram of a DRAM.

FIGS. 3 and 4 are explained in the introductory text above. In FIGS. 1 and 2, the same reference symbols as in FIGS. 3 and 4 are used for mutually corresponding components.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the figures of the drawing illustrating the invention in detail and first, particularly, to FIG. 1 thereof, the commands “command”, namely auto-refresh, activate and NOP (no operation), are synchronized with the clock signal (CLK) a.

In the example of FIG. 1, during a memory bank select signal bank sel.A for selecting the memory bank A (see FIG. 4), an activation pulse c is output in the auto refresh sequence. An auto refresh is thereby initiated for the memory bank A. During the auto refresh pulse, that is to say during the clock cycle “0”, the memory banks cannot be accessed by further commands. However, after the clock cycle “0” has elapsed, that is to say upon the next clock cycle “1”, it is already possible to process other memory banks in addition to the memory bank A with further commands.

After 30 ns or 6 clock cycles, the memory bank A has experienced a refresh, so that this activation is concluded or effected. A precharge pulse must then also be transmitted to the memory bank A. For this purpose, the system waits until a user does not transmit a command (“NOP”). The resultant intermission is utilized internally to select the memory bank A that is being subjected to the auto refresh sequence and to supply a precharge pulse d.

In FIG. 1, the pulses identified by arrows D are generated by the auto refresh sequence and are terminated by the NOP intermission occurring after activation has been effected.

With reference to FIG. 2, there is illustrated a further exemplary embodiment of the present invention. Here, once the memory bank A has been activated, the precharge command for the memory bank C is also concomitantly used for the memory bank A in order thus to end the auto refresh sequence for the memory bank A.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6862238Sep 25, 2003Mar 1, 2005Infineon Technologies AgMemory system with reduced refresh current
US6894917Jan 17, 2003May 17, 2005Etron Technology, Inc.DRAM refresh scheme with flexible frequency for active and standby mode
US6914841Jan 30, 2004Jul 5, 2005Infineon Technologies AgSystem and method for refreshing a dynamic memory device
US7145827Dec 22, 2004Dec 5, 2006Hynix Semiconductor, Inc.Refresh control circuit and method for multi-bank structure DRAM
US7158434Apr 29, 2005Jan 2, 2007Infineon Technologies, AgSelf-refresh circuit with optimized power consumption
US7260010Nov 27, 2006Aug 21, 2007Hynix Semiconductor Inc.Refresh control circuit and method for multi-bank structure DRAM
US7330391Oct 17, 2005Feb 12, 2008Infineon Technologies AgMemory having directed auto-refresh
US7433261Oct 17, 2005Oct 7, 2008Infineon Technologies AgDirected auto-refresh for a dynamic random access memory
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Classifications
U.S. Classification365/222, 365/189.15, 365/233.16, 365/233.17, 365/230.06, 365/230.03, 365/189.16, 365/233.11
International ClassificationG11C11/406
Cooperative ClassificationG11C11/406
European ClassificationG11C11/406
Legal Events
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Sep 25, 2013FPAYFee payment
Year of fee payment: 12
Jan 13, 2010ASAssignment
Owner name: QIMONDA AG, GERMANY
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Effective date: 20060425
Sep 18, 2009FPAYFee payment
Year of fee payment: 8
Sep 22, 2005FPAYFee payment
Year of fee payment: 4
Jan 18, 2002ASAssignment
Owner name: INFINEON TECHNOLOGIES AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FIBRANZ, HEIKO;REEL/FRAME:012511/0092
Effective date: 20001204
Owner name: INFINEON TECHNOLOGIES AG ST. MARTIN STRASSE 53 816
Owner name: INFINEON TECHNOLOGIES AG ST. MARTIN STRASSE 538166
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