|Publication number||US6373725 B1|
|Application number||US 09/716,698|
|Publication date||Apr 16, 2002|
|Filing date||Nov 20, 2000|
|Priority date||Nov 20, 2000|
|Also published as||CN1230966C, CN1418395A, EP1260013A2, WO2002041480A2, WO2002041480A3|
|Publication number||09716698, 716698, US 6373725 B1, US 6373725B1, US-B1-6373725, US6373725 B1, US6373725B1|
|Inventors||Chin Chang, Adan Hernandez, Gert Bruning|
|Original Assignee||Philips Electronics North America Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Referenced by (20), Classifications (13), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates generally to power converters, and more particularly to switchable power converters for multiple level input line power factor correction.
2. Background of the Invention
FIG. 1 illustrates a conventional power converter circuit operating as a high frequency electronic ballast for multiple gas discharge lamps 190. Referring to FIG. 1, the power converter circuit basically comprises two stages. The front end is a boost converter 100 for universal line power factor correction and universal line voltage regulation. The boost converter 100 is primarily comprised of a power switch 102, inductor 104, diode 106, and DC bus capacitor 108.
The back end is a typical voltage-fed half-bridge inverter 140 loaded with the lamps 190 through a resonant tank circuit comprised of a capacitor 152 and inductor 154, along with any magnetizing inductance generated by output transformer 156. The half-bridge inverter is primarily comprised of power switches 148 and 150.
The boost converter of FIG. 1 is ideal for providing a DC bus voltage 112 of 450 VDC (across capacitor 108) for input voltages of 120V/277V AC. The relatively high DC output voltage level is due to the fact that the intrinsic topology of the boost converter requires the DC bus voltage 112 to be greater than the peak value of the input line voltage.
However, some applications require a lower DC bus voltage, for example 225V DC. In those applications a flyback converter is better suited, since the flyback converter is capable of generating the relatively low DC bus voltage of 225V DC from an input voltage of 120V/277VAC. The flyback converter, however, has several drawbacks, including higher component stresses, lower overall efficiency, larger component sizes, and severely large electromagnetic interference (EMI) conditions.
Alternatively, a single-ended primary inductance converter (SEPIC) may be employed. The SEPIC is capable of producing an intermediate DC output voltage, such as 225V DC. While the SEPIC shares some of the drawbacks of the flyback converter, such as higher component stress, lower overall efficiency and larger size, the SEPIC enjoys improved EMI conditions. This is because the SEPIC input section is similar to the boost converter input section.
It is a characteristic of both the flyback and SEPIC converters that the highest losses occur at the lowest input line voltage and the highest voltage stresses occur at the highest input line voltage over a universal input line voltage range. Among the flyback, SEPIC and boost converters, the boost converter exhibits the highest efficiency and lowest voltage stresses. However, as discussed above, the boost converter is only viable for use at lower input line voltages in the case of 225V DC bus voltage specifications.
A switchable power converter is therefore needed that advantageously switches between a boost converter circuit topology, for low input line voltages, and either a flyback or SEPIC converter circuit topology, for high input line voltages, to provide an intermediate DC output voltage level, such as 225V DC, over a range of input line voltage levels.
It is therefore an object of the present invention to provide a switchable power converter.
It is another object of the present invention to provide a switchable power converter having improved efficiency and reduced stresses over a range of input line voltages.
To achieve the above objects, a switchable power converter in accordance with the present invention includes an input section that receives an AC input voltage and rectifies the AC input voltage and a switchable converter section operative to receive the rectified AC input voltage and convert the rectified AC input voltage to an intermediate DC output voltage. The switchable converter section includes at least one configuration switch operative to switch the switchable converter section between a boost converter topology, for low input line voltages, and either a flyback or SEPIC converter circuit topology, for high input line voltages. The configuration switch may be a relay based mechanical switch or a solid state switch, for example.
The above and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of an exemplary embodiment thereof taken in conjunction with the attached drawings in which:
FIG. 1 is a schematic diagram illustrating a conventional boost converter application;
FIGS. 2A-2D are schematic diagrams illustrating a switchable boost/SEPIC power converter in accordance with the present invention;
FIGS. 3A and 3B are schematic diagrams illustrating a switchable boost/isolated SEPIC power converter in accordance with the present invention; and
FIG. 4A-4C are schematic diagrams illustrating a switchable boost/flyback power converter in accordance with the present invention.
Preferred embodiments of the present invention will be described hereinbelow with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid obscuring the invention with unnecessary detail.
Turning again to the drawings, in which like reference numerals identify similar or identical elements throughout the several views, FIG. 2 illustrates an exemplary circuit topology for a switchable boost/SEPIC converter in accordance with the present invention.
Referring to FIG. 2, when a switch 200 is conductive (closed) in position A, the switchable boost/SEPIC converter is configured as a boost converter topology. In this configuration, the boost converter is comprised primarily of power switch 202, inductor 204 and diode 206. When switch 200 is conductive in position B, a SEPIC converter topology is formed comprised primarily of power switch 202, coupled inductors 204 and 208, capacitor 210 and diode 206.
Referring to FIG. 3, a switchable boost/isolated SEPIC converter is shown. Here, when switch 300 is conductive and switch 301 is not conductive (open), a boost converter topology is formed comprised primarily of power switch 302, inductor 304, and diode 306. When switch 300 is not conductive and switch 301 is conductive, an isolated SEPIC converter topology is formed comprised primarily of power switch 302, inductors 304 and 308 coupled together and also coupled to isolation transformer 312, capacitor 310, and diode 306. Here, inductor 308 may be omitted and replaced by the magnetizing inductance of the isolation transformer 312. As can be appreciated, the circuits of FIGS. 2 and 3 are similar, with the circuit of FIG. 3 providing isolation from the load R0 in the SEPIC configuration via isolation transformer 312.
As discussed above, it is advantageous to configure the circuits of FIGS. 2 and 3 to operate in a boost topology when the input line voltage is approximately 120V AC, since the boost converter provides greater circuit efficiency. However, due to the intrinsic output voltage limitations of the boost converter, a SEPIC converter topology is preferable when the input voltage is approximately 277V AC, in order to obtain a medium output voltage that is lower than the peak input voltage, such as 225V DC.
There are notable practical circuit design considerations when implementing a switchable power converter. First, the power factor correction (PFC) control 225, 325 must be capable of achieving power factor correction for both the boost and SEPIC topologies. The PFC control IC preferably operates each converter in the critical conduction mode. The critical conduction mode is at the boundary between the continuous conduction mode and the discontinuous conduction mode. The operating frequency may vary over each input line voltage cycle. The power switch 202, 302 is switched at the instant the drain-source voltage waveform passes through zero (ZVS condition), thereby minimizing RF interference. One example of a suitable PFC control IC is the Motorolla MC34262 (equivalently L6561D).
Another design consideration is the value of the common inductor 204, 304, which is used in both the boost and SEPIC converter topologies. The proper design of the common inductor 204, 304 is critical to properly centering the circuit operating frequency. The ideal inductance value Lb (corresponding to each of inductors 204 and 304) for the boost converter operated at critical conduction mode is calculated using Equation 1 below:
VinLL is the low line input voltage
Vo is the DC output voltage
Po is the output power
fb is the switching frequency.
The ideal inductance value Ls (coupled inductors 204 and 208, and coupled inductors 304 and 308) for the SEPIC converter operated at critical conduction mode is calculated using Equation 2 below:
VinHL is the high line input voltage
Vo is the DC output voltage
N is the isolation transformer 312 turns ration (N=1 for non-isolated Circuit of FIG. 2)
fs is the switching frequency.
Therefore, for a fixed inductance value (i.e. Lb=Ls), the switching frequency ratio fb/fs is calculated by combining Equations 1 and 2 as shown in Equation 3 below:
From Equation 3 it can be appreciated that for the appropriate values of Vo, N, VinLL, and VinHL, the ratio fb/fs will ideally approach 1. It therefore follows that an ideal switching frequency range may be implemented to accommodate both the boost and SEPIC circuit topologies.
The switching between the boost and SEPIC topologies therefore must depend on the input line voltage level. That is, for low line input voltages, such as 120VAC, the switch 200 must be conductive in position A to configure the converter as a boost converter circuit topology. Alternatively, for high line input voltages, such as 277 VAC, the switch must be conductive in position B to configure the converter as a SEPIC circuit topology. Similarly, for the switchable boost/isolated SEPIC converter of FIG. 3, switch 300 must be conductive, and switch 301 not conductive, at low line input voltages to form a boost converter topology. Switch 300 must not be conductive, and switch 301 conductive, for high line input voltages to form an isolated SEPIC topology.
An ordinarily skilled artisan will recognize there are many different ways to implement the topology switching function described above. The simplest implementation would be factory installed jumpers. Slightly more complicated implementations involving automatic switching schemes may also be employed. For example, an input voltage sensing circuit 220, 420 which controls a relay or solid state switch 200, 400, such as a thyristor, according to the input line voltage may be employed.
Another exemplary implementation utilizes a fuse 218, 318 in series with the inductor 208, 308 to sense the current passing therethrough. The fuse conducts current to the inductor 208, 308 from the DC bus initially, forming a SEPIC (or isolated SEPIC) converter. When the input line voltage is high, such as 277VAC, the fuse completes the circuit and the SEPIC converter configuration is properly formed. However, when a low line input voltage is introduced at the input, such as 120VAC, the current through the fuse is greater. After a given time period, the increased current will cause the fuse to stop conducting and disconnect the inductor 208, 308. This zero current condition in the inductor is then sensed to trigger a solid state switch or relay SW to establish the connection between inductor 204, 304 and diode 206, 306, respectively.
Yet another exemplary implementation utilizes the circuit switching frequency information. In this implementation, the circuit is again initially configured as a SEPIC (or isolated SEPIC) converter and includes a switching-frequency sensing circuit 219, 419. The switching frequency of the converter will vary with the input line voltage level. That is, when the input line voltage is high the switching frequency is higher than it is for low line input voltages. Accordingly, when the lower switching frequency is detected, control signals are initiated by the circuit 219, 419 to change the state of a solid state relay or switch, which thereby changes the configuration of the converter to a boost converter.
Referring now to FIG. 4, a switchable boost/flyback converter is illustrated. When switch 400 is conductive in position A, a boost converter topology is formed comprised primarily of power switch 402, inductor 404 a and diode 406. When switch 400 is conductive in position B, a flyback converter comprised primarily of power switch 402, transformer 404 and diode 406, is formed.
In the switchable boost/flyback converter of FIG. 4, it is advantageous to configure the converter in a boost topology for low line input voltages, such as 120V. The boost converter offers greatly improved circuit efficiency. Alternatively, the converter must be configured in a flyback topology for high line input voltages such as 277 VAC, in order to obtain intermediate output voltages, such as 225 VDC, due to the output voltage limitations of the boost converter.
There are notable circuit design considerations when implementing the switchable boost/flyback power converter. The PFC control 425 may be realized using the MC34262 as discussed above with reference to the boost/SEPIC converter. Each converter topology is preferably operated in a critical conduction mode, with high frequency switching under the ZVS condition.
Another design consideration is the value of the common inductor 404 a (of transformer 404). The proper design of inductor 404 a is critical to properly centering the circuit operating frequency. The ideal inductance value Lf (inductor 404 a) for the flyback converter operated at critical conduction mode is calculated using Equation 4 below:
N is the transformer 404 turns ratio
fk is the switching frequency.
The ideal inductance Ls for the boost converter is calculated using Equation 1 above, where Ls corresponds to the inductance of inductor 404 a.
Therefore, for a fixed inductance value, (i.e. Lf=Ls), the switching frequency ratio fb/fk is calculated by combining Equations 1 and 4 as shown in Equation 5 below:
The switching function may be implemented using the techniques discussed above with respect to the switchable boost/SEPIC converter.
Accordingly, by using a switchable power converter, the most efficient power converter circuit for wide input and/or output range applications is realized. By using the best characteristics of each converter type and combining them in a suitable configuration, circuit efficiency is greatly improved over the single topology circuits, such as the flyback and SEPIC converter.
An ordinarily skilled artisan will recognize that the present invention also encompasses many variations to the exemplary embodiments detailed above. For example, the switching functions of the present invention may be realized using resources shared with, for instance, the power stage components and/or control circuitry to thereby minimize cost and increase compactness. In addition, while the switching actions and number of switches are limited in the exemplary embodiments detailed above, the present invention may include any number of switches/switching actions. Any number of components may be added or removed from the circuit topology in accordance with the switches/switching actions.
In addition, the converter section may be operated using various conduction modes and is not limited to only critical conduction mode. For example, the converter section may also operate in continuous conduction mode, discontinuous conduction mode, and/or any combination of the three modes.
Further, while the exemplary embodiments described above illustratively utilize low line and high line input voltages of 120V/277V AC, respectively, to produce an intermediate DC output voltage of 225V, the circuit components, circuit topology and switching frequency characteristics may be selected as needed to accompany other operating voltages, such as 120V/240V AC input voltages.
While the present invention has been described in detail with reference to the preferred embodiments, they represent mere exemplary applications. Thus, it is to be clearly understood that many variations can be made by anyone having ordinary skill in the art while staying within the scope and spirit of the present invention as defined by the appended claims.
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|U.S. Classification||363/21.01, 323/284, 323/222|
|International Classification||H02M1/42, H02M3/00, H02M1/00, H02M1/10|
|Cooperative Classification||H02M1/4208, H02M2003/1557, Y02B70/126, H02M1/10|
|European Classification||H02M1/42B, H02M1/10|
|Nov 20, 2000||AS||Assignment|
Owner name: PHILIPS ELECTRONICS NORTH AMERICA CORPORATION, NEW
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, CHIN;HERNANDEZ, ADAN;BRUNING, GERT;REEL/FRAME:011287/0462;SIGNING DATES FROM 20001114 TO 20001117
|Apr 6, 2004||CC||Certificate of correction|
|Sep 27, 2005||FPAY||Fee payment|
Year of fee payment: 4
|Oct 8, 2009||FPAY||Fee payment|
Year of fee payment: 8
|Nov 22, 2013||REMI||Maintenance fee reminder mailed|
|Apr 16, 2014||LAPS||Lapse for failure to pay maintenance fees|
|Jun 3, 2014||FP||Expired due to failure to pay maintenance fee|
Effective date: 20140416