|Publication number||US6380557 B2|
|Application number||US 09/726,605|
|Publication date||Apr 30, 2002|
|Filing date||Dec 1, 2000|
|Priority date||Dec 6, 1999|
|Also published as||US6500685, US20010002795, US20020088974|
|Publication number||09726605, 726605, US 6380557 B2, US 6380557B2, US-B2-6380557, US6380557 B2, US6380557B2|
|Original Assignee||Oki Electric Industry Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Non-Patent Citations (1), Referenced by (5), Classifications (18), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The invention relates to a test chip for molding material including fillers and a method for evaluating the molding material by using the test chip.
2. Description of the Related Art
At the very last stage of a process of manufacturing semiconductor chips, a semiconductor chip is molded with a molding material. The molding material is formed of resin with minimum chips of silica glass, which are generally called “fillers”.
During the very last stage of the manufacturing process, it is well known that characteristics of a transistor of the semiconductor chip are deteriorated or that a gate oxide layer of the transistor is destroyed by the fillers because the fillers mechanically damage the surface of the semiconductor chip. Specifically, with an increase in the level of integration of semiconductor chips, a part of circuit patterns should be formed under terminal pads and the distance between the terminal pads should become short, Therefore, the problems caused by the fillers become more seriously because the fillers are stacked between the pads.
To avoid the problems described above, several proposals have been made. For example, forming a thick final passivation layer, forming a wafer coat layer between the final passivation layer and the resin, and developing a low stress resin are proposed. However, since the damage caused by the filler is varied, depending on the resin's manufacture and kinds of circuit structures formed on the semiconductor chips, these proposals are insufficient to resolve the problems described above.
Therefore, it is necessary to test the resin itself to evaluate how and what influences of fillers in resin are given to the semiconductor chip, so that the most appropriate resin can be used for each semiconductor chip in accordance of the test result of the resin itself. To perform the resin test, it is necessary to form a test circuit somewhere on the semiconductor chip. However, if a test circuit is formed somewhere on the semiconductor chip to evaluate the influence of the fillers, the filler does not always stay on the test circuit, and it is almost impossible to predict where the fillers are located on the semiconductor chip. Therefore, a test for the resin could not be performed effectively.
An objective of the invention is to capture fillers at the specific location on a test circuit easily and effectively to evaluate how and what influences of fillers in resin are given to the semiconductor chip. Further, another objective of the invention is to show the result of the evaluation quantitatively. To evaluate the influences, many test chips having different structure, many test chips formed by different steps, and many kinds of resin having different amount of fillers are prepared. By using these different materials to the different test chips, the result of the evaluation can be shown in a quantitative form.
These objectives are achieved by providing a test chip for a molding material including fillers, including, a semiconductor substrate, a test circuit formed on the substrate, the test circuit including at least one transistor, and two dams formed on the substrate for providing a slit therebetween, the slit capturing the fillers of the molding material when the molding material is applied to the test circuit.
Further, these objectives are achieved by providing a method for testing a molding material including fillers for a semiconductor device, including steps of preparing a test chip including a semiconductor substrate, a test circuit formed on the substrate, which includes at lease one transistor, and two dams formed on the substrate for providing a slit therebetween, placing the test chip in molding equipment, injecting the molding material including fillers into the molding equipment, capturing the fillers in the slit, and detecting the influence of the fillers on electrical characteristics of the test chip using the test circuit.
The invention will be more particularly described with reference to the accompanying drawings in which:
FIG. 1 is a sectional view of a test chip of a first embodiment of the invention;
FIG. 2 is a sectional view of a test chip of a second embodiment of the invention;
FIG. 3 is a plane view of a test chip of a third embodiment of the invention; and
FIG. 4 is a plane view of a test chip of a fourth embodiment of the invention.
Referring to FIG. 1, a test chip 100 of a first embodiment includes three transistors A, B and C. These transistors A, B and C are formed on a surface of the semiconductor substrate 1, and are separated to each other by oxide layers 2. A test circuit is formed with these three transistors A, B and C by connecting them to each other with a metal wiring layer 5 for testing electrical characteristics and functions of ROMs or DRAMs formed on the same substrate 1. The test circuit may be formed in a part of ROMs or DRAM. The test chip also includes an intermediate insulating layer 3 and a passivation layer 4, which are formed on the transistors A, B and C. Dams 11 for capturing fillers included in a resin, are formed on the passivation layer 4. The dams 11 are formed in parallel with each other to provide a slit 12 therebetween on the test circuit, so that the fillers are captured in the slits 12 which is located on the test circuit.
Furthermore, the dams 11 are formed perpendicular to a direction of resin flow. The dams 11 are formed of an insulating material such as polyimide, resist or CVD-SiO2.
To form the dams 11, the insulating layer is formed on the entire surface of the passivation layer 4, and then is patterned. The thickness of the dam 11 is set to be in the range from 30 μm to 130 μm. The width of the slit 12 is determined in the range from 150 μm to 500 μm to capture various sizes of the fillers in various formation.
The test chips 100 having the dams 11 and a slit 12 is set in a molding die of molding equipment, and then, the resin is injected into the molding equipment. The flow of the resin is indicated as an arrow in FIG. 1. The fillers 8 in the resin are stacked in the slit 12 between the dams 11. After that, since thermal stress caused by shrinkage when the resin is solidified, thermal stress when the resin is reflowed, and thermal stress caused by heat cycle, are applied to the resin, the captured fillers 8 mechanically damage the transistors A, B and C. Then, by performing a test with the test circuit, a change of electrical characteristics and defective of the functions of ROM or DRAM can be detected.
Then, the test is performed by using another resin with a test chip having the same structure described above, or using the same resin with the test chip having a different structure. By comparing the test results, it is possible to select the best resin for the actual semiconductor chip.
According to the first embodiment, it is easy and effective to capture the fillers 8 of the resin at the specific location on the test circuit because the slit 12 between the dams 11 is formed on the test circuit. Therefore, several kinds of resin having different sizes or amounts of fillers can be tested with several kinds of test chip having different structures. As a result, as it is possible to detect changes of electrical characteristics and defects in the operation of a ROM or a DRAM, the appropriate resin can be used for an actual semiconductor chip.
Further, an alternative test circuit, which does not have a passivasion layer, may be used. After testing the resin with a test chip having an alternative test circuit, the influence of the fillers on the passivation layer can be found by comparing the test results of the test circuit and the alternative test circuit.
Referring to FIG. 2, a test chip 200 of a second embodiment includes a test circuit having three transistors A′, B′ and C′. In contrast to the test chip of the first embodiment, the test chip 200 does not include an intermediate insulating layer and a passivation layer. Since there are no intermediate insulating layers, a gate electrode 213 of each transistor A′, B′ and C′can be formed of aluminum or copper, which is the same material as that of a metalized wire 205 for connecting the transistors to each other. Dams 211 for capturing fillers included in a resin, are formed on the exposed surface of the test chip. The dams 211 are formed in parallel with each other to provide a slit 212 therebetween on the test circuit, so that the fillers 208 are captured in the slit 212, which located on the test circuit. Furthermore, the dams 211 are formed perpendicular to a direction of resin flow. The material of the dams 211 is the same as that used in the first embodiment. Further, the process for forming the dams 211 is also the same as that described for the first embodiment. Moreover, the thickness of each dam 211 and the width of the slit 212 are the same as in the first embodiment, for the same reasons.
According to the second embodiment, since there is no intermediate insulating layers and passivation layers on the transistors A′, B′ and C′, mechanical damage caused by the fillers 208 is applied to a gate electrode 213 of each transistors A′, B′ and C′ directly. Therefore, an ability of the test chip to detect a change of electrical characteristics and defects in the operation of a ROM or a DRAM is increased.
Referring FIG. 3, a test chip 300 of the third embodiment is described. The test chip 300 includes a transistor area 315, and a peripheral area 314 surrounding the transistor area 315. In the peripheral area, a plurality of bonding wire pads 316 is formed. A plurality of dams 311 are formed in parallel with each other to provide slits 312 therebetween in the transistor area 315. Each slit has substantially the same width, of around 500 μm, for capturing fillers contained in resin. Each dam 311 has substantially the same height, of around 130 μm, for capturing the fillers easily. Further, each dam 311 is formed to extend perpendicularly to a direction of resin flow, which is indicated by an arrow in FIG. 3. The material of the dam 311 is the same as that used in the first and second embodiments. Further, the process for forming the dams 311 is also the same as that described above for the first and second embodiments. Transistors forming a test circuit are formed at the bottom in the each slit 312. An intermediate insulating layer and a passivation layer may be formed on the transistors, as in the first embodiment. Alternatively, these layers may not be formed on the transistors, as in the second embodiment.
According to the third embodiment, since the dams 311 and the slits 312 are formed over the entire transistor area 315, it is possible to find out which location the fillers leads to the most mechanical damage to the transistors. Also, when several test circuits of different structures are formed under each slit 312, it is possible to find out what structure leads to the most mechanical damage from the fillers.
Referring to FIG. 4, a test chip 400 of the fourth embodiment is described. The test chip 400 includes a transistor area 415, and a peripheral area 414 surrounding the transistor area 415. In the peripheral area, a plurality of bonding wire pads 416 are formed. A plurality of dams 411 having the height in the range of 30-130 μm, are formed in parallel with each other to provide slits 418, 419 and 420 therebetween in the transistor area 415, each having a different width. Each dam 411 is formed to extend perpendicularly to a direction of resin flow, which is indicated by an arrow in FIG. 4. The material of the dam 411 is the same as that used in the first, second and third embodiments. Further the process for forming the dams 411 is also the same as that described above for the first, second and third embodiments. The widths of the slits 418, 419 and 420 are set to be at 500 μm, 300 μm and 150 μm, respectively. The widths of dams 411 are varied in this embodiment. However, dams having the same width may be used.
Generally, diameters of fillers contained in resin are in the range of 50-150 mm, and the diameters of the fillers depend on kinds of resin. According to the fourth embodiment, since slits having the different widths are formed, it is possible to evaluate any kind of resin. Therefore, even if the diameter of the filler is unknown, the test can be performed. If necessary, after finding the best slit width for the particular resin, using the test chip 400, a test using the test chip of the third embodiment, which chip has the best slits, may be performed.
While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. For example, in the first through fourth embodiments, the influence of the fillers is tested and evaluated electrically by the test circuit. However, it is possible to evaluate the influence visually using a SEM (Scanning Electron Microscope) or a metallurgical Microscope. Therefore, it is not necessary to form a test circuit on the substrate. In this embodiment, the dams are directly formed on a silicon substrate. However, if a layer made of a material softer than fillers, is formed on the exposed substrate, it is easier to observe the influence of the fillers using the SEM. Various other modifications of the illustrated embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. Therefore, the appended claims are intended cover any such modifications or embodiments as fall within the true scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5149662 *||Feb 21, 1992||Sep 22, 1992||Integrated System Assemblies Corporation||Methods for testing and burn-in of integrated circuit chips|
|US5907190 *||Nov 21, 1995||May 25, 1999||Dow Corning Toray Silicone Co., Ltd.||Semiconductor device having a cured silicone coating with non uniformly dispersed filler|
|US6114627 *||Aug 20, 1997||Sep 5, 2000||Micron Technology, Inc.||Underfill coating for LOC package|
|US6274397 *||Jun 1, 1999||Aug 14, 2001||Taiwan Semiconductor Manufacturing Company Ltd.||Method to preserve the testing chip for package's quality|
|1||*||J. Wu et al., "Evaluation and Characterization of High-Performance Filling Encapsulants for System Chips Application," Proceedings of the 2000 Electronic Components and Technology Conference, pp. 937-943, Sep. 2000.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7041532 *||Feb 25, 2004||May 9, 2006||Micron Technology, Inc.||Methods for fabricating interposers including upwardly protruding dams|
|US7064002||Nov 21, 2002||Jun 20, 2006||Micron Technology, Inc.||Method for fabricating interposers including upwardly protruding dams, semiconductor device assemblies including the interposers|
|US7115981||Oct 7, 2003||Oct 3, 2006||Micron Technology, Inc.||Semiconductor device assemblies including interposers with dams protruding therefrom|
|US20030068840 *||Nov 21, 2002||Apr 10, 2003||Grigg Ford B.||Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods|
|US20040166607 *||Feb 25, 2004||Aug 26, 2004||Grigg Ford B.||Methods for fabricating interposers including upwardly protruding DAMS|
|U.S. Classification||257/48, 257/E23.121, 438/15, 324/762.01|
|International Classification||H01L23/31, G01R31/28, H01L21/66, H01L21/56, H01L23/544, H01L23/29|
|Cooperative Classification||H01L2924/0002, G01R31/2884, G01R31/2831, H01L22/34, H01L23/295|
|European Classification||H01L22/34, G01R31/28E11, G01R31/28G4|
|Dec 1, 2000||AS||Assignment|
Owner name: OKI ELECTRIC INDUSTRY CO., LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAKAHARA, MASARU;REEL/FRAME:011361/0336
Effective date: 20001130
|Oct 7, 2005||FPAY||Fee payment|
Year of fee payment: 4
|Mar 5, 2009||AS||Assignment|
Owner name: OKI SEMICONDUCTOR CO., LTD., JAPAN
Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022399/0969
Effective date: 20081001
Owner name: OKI SEMICONDUCTOR CO., LTD.,JAPAN
Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022399/0969
Effective date: 20081001
|Sep 30, 2009||FPAY||Fee payment|
Year of fee payment: 8
|Dec 6, 2013||REMI||Maintenance fee reminder mailed|
|Apr 30, 2014||LAPS||Lapse for failure to pay maintenance fees|
|Jun 17, 2014||FP||Expired due to failure to pay maintenance fee|
Effective date: 20140430