|Publication number||US6381693 B2|
|Application number||US 09/223,809|
|Publication date||Apr 30, 2002|
|Filing date||Dec 31, 1998|
|Priority date||Dec 31, 1998|
|Also published as||US20010042243|
|Publication number||09223809, 223809, US 6381693 B2, US 6381693B2, US-B2-6381693, US6381693 B2, US6381693B2|
|Inventors||Andrew J. Fish, William J. Clem|
|Original Assignee||Intel Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (14), Non-Patent Citations (1), Referenced by (88), Classifications (10), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to arrangements to allow processing systems to be operable with different processors needing differing system firmware.
Firmware typically is hardware specific and must completely match hardware installed within a particular system. However, it has been found that, occasionally, there may be times where it is advantageous to change and/or add hardware within a system. Any change in hardware in the system typically requires a corresponding change of firmware. Previously, upgrading of firmware required obtaining and then physically replacing at least one semiconductor chip. Some newer systems have disk-loaded firmware that is somewhat easier/cheaper to upgrade (e.g., can be downloaded from the Internet). However, such updating procedures may still be too confusing and/or cumbersome to an average user.
The foregoing and a better understanding of the present invention will become apparent from the following detailed description of exemplary embodiments and the claims when read in connection with the accompanying drawings, all forming a part of the disclosure hereof this invention. While the foregoing and following written and illustrated disclosure focuses on disclosing example embodiments of the invention, it should be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
The following represents brief descriptions of the drawings, wherein:
FIG. 1 illustrates an example block diagram of an example processing system for background discussion;
FIG. 2 illustrates an example block diagram of an example processing system embodiment in accordance with the present invention;
FIG. 3 illustrates an example block diagram of an example embodiment of the present invention;
FIG. 4 illustrates an example cross-reference table useable with an embodiment of the present invention; and
FIG. 5 illustrates another example block diagram of an example embodiment of the present invention.
Before beginning a detailed description of embodiments of the subject invention, mention of the following is in order. When appropriate, like reference numerals and characters are used to designate identical, corresponding or similar components in differing figure drawings. Further, in the detailed description to follow, although exemplary components are given, the present invention is not limited to the same. Next, known power connections and/or other connections (e.g., signal lines) are not shown within the FIGS. for simplicity of illustration and discussion, as so as not to obscure the invention. Still further, while example embodiments of the present invention are described with respect to a processor change, the present invention is not limited to use with such processor change. More particularly, embodiments of the present invention may be used with respect to modification of differing arrangements within a processing system. Finally, as used herein, the terminology “firmware” includes any stored code in the processing system which is used for controlling functions of the processing system, with firmware including, but not being limited to, a basic input/output system (BIOS).
Turning now to detailed discussion, FIG. 1 illustrates an example block diagram of an example processing system 10, useful in describing background disadvantages before discussion of example embodiments of the invention. The example system includes a processor unit (PU) 12 which may be any processor, with such PU 12 being coupled to a bus and bus controller 14 of any design. Random access memory (RAM) 16 is coupled to the bus and bus controller 14. An I/O controller 18 is coupled to the bus and bus controller 14, and to at least one I/O device 20. The system 10 includes system firmware 22 which is customized to work with the architectures of the system, e.g., with the PU 12, I/O controller 18 and I/O device(s) 20 for operation of the processing system.
In the FIG. 1 example, differing types of PUs may be implemented as the PU 12, resulting in many diverse possible configurations. For purposes of this disclosure, differing types of processors will be generically referred to using alphabetical tags or designations, such as type A processor, type B processor . . . type N processor. However, embodiments of the present invention are not limited to alphabetical designation, e.g., embodiments of the present invention could just as easily be implemented using numeric and/or alpha-numeric tags or designations, such as differing processor part or model numbers.
Newly purchased systems typically do not have a system firmware problem, i.e., because newly purchased systems typically come with a predetermined hardware configuration (including a predetermined PU), and have system firmware uniquely written (i.e., customized) to the predetermined hardware configuration. However, any subsequent hardware (e.g., PU) change or addition resulting in configuration modification may cause the system firmware to need to be correspondingly updated in order to keep the processing system operating properly. As one example, a problem may exist where differing types of processors are exchanged (e.g., upgradeable) within a particular processing system configuration. Although the present invention is not limited thereto, one upgrade example might be a processor of a 64-bit architecture being substituted for a processor of a 32-bit architecture on a motherboard.
One example problem which might exist, is that the address maps of the system firmware or BIOS firmware for a replaced (i.e., old) PU may not work with a replacement (i.e., new) PU, i.e., such address maps may conflict. More specifically, firmware for respective processor types typically are specific to each processor, and typically cannot be used to run a different processor type.
Problems such as this can only be solved via some type of firmware adjustment, e.g., by physical replacement of the firmware or updating thereof. However, as mentioned previously, replacement or updating of system firmware may be too expensive, too confusing and/or cumbersome to an average user, and often results in substantial problems/delays in getting a processing system to work properly again after even slight modification. Such problems/delays are at the very least inconvenient, and are more probably very disruptive and costly, especially in a business environment.
As a result of such disadvantages, it is desirable for hardware manufacturers, e.g., manufacturers of PU 12, to avoid having installation of their devices (e.g., component upgrading) require substantial user work in updating system firmware 22. What would be ideal is an arrangement adapted to allow a hardware component (e.g., PU 12) modification, without requiring a user to perform a corresponding firmware modification. FIG. 2 illustrates an example embodiment of an example processing system 100 in accordance with the present invention, which mitigates or obviates user work in updating firmware. The bus and bus controller 14, RAM 16, I/O controller 18, and I/O device(s) 20, may be the same as those of FIG. 1, and accordingly redundant description thereof is omitted herein for sake of brevity. Instead, discussion turns to a first example firmware and/or I/O hardware arrangement useable in the example embodiment of the present invention.
More particularly, in practice, if a number of differing hardware configurations (e.g., differing PUs 12) were applied to the FIG. 2 embodiment, some firmware portions may be mutually useable in common for all (or for at least a substantial portion of) the differing configurations, while other respective firmware portions may each be customized for use with one or several of the respective differing configurations (while not being used with others). Accordingly, FIG. 2 contains an example embodiment of a system firmware 101, having a modular firmware layout which accommodates (i.e., provides) both common firmware portions and customized firmware portions in differing accessible areas. More particularly, area 102 stores common firmware portions, whereas area 104 stores a plurality of customized firmware portions for a plurality of hardware types.
For example, area 104 may contain a custom processor type A firmware portion which supports functionality/operation of a processor type A, custom processor type B firmware portion which supports functionality/operation of processor type B, . . . and custom processor type N firmware portion which supports functionality/operation of a processor type N. There typically may be as many custom processor type firmware portions as there are possible types of processors which may be utilized as the PU 12. Each customized firmware portion may be provided in a differing sub-area of the area 104, and may be accessed and executed separately from all of the other customized firmware portions, or may be accessed and executed in conjunction with other ones of the customized firmware portions. Again, embodiments of the present invention are not limited in that N can be of any number of custom firmware portions, while available storage capacity size allotted to the firmware may pose some limitation.
The firmware, which is coupled to the I/O controller, may be stored in a storage device of the non-volatile type such as a FLASH memory, but embodiments of the present invention are not limited thereto. Instead the firmware may alternatively be stored in a read-only memory (ROM), non-volatile RAM (NVRAM), hard-disk (HD), etc. Further, the system firmware may at least partially include a basic I/O system (BIOS). Still further, while the firmware in the FIG. 2 example embodiment is illustrated as being coupled to the I/O controller 18, such firmware may alternatively be coupled to any one of a plurality of other possible addressable locations in the system architecture. More particularly, the possible locations are any address in the address space of the system.
Turning now to further elaboration of the firmware 101, the common firmware portions within area 102 may be accessed and executed upon every system initialization (e.g., before access/execution of any customized firmware portions), irrespective of which type of PU 12 is installed within the system configuration. In contrast, only a selected one or ones of the customized firmware portions within area 104 may be executed upon system initialization (e.g., after access/execution of the common firmware portions).
More specifically, embodiments of the present invention have arrangements (e.g., operations instructed by execution of the common firmware portions) which determine (e.g., during initialization) which particular type of PU 12 is installed within the system configuration, and which utilize such information to access and execute the one or ones of the customized firmware portions corresponding to (i.e., required for use with) the type of PU 12 installed in the system. More specifically, if the installed PU 12 is a processor type B, then a custom processor type B firmware portion would be accessed and executed during system initialization.
An embodiment of the present invention has firmware arrangements allowing it to be configurable with any one of a plurality of different processors, with each of the different processors using a system firmware which is customized relative to the system firmware of other ones of the plurality of different processor types. The invention permits different processor types each having customized system firmware to be substituted in the hardware platform without manual changing of the system firmware. The term customized firmware portions should not be taken as firmware having programming necessarily mutually exclusive of other firmware, but instead, differing customized firmware portions may contain some similar portions of programming and/or may provide similar operations and/or functions.
In continuing discussion, embodiments of the invention have an arrangement(s) to identify (e.g., upon initialization) the type of processor which is installed in the processing system configuration. More particularly, the FIG. 2 example embodiment further illustrates an example processor identifier 106 which may perform one or more processes for identifying the installed PU 12. While the example processor identifier 106 is illustrated as being coupled to the bus controller 14, such identifier may instead be coupled to the system in any one of a plurality of different locations. Further, the processor identifier 106 may be either hardware or software implemented.
During initialization, for example, execution of the common firmware portions by the PU 12 may cause the processor identifier 106 to determine identification of the PU 12. As a non-exhaustive list of possible processes, processor identifier 12 may: have a sensor to sense physical presence of pins or structures unique to differing PUs 12; sense a voltage, current or signal unique to differing PUs 12; optically sense some type of predetermined indicia identifying particular PUs 12; read an identification of the PU type stored in processing system; read a message transmitted on the bus of the bus and bus controller 14; identify a protocol used by the bus of the bus and bus controller 14; determine if a predetermined signal is present or absent in the system; and analyze at least one signal to identify a predetermined signal pattern in the at least one signal customized to the processor type. Practice of embodiments of the present invention is not limited in any way to any particular process for identifying the processor, and the above examples are in no way exhaustive.
Embodiments of the present invention use such resultant (i.e., determined) identification to dynamically (i.e., upon reset or initialization of the system) activate (in addition to the generic common firmware) one or more corresponding ones of the customized firmware portions. More particularly, the processor identifier 106 may additionally have the FIG. 4 cross-reference table 400 for using the identification to determine which one(s) of the custom firmware portions should be executed for each differing type of possible I/O devices. More particularly, the FIG. 4 example illustrates a Cross-Reference Table 400 having entries designating differing possible types of PUs 12 in a “PU Type” column, and further pointer entries (e.g., unique IDs or addresses) designating corresponding firmware portions which should be accessed/executed in a “Pointer(s)” column.
Note that for an installed processor type A, the pointers (represented figuratively by the FIG. 4 dashed oval 410 and the FIG. 2 long/short dashed arrows 410) indicate that the common firmware portions and custom processor type A firmware portions should be accessed and executed. For an installed processor type N, the pointers indicate that the common firmware portions and both the custom processor type A and N firmware portions should be accessed and executed. Note that the type N example shows that multiple custom firmware portions may be accessed and executed for some types of PUs 12. More particularly, the type N example shows that the custom processor type firmware portions are not limited for use only with their own designated type of PUs 12.
The FIG. 2 example embodiment is advantageous in that it allows Cross-Reference Table 400 and/or firmware 101 components to be mass produced and/or generically programmed with common firmware portions, custom firmware portions, PU types and/or pointer(s) to versatilely accommodate all presently known (e.g., as of the date of manufacture) hardware components (e.g., PUs 12). Further, if such components are provided as one or more FLASH memory components, such can be arranged to be easily reprogrammed to upgrade (e.g., via an internet or disk-loaded firmware download).
The table 400 and/or firmware 101 may also provide additional optional information which is used by the system 100 during operation of the PU 12 which is accessed when the system is reset. The additional information may be of diverse types and provide a mechanism for supporting different types of system operation as follows. The additional information: may relate to a chipset used by the I/O controller 18 which is used by the PU 12 during operation of the system 100; may be code used by the system 100 during operation of the PU 12 or code used by the bus controller 18; may encode system responses to system state changes, such as, but not limited to, the system stopping or continuing upon error conditions. Such additional information examples are in no way exhaustive.
Discussion turns next to FIG. 3 which illustrates another example embodiment of the present invention. More particularly, whereas the FIG. 2 firmware arrangements used a Cross-Reference Table 400, pointers and singular firmware component 101, the FIG. 3 firmware arrangement has separate firmware components 104 a and 104 b, and a logical gate arrangement to supply an activating power or signal to only one of the firmware components 104 a and 104 b. That is, the identification from the processor identifier 106 is subjected to the inverse question “IS PROCESSOR TYPE A” loaded, and logical gates 108 and 110 convert the results of such query oppositely to one another. The opposite outputs from the logical gates 108 and 110 are used to either supply power to, or otherwise only activate one of, the separate firmware components 104 a and 104 b.
More particularly, the system 106 is arranged such that if a processor type A is installed in the processor 112 within the processing system, the firmware component 104 a containing the system firmware for the type A processor is activated to provide firmware code to the processor 112, while the firmware component 104 b is deactivated. In contrast, if a processor type B is installed in the processor 112 within the processing system, the firmware component 104 b containing the system firmware for the type B processor is activated to provide firmware code to the processor 112, while the firmware component 104 a is deactivated.
FIG. 5 is similar to FIG. 3, except that the FIG. 5 system 500 shows firmware components 104 a′ and 104 b′ which each include an assembly of separate firmware components. More particularly, the firmware component 104 a′ is illustrated as including a plurality (e.g., four) low pin count (LPC) FLASH memories 0, 1, 2, 3. In contrast, the firmware component 104 b′ is illustrated as including a plurality (e.g., two) LPC FLASH memories 0, 4. The FLASH memories 0 in common with both firmware components 104 a′ and 104 b′ are again indicative of the fact that differing PU's 112, may utilize some firmware portions in common. FIG. 5 further shows an LPC super input/output (SIO) component.
For sake of brevity and clarity of illustration and discussion, the FIGS. 3 and 5 example embodiments were illustrated as having only two firmware components 104 a and 104 b for supporting two differing PUs. However, embodiments of the present invention are in no way limited to supporting only two different PUs, or in fact any number of differing PUs. However, the prohibitive cost of a large number of firmware components (i.e., storages), and/or scarcity of space within a processing system, may represent some limitation.
In addition to the embodiments of the present invention being useful in situations wherein a processor modification is made some time after purchase, a universal or standard firmware which versatilely supports installation of different processors would permit hardware platforms to be assembled without requiring firmware change. Further, embodiments of the present invention are applicable to not only personal computers (PCs), but to other processing systems such as servers.
This concludes the description of the preferred embodiments. Although the present invention has been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this invention. More particularly, reasonable variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the foregoing disclosure, the drawings and the appended claims without departing from the spirit of the invention. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4328542 *||Nov 7, 1979||May 4, 1982||The Boeing Company||Secure implementation of transition machine computer|
|US5313584||Nov 25, 1991||May 17, 1994||Unisys Corporation||Multiple I/O processor system|
|US5604905 *||Feb 28, 1995||Feb 18, 1997||Next Software, Inc.||Method and apparatus for architecture independent executable files|
|US5752032 *||Nov 21, 1995||May 12, 1998||Diamond Multimedia Systems, Inc.||Adaptive device driver using controller hardware sub-element identifier|
|US5805902||Oct 28, 1997||Sep 8, 1998||Elonex I.P. Holdings, Ltd.||Structure and method for issuing interrupt requests as addresses and for decoding the addresses issued as interrupt requests|
|US5832280||Oct 5, 1995||Nov 3, 1998||International Business Machines Corporation||Method and system in a data processing system for interfacing an operating system with a power management controller.|
|US5835704 *||Nov 6, 1996||Nov 10, 1998||Intel Corporation||Method of testing system memory|
|US5835775 *||Dec 12, 1996||Nov 10, 1998||Ncr Corporation||Method and apparatus for executing a family generic processor specific application|
|US5938765 *||Aug 29, 1997||Aug 17, 1999||Sequent Computer Systems, Inc.||System and method for initializing a multinode multiprocessor computer system|
|US5943673||May 10, 1996||Aug 24, 1999||General Signal Corporation||Configuration programming system for a life safety network|
|US5958049||Mar 17, 1997||Sep 28, 1999||International Business Machines Corporation||Operating system debugger using kernel and dynamic extension with debugger drivers to support different output devices|
|US6049668 *||Apr 13, 1998||Apr 11, 2000||Intel Corporation||Method and apparatus for supporting multiple processor-specific code segments in a single executable|
|US6065067||Mar 5, 1998||May 16, 2000||Compaq Computer Corporation||System, method and program for controlling access to an input/output device possible resource settings data in an advanced configuration and power interface operating system|
|US6081890 *||Nov 30, 1998||Jun 27, 2000||Intel Corporation||Method of communication between firmware written for different instruction set architectures|
|1||Harvey M. Deitel, "An Introduction to Operating Systems," Addision-Wesley Publishing Company, Inc., First Edition, p. 5, lines 15-19 (No Publ. Date Avail.).|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6745324 *||Nov 16, 2000||Jun 1, 2004||International Business Machines Corporation||Dynamic firmware image creation from an object file stored in a reserved area of a data storage device of a redundant array of independent disks (RAID) system|
|US6910115 *||Oct 31, 2001||Jun 21, 2005||Hewlett-Packard Development Company, L.P.||System and method for configuring a removable storage medium|
|US6985987 *||Oct 22, 2001||Jan 10, 2006||Via Technologies, Inc.||Apparatus and method for supporting multi-processors and motherboard of the same|
|US7003656 *||Jun 13, 2002||Feb 21, 2006||Hewlett-Packard Development Company, L.P.||Automatic selection of firmware for a computer that allows a plurality of process types|
|US7036007 *||Sep 9, 2002||Apr 25, 2006||Intel Corporation||Firmware architecture supporting safe updates and multiple processor types|
|US7043585 *||Mar 13, 2002||May 9, 2006||Sun Microsystems, Inc.||Flexible system architecture with common interface for multiple system functions|
|US7134007 *||Jun 30, 2003||Nov 7, 2006||Intel Corporation||Method for sharing firmware across heterogeneous processor architectures|
|US7159105 *||Jun 30, 2003||Jan 2, 2007||Intel Corporation||Platform-based optimization routines provided by firmware of a computer system|
|US7246222 *||Apr 21, 2003||Jul 17, 2007||Hewlett-Packard Development Company, L.P.||Processor type determination based on reset vector characteristics|
|US7281243||Dec 29, 2003||Oct 9, 2007||Intel Corporation||System and method to enable seamless diffusion of platform-based optimized routines via a network|
|US7305544 *||Dec 10, 2004||Dec 4, 2007||Intel Corporation||Interleaved boot block to support multiple processor architectures and method of use|
|US7350063 *||Jun 11, 2002||Mar 25, 2008||Intel Corporation||System and method to filter processors by health during early firmware for split recovery architecture|
|US7363484 *||Sep 15, 2003||Apr 22, 2008||Hewlett-Packard Development Company, L.P.||Apparatus and method for selectively mapping proper boot image to processors of heterogeneous computer systems|
|US7389508||Sep 25, 2003||Jun 17, 2008||International Business Machines Corporation||System and method for grouping processors and assigning shared memory space to a group in heterogeneous computer environment|
|US7392511 *||Sep 25, 2003||Jun 24, 2008||International Business Machines Corporation||Dynamically partitioning processing across plurality of heterogeneous processors|
|US7415703||Sep 25, 2003||Aug 19, 2008||International Business Machines Corporation||Loading software on a plurality of processors|
|US7444632||Sep 25, 2003||Oct 28, 2008||International Business Machines Corporation||Balancing computational load across a plurality of processors|
|US7454603||Feb 11, 2002||Nov 18, 2008||Intel Corporation||Method and system for linking firmware modules in a pre-memory execution environment|
|US7472297||Dec 15, 2005||Dec 30, 2008||International Business Machines Corporation||Method initializing an environment of an integrated circuit according to information stored within the integrated circuit|
|US7475257||Sep 25, 2003||Jan 6, 2009||International Business Machines Corporation||System and method for selecting and using a signal processor in a multiprocessor system to operate as a security for encryption/decryption of data|
|US7478390||Sep 25, 2003||Jan 13, 2009||International Business Machines Corporation||Task queue management of virtual devices using a plurality of processors|
|US7496917||Sep 25, 2003||Feb 24, 2009||International Business Machines Corporation||Virtual devices using a pluarlity of processors|
|US7516252||Jun 8, 2005||Apr 7, 2009||Intel Corporation||Port binding scheme to create virtual host bus adapter in a virtualized multi-operating system platform environment|
|US7516456||Sep 25, 2003||Apr 7, 2009||International Business Machines Corporation||Asymmetric heterogeneous multi-threaded operating system|
|US7523157||Sep 25, 2003||Apr 21, 2009||International Business Machines Corporation||Managing a plurality of processors as devices|
|US7549145||Sep 25, 2003||Jun 16, 2009||International Business Machines Corporation||Processor dedicated code handling in a multi-processor environment|
|US7617391 *||Dec 15, 2005||Nov 10, 2009||Lsi Logic Corporation||Method and apparatus for dynamically selecting one of multiple firmware images for booting an I/O controller|
|US7653808 *||Nov 27, 2002||Jan 26, 2010||Intel Corporation||Providing selectable processor abstraction layer components within one BIOS program|
|US7653908||Mar 4, 2008||Jan 26, 2010||International Business Machines Corporation||Grouping processors and assigning shared memory space to a group in a heterogeneous computer environment|
|US7694306||Jun 25, 2008||Apr 6, 2010||International Business Machines Corporation||Balancing computational load across a plurality of processors|
|US7748006||Jun 2, 2008||Jun 29, 2010||International Business Machines Corporation||Loading software on a plurality of processors|
|US7844945 *||Aug 3, 2005||Nov 30, 2010||Avocent Fremont Corp.||Software and firmware adaptation for unanticipated/changing hardware environments|
|US7921151||Jul 19, 2008||Apr 5, 2011||International Business Machines Corporation||Managing a plurality of processors as devices|
|US7996693||Nov 25, 2008||Aug 9, 2011||International Business Machines Corporation||Integrated circuit environment initialization according to information stored within the integrated circuit|
|US8086833||Sep 8, 2008||Dec 27, 2011||Intel Corporation||Method and system for linking firmware modules in a pre-memory execution environment|
|US8091078||May 7, 2008||Jan 3, 2012||International Business Machines Corporation||Dynamically partitioning processing across a plurality of heterogeneous processors|
|US8219981||Jul 15, 2008||Jul 10, 2012||International Business Machines Corporation||Processor dedicated code handling in a multi-processor environment|
|US8250373||Oct 29, 2008||Aug 21, 2012||Hewlett-Packard Development Company, L.P.||Authenticating and verifying an authenticable and verifiable module|
|US8549521||Mar 14, 2008||Oct 1, 2013||International Business Machines Corporation||Virtual devices using a plurality of processors|
|US20030084262 *||Oct 31, 2001||May 1, 2003||Weirauch Charles Robert||System and method for configuring a removable storage medium|
|US20030154368 *||Feb 11, 2002||Aug 14, 2003||Stevens, William A.||Method and system for linking firmware modules in a pre-memory execution environment|
|US20030188067 *||Mar 13, 2002||Oct 2, 2003||Kenneth Okin||Flexible system architecture with common interface for multiple system functions|
|US20030229775 *||Jun 11, 2002||Dec 11, 2003||Schelling Todd A.||System and method to filter processors by health during early firmware for split recovery architecture|
|US20030233536 *||Jun 13, 2002||Dec 18, 2003||Sachin Chheda||Automatic selection of firmware for a computer that allows a plurality of process types|
|US20040049669 *||Sep 9, 2002||Mar 11, 2004||Schelling Todd A.||Firmware architecture supporting safe updates and multiple processor types|
|US20040092024 *||Apr 25, 2003||May 13, 2004||Ventana Medical Systems, Inc.||Method and apparatus for automated coverslipping|
|US20040103273 *||Nov 27, 2002||May 27, 2004||Goud Gundrala D.||Delaying the authentication of a processor abstraction layer component|
|US20040123070 *||Dec 23, 2002||Jun 24, 2004||Shidla Dale J.||Automatic detection of different microprocessor architectures|
|US20040210750 *||Apr 21, 2003||Oct 21, 2004||Chheda Sachin N.||Processor type determination|
|US20040249992 *||Apr 30, 2003||Dec 9, 2004||Komarla Eshwari P.||Methods and apparatus to provide environment-based instruction selection|
|US20040268107 *||Jun 30, 2003||Dec 30, 2004||Zimmer Vincent J.||Method for sharing firmware across heterogeneous processor architectures|
|US20040268109 *||Jun 30, 2003||Dec 30, 2004||Rothman Michael A.||Platform-based optimization routines provided by firmware of a computer system|
|US20050060531 *||Sep 15, 2003||Mar 17, 2005||Davis Michael Ryan||Apparatus and method for selectively mapping proper boot image to processors of heterogeneous computer systems|
|US20050071513 *||Sep 25, 2003||Mar 31, 2005||International Business Machines Corporation||System and method for processor dedicated code handling in a multi-processor environment|
|US20050071526 *||Sep 25, 2003||Mar 31, 2005||International Business Machines Corporation||System and method for virtual devices using a plurality of processors|
|US20050071651 *||Sep 25, 2003||Mar 31, 2005||International Business Machines Corporation||System and method for encrypting data using a plurality of processors|
|US20050071828 *||Sep 25, 2003||Mar 31, 2005||International Business Machines Corporation||System and method for compiling source code for multi-processor environments|
|US20050081181 *||Sep 25, 2003||Apr 14, 2005||International Business Machines Corporation||System and method for dynamically partitioning processing across plurality of heterogeneous processors|
|US20050081182 *||Sep 25, 2003||Apr 14, 2005||International Business Machines Corporation||System and method for balancing computational load across a plurality of processors|
|US20050081201 *||Sep 25, 2003||Apr 14, 2005||International Business Machines Corporation||System and method for grouping processors|
|US20050081202 *||Sep 25, 2003||Apr 14, 2005||International Business Machines Corporation||System and method for task queue management of virtual devices using a plurality of processors|
|US20050081203 *||Sep 25, 2003||Apr 14, 2005||International Business Machines Corporation||System and method for asymmetric heterogeneous multi-threaded operating system|
|US20050086655 *||Sep 25, 2003||Apr 21, 2005||International Business Machines Corporation||System and method for loading software on a plurality of processors|
|US20050091473 *||Sep 25, 2003||Apr 28, 2005||International Business Machines Corporation||System and method for managing a plurality of processors as devices|
|US20050091496 *||Oct 23, 2003||Apr 28, 2005||Hyser Chris D.||Method and system for distributed key management in a secure boot environment|
|US20050204089 *||Jun 13, 2004||Sep 15, 2005||Chao-Ping Chuang||Method and related system for accessing lpc memory or firmware memory in a computer system|
|US20060031425 *||Jun 7, 2004||Feb 9, 2006||Northrop Grumman Corporation||Method for imaging computer systems|
|US20060031815 *||Aug 3, 2005||Feb 9, 2006||Osa Technologies, Inc.||Software and firmware adaptation for unanticipated/changing hardware environments|
|US20060047939 *||Sep 1, 2004||Mar 2, 2006||International Business Machines Corporation||Method and apparatus for initializing multiple processors residing in an integrated circuit|
|US20060129795 *||Dec 10, 2004||Jun 15, 2006||Intel Corporation||Interleaved boot block to support multiple processor architectures and method of use|
|US20060282591 *||Jun 8, 2005||Dec 14, 2006||Ramamurthy Krithivas||Port binding scheme to create virtual host bus adapter in a virtualized multi-operating system platform environment|
|US20070061813 *||Aug 30, 2005||Mar 15, 2007||Mcdata Corporation||Distributed embedded software for a switch|
|US20070067614 *||Sep 20, 2005||Mar 22, 2007||Berry Robert W Jr||Booting multiple processors with a single flash ROM|
|US20070143584 *||Dec 15, 2005||Jun 21, 2007||Capps Louis B Jr||Method and apparatus for initializing operational settings of an integrated circuit|
|US20070143589 *||Dec 15, 2005||Jun 21, 2007||Rawe Lawrence J||Method and apparatus for dynamically selecting one of multiple firmware images for booting an I/O controller|
|US20080155203 *||Mar 4, 2008||Jun 26, 2008||Maximino Aguilar||Grouping processors and assigning shared memory space to a group in a heterogeneous computer environment|
|US20080162834 *||Mar 15, 2008||Jul 3, 2008||Daniel Alan Brokenshire||Task Queue Management of Virtual Devices Using a Plurality of Processors|
|US20080168443 *||Mar 14, 2008||Jul 10, 2008||Daniel Alan Brokenshire||Virtual Devices Using a Plurality of Processors|
|US20080235679 *||Jun 2, 2008||Sep 25, 2008||International Business Machines Corporation||Loading Software on a Plurality of Processors|
|US20080250414 *||May 7, 2008||Oct 9, 2008||Daniel Alan Brokenshire||Dynamically Partitioning Processing Across A Plurality of Heterogeneous Processors|
|US20080271003 *||Jun 25, 2008||Oct 30, 2008||International Business Machines Corporation||Balancing Computational Load Across a Plurality of Processors|
|US20080276232 *||Jul 15, 2008||Nov 6, 2008||International Business Machines Corporation||Processor Dedicated Code Handling in a Multi-Processor Environment|
|US20080301695 *||Jul 19, 2008||Dec 4, 2008||International Business Machines Corporation||Managing a Plurality of Processors as Devices|
|US20090006832 *||Sep 8, 2008||Jan 1, 2009||Stevens Jr Willliam A||Method and System for linking Firmware Modules in a Pre-Memory Execution Environment|
|US20090055658 *||Oct 29, 2008||Feb 26, 2009||Hyser Chris D||Authenticating and Verifying an Authenticable and Verifiable Module|
|US20090094446 *||Nov 25, 2008||Apr 9, 2009||Capps Jr Louis Bennie||Integrated circuit environment initialization according to information stored within the integrated circuit|
|EP1787195A2 *||Aug 3, 2005||May 23, 2007||Osa Technologies, Inc.||Software and firmware adaptation for unanticipated/changing hardware environments|
|WO2006017682A2 *||Aug 3, 2005||Feb 16, 2006||Osa Technologies Inc||Software and firmware adaptation for unanticipated/changing hardware environments|
|U.S. Classification||713/1, 713/2|
|International Classification||G06F9/455, G06F9/445|
|Cooperative Classification||G06F9/455, G06F9/44547, G06F9/4401|
|European Classification||G06F9/445P2A, G06F9/44A, G06F9/455|
|Jul 27, 1999||AS||Assignment|
Owner name: INTEL CORP., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FISH, ANDREW J.;CLEM, WILLIAM J.;REEL/FRAME:010120/0953
Effective date: 19990726
|Oct 28, 2005||FPAY||Fee payment|
Year of fee payment: 4
|Oct 21, 2009||FPAY||Fee payment|
Year of fee payment: 8
|Oct 2, 2013||FPAY||Fee payment|
Year of fee payment: 12