US 6381727 B1 Abstract A receiver for data encoded as a series of symbols, each including a plurality of components such as the I and Q components of 16-QAM symbols or other multi-value multi-phase system. Each component denotes values for a plurality of bits. Probability calculation circuits 111-1 through 111-16 use the values of the components constituting each received symbol to calculate the probability that each one of the possible symbols was transmitted and received. Metric calculation circuits 112-1 through 112-4 calculate a bit metric for each bit denoted by the symbol. The bit metric represents the probability that the bit having a specified value was transmitted. The bit metric may be calculated by adding the probabilities calculated by the probability calculation for those possible symbols having a component denoting the specified value of the bit. For example, the sum of the probabilities of all symbols denoting a first bit value of zero gives the probability that a zero bit value was transmitted and received. The data represented by the symbols may represent data encoded by a convolutional code, and the bit metrics may be supplied to a decoder such as a Viterbi decoder.
Claims(14) 1. A data receiver for receiving data including a series of multi-component signals representing symbols selected from a set of possible multi-component, multi-value symbols, each signal denoting values for more than two bits, said data receiver comprising:
bit metric calculation means for calculating a bit metric for a particular bit i, the bit metric is calculated based on ΣP(S
_{j}∩R), wherein P(S_{j}∩R) represents the probability of transmission of symbol S_{j }and reception of received signal R, and ΣP(S_{j}∩R) represents the sum of the probabilities P(S_{j}∩R) of all symbols S_{j }in which the particular bit has a given value, the given value being 0 or 1. 2. A data receiver as claimed in
_{j}∩R))/(ΣP (S_{k}∩R)), wherein P(S_{k}∩R) represents the probability of transmission of symbol S_{k }and reception of received signal R, and ΣP(S_{k}∩R) represents the sum of the probabilities P(S_{k}∩R) of all the set of possible multi-component, multi-value symbols.3. A data receiver as claimed in
4. A data receiver for receiving data including a series of multi-component signals representing symbols selected from a set of possible multi-component, multi-value symbols, each signal denoting values for more than two bits, said data receiver comprising:
(a) a memory having stored therein a set of bit metrics for a particular bit having a predetermined value in the transmitted signal, different bit metrics being stored at different addresses in said memory; and
(b) reading means for selecting at least one address in said memory for each received signal based upon the components of such received signal and reading out of said memory the bit metric stored at each selected address, said reading means and said stored set of bit metrics being arranged so that, for any received signal, the bit metric read out from said memory for each particular bit i will be substantially equal to the bit metric found by calculating a bit metric for such particular bit i based on ΣP(S
_{j}∩R), wherein P(S_{j}∩R) represents the probability of transmission of symbol and reception of received signal R, and ΣP(S_{j}∩R) represents the sum of the probabilities P(S_{j}∩R) of all symbols S_{j }in which the particular bit i has a given value, said given value being 0 or 1. 5. A data receiver as claimed in
_{j}∩R))/(ΣP(S_{k}∩R)), wherein P(S_{k}∩R) represents the probability of transmission of symbol S_{k }and reception of received signal R, and ΣP(S_{k}∩R) represents the sum of the probabilities ΣP(S_{k}∩R) of all of the set of possible multi-component, multi-value symbols.6. A data receiver as claimed in
_{j}∩R).7. A data receiver as claimed in
8. A method of receiving data including a series of multi-component signals representing symbols selected from a set of possible multi-component, multi-value symbols, each signal denoting values for more than two bits, the method comprising:
calculating a bit metric for a particular bit i, the bit metric being calculated based on ΣP(S
_{j}∩R), wherein P(S_{j}∩R) represents the probability of transmission of symbol S_{j }and reception of received signal R, and ΣP(S_{j}∩R) represents the sum of the probabilities P(S_{j}∩R) of all symbols S_{j }in which the particular bit has a given value, the given value being 0 or 1. 9. The method as claimed in
_{j}∩R))/ΣP(S_{k}∩R)), wherein P(S_{k}∩R) represents the probability of transmission of symbol S_{k }and reception of received signal R, and ΣP(S_{k}∩R) represents the sum of the probabilities P(S_{k}∩R) of all the set of possible multi-component, multi-value symbols.10. The method as claimed in
11. A method of receiving data including a series of multi-component signals representing symbols selected from a set of possible multi-component, multi-value symbols, each of the signals denoting values for more than two bits, the method comprising:
providing a memory having stored therein a set of bit metrics for a particular bit having a predetermined value in the transmitted signal, different bit metrics being stored at different addresses in the memory;
selecting at least one address in the memory for each received signal based upon the components of such received signal; and
reading out of the memory the bit metric stored at each selected address so that, for any received signal, the bit metric read out from the memory for each particular bit i will be substantially equal to the bit metric found by calculating a bit metric for such particular bit i based on ΣP(S
_{j}∩R), wherein P(S_{j}∩R) represents the probability of transmission of symbol S_{j }and reception of received signal R, and ΣP(S_{j}∩R) represents the sum of the probabilities P(S_{j}∩R) of all symbols S_{j }in which the particular bit i has a given value, the given value being 0 or 1. 12. The method as claimed in
_{j}∩R))/(ΣP(S_{k}∩R), wherein P(S_{k}∩R) represents the probability of transmission of symbol S_{k }and reception of received symbol R, and ΣP(S_{k}∩R) represents the sum of the probabilities P(S_{k}∩R) of all of the set of possible multi-component, multi-value symbols.13. The method as claimed in
_{j}∩R).14. The method as claimed in
Description The present application is a continuation of Application Ser. No. 08/924,420, filed on Aug. 27, 1997, now abandoned. The present invention relates to an apparatus and a method for receiving data and, more particularly, to a data receiver and a data receiving method for receiving multi-component signals representing values for several data bits. In the U.S.A., digital broadcasting bas already been started. Also in Europe, the organization for standardization “Digital Video Broadcasting (DVB)” has been formed to introduce digital TV broadcasting and its standard system is now being made. Such digital broadcasting is described, for example, in “Europe set to start digital satellite broadcasting in 1996 after successful U.S. nationwide services”, NJKKEI ELECTRONICS 1.15, 1996 (No. 653), pp. 139-151. In digital broadcasting and in other types of data transmission, it is desirable to minimize the power in the signal. This in turn reduces the ratio of signal power to noise power, and increases the probability of transmission errors. An error-correcting code is used to obtain a coding gain which compensates for this effect. Ordinarily, in a system using such a method, error-correcting coding is performed on the transmitting side while error-correcting decoding is performed on the receiving side. A convolutional code is particularly advantageous for transmission on a communication path with a low signal power to noise power ratio (S/N ratio). As further explained below, a convolutional code effectively spreads the information contained in each bit of the original message into several bits of the transmitted signal. The receiver determines the value of each original bit from the received signals representing the bits of the transmitted signal. Because the transmitted signal contains redundant information, the original bit values can still be determined with good accuracy even if some of the bit values in the transmitted signal are corrupted by noise in the transmission path. The receiver can use a probabilistic or “soft” decoding scheme. If a most likely path decoding method such as Viterbi decoding is used, soft decision decoding can be performed easily and a high coding gain can be obtained. In a “punctured” convolutional code, a sequence of bits output from a convolutional encoder is thinned out by deleting some of the bits in accordance with a certain rule. Thus, the redundancy introduced by convolutional encoding is reduced, and a plurality of code rates can be achieved easily. It is also possible to improve tolerance to noise in a transmission path by diffusing bits of an encoded signal, such as the bits of a code sequence output from a punctured convolutional code encoder, in accordance with a certain rule. “Diffusing” in this context refers to shuffling or reordering the bits. FIG. 9 shows an example of a transmitter proposed in accordance with the standard DVB-T for DVB ground wave television. This transmitter uses a punctured convolutional code, bit diffusion and a quadrature phase-shift keying (QPSK) system. In the example shown in FIG. 9, serial data output from an information source FIG. 10 shows an example of the convolutional encoder In this example, the two mother code bits X and Y which are obtained when one original bit is input at terminal FIG. 11 is a state diagram showing state transitions of the convolutional encoder shown in FIG. The inputs and outputs associated with these and other states are shown in FIG. 11 as expressions such as “1/01”, denoting input/outputs. In each such expression, the first digit represents the input, whereas the second digit represents the X output resulting from that input and the last digit represents the Y output resulting from the input. The mother code sequences X and Y provided by convolutional encoder X: 10 Y: 11 Bits corresponding to 1 in the erase map are transmitted but bits corresponding to 0 in the map are not transmitted (erased). Stated another way, every other bit in the X mother code sequence is omitted from the serial bit stream formed by the bit erase circuit. Thus, if the outputs of convolutional encoder The bit erase circuit reduces redundancy in the coded message and thus changes the code rate. Considering the convolutional encoder and the bit erase circuit together, the number of bits in the original message input to the convolutional encoder The bit stream or serialized punctured convolutional code sequence output from the bit erase circuit The data sequences x and y from converter In an example of such bit diffusion, M bits of input data is assumed to be one block, and a suitable value s is set. The bit diffusion process is performed by replacing a vector formed of an M-bit input sequence: (B (B′ The bit diffusion circuits Data sequences x′ and y′ after bit diffusion, constituting a diffused punctured convolutional code message, are output from the bit diffusion circuits Signal point assignment circuit when (x′, y′)=(0, 0), (I′, Q′)=(1/{square root over (2)},1/{square root over (2)}) is set; when (x′, y′)=(0, 1), (I′, Q′)=(1/{square root over (2)},−1/{square root over (2)}) is set; when (x′, y′)=(1, 0), (I′, Q′)=(−1/{square root over (2)},1/{square root over (2)}) is set; and when (x′, y′)=(1, 1), (I′, Q′)=(−1/{square root over (2)},−1/{square root over (2)}) is set. Each set of components (I′,Q′) constitutes one QPSK symbol. Each such symbol includes a first component I′ denoting the value of one bit x′ in the diffused punctured convolutional code message and a second component Q′ denoting the value of another bit y′ in the diffused punctured convolutional code message. A symbol diffusion circuit For example, if N−1 symbols form a diffusion unit block and if a number G smaller than N is selected such that G and N are prime to each other, diffusion is executed as replacement of a vector formed of symbols before diffusion: (S′ (S Diffusion circuit FIG. 13 shows the configuration of a receiver for receiving data from the transmitter shown in FIG. 9. A demodulator A symbol diffusion reversal circuit (S (S′ I component values I′ and Q component values Q′ output from the symbol diffusion reversal circuit (B (B′ The value s used in bit diffusion reversal processing in the bit diffusion reversal circuit The two data sequences (x, y) output from the bit diffusion reversal circuits The bit insertion circuit X: 10 Y: 11 Thus, when data is input in the order of x X Y The output data sequences X and Y are supplied to a Viterbi decoder The Viterbi decoder FIG. 14 shows an example of the Viterbi decoder Outputs (branch metrics) BM00 and BM11 from the branch metric calculation circuits Four state metric storage units An output (state metric) SM00 from state metric storage Each of the ACS circuits Each of the state metric storages The operation of the Viterbi decoder ACS circuit
SM00 is the value of the state metric storage If the result of calculation (1) is smaller, SEL00=0 is supplied to the path memory This calculation will be described with reference to the state transition diagram of FIG. Each of the ACS circuits Path memory FIG. 15 shows a branch metric calculation circuit Data Y input via the terminal Thus, when no insertion flag is supplied, the operation of this branch metric calculation circuit is as described below. The subtracter circuit On the other hand, when the flag indicating insertion in X is input, the selector Each of the branch metric calculation circuits FIG. 16 is a block diagram of the path memory Each of the selectors Other selectors and registers are arranged in the same manner as those described above; the selectors and registers are arranged in n columns (four columns in the example shown in FIG. Outputs from registers The above-described connections in the path memory The increasing demand for high speed data transmission makes it desirable to extend the digital data transmission system described above from the QPSK implementation to other, more complex modulation systems. In the more complex transmission schemes, each transmitted signal denotes values for more than two bits. Each signal typically includes two components, each component having more than two possible nominal values. Examples of such modulation systems include 16-QAM, 64-QAM, and 256-QAM. In the 16-QAM system, each symbol includes two components, and each component has four possible nominal values, so that any one of 16 possible symbols can be transmitted. Thus, each symbol can denote values for four bits. The 64-QAM and 256-QAM systems use symbol sets with 64 and 256 possible symbols to encode six and eight bits per symbol, respectively. By comparison, in the QPSK system described above, only two bits are encoded in each symbol. The more complex transmission systems offer the possibility of higher data transmission rates. However, it is difficult to use an encoding and decoding strategy with convolutional or punctured convolutional coding and with bit diffusion as described above in combination with a multi-component, multi-value modulation system. FIG. 17 depicts a data transmitter using 16-QAM. In FIG. 17, sections corresponding to the QPSK transmitter of FIG. 9 are indicated by the same reference numerals. The convolutional encoder The signal point assignment circuit (I′, Q′)=(3/{square root over (10)},3/{square root over (10)}) when (u′, v′, x′, y′)=(0, 0, 0, 0), and (I′, Q′)=(3/{square root over (10)},1/{square root over (10)}) when (u′, v′, x′, y′)=(0, 0, 0, 1). The symbols produced by signal point assignment circuit A receiver for the 16-QAM signal from the transmitter of FIG. 17, constructed in a manner analogous to the QPSK receiver of FIG. 13, would have the structure shown in FIG. In the QPSK system as described above with reference to FIG. 13, each of the signal components I and Q input from the symbol diffusion reversal circuit The same problem arises in connection with the bit erase and bit insertion operations. Thus, the bit erase circuit It would appear that the problems associated with handling component values representing multiple bits could be obviated by recovering the individual bit values at or immediately after the symbol diffusion reversal circuit However, such a system makes a “hard” decision as to the value of each bit based on the content of a single received signal. It sacrifices the advantages of noise immunity and coding gain obtained by “soft” decoding, such as the Viterbi decoding discussed above, in which information transmitted in several signals, during several unit times, contributes to the decision made by the receiver as to the most probable value for each bit of the reproduced information. Similar problems arise in other multi-value, multi-component modulation systems such 64-QAM or 256-QAM. Thus there has been a need for improved receiving apparatus and methods which can accurately receive and decode data transmitted by a multi-value, multi-component modulation system can be accurately decoded. One aspect of the present invention provides a data receiver for receiving data which includes a series of received multi-component signals representing symbols selected from a set of possible multi-component, multi-value symbols wherein signal denotes values for more than two bits. Typically, each component denotes values for a plurality of bits. The data receiver includes probability calculation means for calculating, from components of each received signal, probabilities that different possible symbols of the symbol set constituted the transmitted symbol represented by the received signal. The receiver further includes bit metric calculation means for calculating bit metrics for the bits denoted by each received signal. The bit metric calculation means may be arranged to calculate a bit metric for a particular bit from the probabilities calculated by the probability calculation means for those possible symbols which denote a predetermined value of that particular bit. For example, in the 16-QAM system discussed above, the probability calculation means preferably calculates, from the I and Q components of each received signal, the probability that each of the symbols shown in FIG. 18 was transmitted. The probability that each symbol was transmitted may be calculated as a function of the distance between the coordinates defined by the components of the received signal and the coordinates defined by the nominal component values of each symbol. The bit metric calculation means may be arranged to calculate the sum of the probabilities of all of the symbols denoting the predetermined value for the bit in question. For example, to calculate the bit metric for the first bit in the 16-QAM system, the system may calculate the sum of the probabilities for all of the symbols denoting a first-bit value of 0, i.e., for all of the symbols having I-component values of 1/{square root over (10)} or 3/{square root over (10)}. To calculate the bit metric for the fourth bit, the bit metric calculation means may calculate the sum of the probabilities for all of the symbols denoting a fourth-bit value of 0, i.e., all of the symbols in which the Q-component value is 3/{square root over (10)} or −3/{square root over (10)}. Other composites of the probabilities, and other functions of the sum of probabilities can be used instead of the simple sum. Because each bit metric represents a single bit of transmitted data, the bit metrics can be handled and subjected to processes such as bit diffusion reversal and bit insertion inverse to the bit diffusion and bit erasure processes applied to single-bit data at the transmitter. The receiver may include means for forming sequences of bit metrics and reordering the bit metrics so as to reverse a bit diffusion operation applied at the transmitter. The receiver may further include means for inserting dummy values into a sequence of bit metrics, thereby reversing a bit erasure operation at the transmitter. However, the bit metrics are not “hard” 1 or 0 values for individual bits. Rather, the bit metric represents the probability that the transmitted symbol included the predetermined value for that particular bit As mentioned above, functions of the sum of probabilities other than the sum itself may be employed. For example, the bit metric may be calculated as the product of −1 and the logarithm of the aforementioned sum of probabilities. According to a further embodiment of the invention, the bit metric calculation means may be operative to calculate a first sum representing the probabilities of transmission of all of the possible symbols in the symbol set and may be arranged to calculate a second sum including only the probabilities of transmission of the symbols having a component denoting the predetermined value of the bit in question. The bit metric calculation means may be arranged to obtain the bit metric for the particular bit by dividing the second sum by the first sum. As further explained below, the quotient so obtained is the value of the conditional posterior probability that the transmitted symbol denoted the predetermined value of the particular bit. A data receiver according to a further aspect of the present invention is also adapted to receive the multi-component signals representing symbols selected from a set of possible symbols in a multi-component, multi-value symbol set. A receiver according to this aspect of the invention includes a memory having stored therein a set of bit metrics for bits having predetermined values in the transmitted signal. Different bit metrics are stored at different addresses in the memory. The receiver according to this aspect of the invention also includes reading means for selecting one or more addresses in the memory for each received signal based on the components of that received signal and reading out of the memory the bit metric stored at each selected address. Preferably, the reading means and the stored set of bit metrics are arranged so that, for any received signal, the bit metric read out from the memory will be substantially equal to the bit metric found by calculating, from the received signal, probabilities that different symbols were transmitted and calculating a bit metric from the calculated probabilities for those symbols having a component denoting the predetermined value of the bit. Thus, preferred receivers according to this aspect of the invention derive the bit metrics by use of a “lookup table” approach rather than by direct calculation, but arrive at substantially the same values of the bit metrics as used in the above-mentioned aspect of the invention. Further aspects of the present invention provide methods of receiving multi-component, multi-value signals representing symbols of a multi-component, multi-value symbol set. The method may include the steps of calculating, from the components of each received signal, probabilities that different possible symbols constituted the transmitted symbol and calculating bit metrics for the bits denoted by the received signal from the probabilities calculated for those possible symbols denoting the predetermined value of the bit. The steps of calculating the probabilities may be performed by determining the distance between the coordinates defined by the components of the received signal and the coordinates defined by the nominal component values of each symbol. The step of calculating the bit metrics may be performed by calculating a sum of the probabilities for those symbols denoting a predetermined value of a bit, as discussed above in connection with the receiver. Other methods according to other aspects of the invention include the steps of selecting at least one address in a memory for each received signal based upon the components of the signal and reading out one or more bit metrics stored at the selected address or addresses in the memory. As discussed above in connection with the receiver, different bit metrics are stored at different addresses in the memory, so that different received signals having different components will cause different bit metrics to be read out of the memory. The arrangement of the stored bit metrics in the memory, and the way in which the address is selected based upon the received components, desirably are selected so that the bit metrics read out from the memory will be equivalent to those arrived at by calculation. Methods in accordance with the foregoing aspects of the invention desirably further include the steps of processing the bit metrics and recovering reproduced data from the processed bit metrics. Most preferably, the bits represented by the received signals include transmitted data which constitutes the original data encoded in a convolutional code. The processing step most preferably includes the step of deconvoluting the bit metrics in a manner inverse to the convolutional code. The deconvoluting step desirably is performed so as to provide a “soft” or most-likelihood decoding, in which the value of each bit in the reproduced data depends upon the value of several bits in the transmitted data. The processing step may include the steps of forming one or more streams of bit metrics and subjecting the bit metrics streams to bit diffusion reversal processing, bit insertion processing or both. As discussed above in connection with the apparatus, the methods allow the use of multi-value, multi-component transmission schemes, while maintaining all of the advantages afforded by bit diffusion, bit erasure and soft decoding. The foregoing and other objects, features and advantages of the present invention will be more readily apparent from the detailed description of the preferred embodiments set forth below, taken in conjunction with the accompanying drawings. FIG. 1 is a block diagram showing the configuration of a data receiver according to one embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of an example of the metric calculation circuit shown in FIG. FIG. 3 is a block diagram showing the configuration of an example of the Viterbi decoder shown in FIG. FIG. 4 is a block diagram showing the configuration of another example of the metric calculation circuit shown in FIG. FIG. 5 is a block diagram showing the configuration of yet another example of the metric calculation circuit shown in FIG. FIG. 6 is a block diagram showing the configuration of a data receiver according to another embodiment of the present invention. FIG. 7 is a block diagram showing the configuration of an example of the second metric calculation circuit shown in FIG. FIG. 8 is a block diagram showing the configuration of an example of the Viterbi decoder shown in FIG. FIG. 9 is a block diagram showing the configuration of a conventional data QPSK transmitter. FIG. 10 is a block diagram showing the configuration of an example of the convolutional encoder shown in FIG. FIG. 11 is a diagram showing state transitions of the convolutional encoder shown in FIG. FIG. 12 is a diagram showing a symbol set of QPSK. FIG. 13 is a block diagram showing the configuration of a conventional QPSK data receiver. FIG. 14 is a block diagram showing the configuration of an example of the Viterbi decoder shown in FIG. FIG. 15 is a block diagram showing the configuration of an example of the branch metric calculation circuit shown in FIG. FIG. 16 is a block diagram showing the configuration of an example of the path memory shown in FIG. FIG. 17 is a block diagram showing the configuration of an example of a data transmitter using 16-QAM. FIG. 18 is a diagram showing a symbol set of 16-QAM. FIG. 19 is a diagram showing the configuration of a hypothetical data receiver for receiving data transmited by the transmitter shown in FIG. FIG. 1 shows a receiver in accordance with one embodiment of the invention. This receiver is arranged to receive data transmitted by the transmitter shown in FIG. The bit metric calculation circuit The probability calculation circuit The probability calculation circuit The probability calculation circuit The posterior probabilities are calculated in the same manner with respect to the other 16-QAM symbols. Thus, sixteen posterior probabilities in all are obtained as calculation results. Various calculation methods are conceivable for calculation in the probability calculation circuits
In this equation, σ represents the square root of ˝ of noise power in the transmission channel. That is, 2σ In this embodiment, the bit metrics are calculated as discussed below by summing the probabilities that symbols denoting 0 values for each bit were transmitted. Therefore, the probability that symbol S1111 was transmitted does not enter into the calculation of the bit metrics. Probability calculation circuit An adder circuit Similarly, a second adder circuit A third adder circuit A fourth adder circuit The bit metric calculation circuit of FIG. 2 calculates P(bi=0∩R), i.e., the posterior probability of transmission of a symbol in which the bit i is 0 and reception of received signal R(I, Q). That is, the metric calculation circuit u′ representing metric P(b v′ representing metric P(b x′ representing metric P(b y′ representing metric P(b Each metric is calculated in accordance with the following equation:
P(Sj∩R) represents the posterior probability of transmission of symbol S The bit metrics calculated by bit metric calculation circuit The reordered sequences of bit metrics u,v,x and y for the first to fourth bits resulting from bit diffusion reversal processing are input to a parallel-serial converter Bit insertion circuit X: 10 Y: 11 is used to insert an arbitrary dummy data item (0 in this case) in the data sequence, and the data sequence is split into two sequences X and Y. The data input to insertion circuit u v Data sequences X and Y are output from the bit insertion circuit FIG. 3 shows the configuration of an example of the Viterbi decoder The values X input to the input terminal The selector The selector The selector The selector The multiplier circuit The output BM00 of the multiplier circuit An output SM00 from a state metric storage The ACS circuits In other respects, the configuration of the Viterbi decoder The Viterbi decoder The selectors Also, the selectors Because branch metric calculation by the multiplier circuits When no dummy data item is inserted in X, the bit metric value X supplied from the bit insertion circuit Similarly, when no dummy data item is inserted in Y, the bit metric value Y supplied from the bit insertion circuit The multiplier circuit Similarly, the multiplier circuit The multiplier circuit The multiplier circuit When a dummy data item inserted in X or Y is supplied, the corresponding one of the selectors The ACS circuit
In these expressions, SM00 represents the value of the state metric storage The ACS circuit The ACS circuits A further embodiment of the bit metric calculation circuit
In this equation, P(bi=0|R) represents the conditional posterior probability that the bit i (bi) (the first, second, third or fourth bit) denoted by a transmitted symbol is 0 when received signal R(Ir, Qr) is received, P(R) represents the probability of signal R(Ir, Qr) being received, and P(bi=0∩R) represents the probability of transmission of a symbol in which the bit i is 0 and reception of received signal R(Ir, Qr). Similarly, the conditional posterior probability that the bit i of a transmitted symbol is 1 when received signal R(Ir, Qr) is received can be obtained by the following equation:
In this equation, P(bi=1|R) represents the conditional posterior probability that bit i of a transmitted symbol is 1 when signal R(Ir, Qr) is received, P(R) represents the probability of signal R(Ir, Qr) being received, and P(bi=1∩R) represents the probability of transmission of a symbol in which the bit i is 1 and reception of signal R(Ir, Qr). The conditional posterior probability that the bit i of a transmitted symbol is 1 when signal R(Ir, Qr) is received can also be obtained by the following equation:
The bit metric calculation circuit of FIG. 4 calculates probabilities for the first through fourth bits constituting each of 16-QAM symbols from the input I component Ir and Q component Qr, and outputs: u representing metric P(b v representing metric P(b x representing metric P(b y representing metric P(b Each of the metrics is calculated in accordance with equation (6) shown above. That is, In this equation, P(Sj∩R) represents the probability of transmission of symbol S On the other hand, P(S In the bit metric calculation circuit shown in FIG. 4, the probability calculation circuits The first through fourth adder circuits S0000, S0001, S0010, S0011, S0100, S0101, S0110, S0111. Adder circuits Adder circuit S0000, S0001, S0010, S0011, S0100, S0101, S0110, S0111, S1000, S1001, S1010, S1011, S1100, S1101, S1110, S1111. Divider circuits A bit metric determination circuit according to a further embodiment of the invention is depicted in FIG. If the symbol diffusion reversal circuit If the received data is converted to digital form at the demodulator, symbol diffusion reversal circuit operates on the I and Q components as digital words, and A/D converters A value stored at the address specified by the address data supplied from the terminals The values stored in each ROM FIG. 6 shows the configuration of a receiver according to a further embodiment of the present invention. The receiver shown in FIG. 6 has the same components as the receiver discussed above with reference to FIGS. 1-3. However, the bit metric calculation device used in the receiver of FIG. 6 incorporates both a first metric calculation circuit The second metric calculation circuit A second logarithmic operation device Likewise, a third logarithmic operation device The first inverting circuit If signal R received by the receiver is dependent with respect to time, the Viterbi decoder is maximum (i.e., a maximum likelihood path). In this equation, R(t) represents a received signal at time t, {R(t)} represents a received signal sequence, and P({R(t)}) represents the probability that a received signal sequence is {R(t)}. Also, bi(t) is the value (0 or 1) of the bit i incorporated in a symbol transmitted at time t, and {bi(t)} represents a transmitted bit data sequence. If the sequence length is 2, {bi(t)} is formed four ways as {00}, {01}, {10} and {11} since each bit can have either of two values (0 or 1) at each of two times t. If the sequence length is 3, {bi(t)} is formed eight ways. If the sequence length is 4, {bi(t)} is formed sixteen ways. The Viterbi decoder Further, in the embodiment of FIG. 6, the functional form of the probability P(bi(t)=0∩R(t)) (P(bi=0∩R) at time t) which is the metric in the first embodiment is assumed to be an exponential function as shown below.
Then the numerator ΠP(bi(t)=0∩R(t)) of equation (12) is:
and the Viterbi decoder
is minimized. Accordingly, the bit metric for each bit i at time t is obtained as the value of an expression:
That is, in the embodiment of FIGS. 1-3, the bit metric calculation circuit
In contrast, in the embodiment of FIGS. 6-8, the second metric calculation circuit The logarithmic operation devices The bit metric determination circuit shown in FIG. 5 may be used in place of the combined first and second metric circuits of FIGS. 6 and 7. Thus, the logarithms of the sums of the above-described posterior probabilities corresponding to the values of I component I′ and Q component Q′ of received signal R are stored in ROMs FIG. 8 shows the configuration of the Viterbi decoder The value X input through the input terminal The selector The selector The selector The selector The adder circuit The output BM00 of the adder circuit An output SM00 from a state metric storage The ACS circuits The ACS circuits In the above-described embodiments, data modulated in accordance with a 16-QAM modulation scheme is demodulated and decoded. However, the present invention is also useful with other multi-value multi-component modulation systems such as 64-QAM or 256-QAM in which each symbol denotes more than two bits. In the 16-QAM, 64-QAM and 256-QAM systems, each of I and Q components denotes two or more bits. The present invention also can be applied to 8-PSK modulation and still other multi-value, multi-component modulation systems. In some of these systems, one component may denote only one bit. Further, although conventional modulation systems use two orthogonal components, the present invention can be applied to modulation systems having a greater number of components in each transmitted signal. Multi-component modulation systems are also known as multi-phase modulation systems. The present invention can be employed with any transmission medium. Thus, although the transmitters and receivers discussed above employ electromagnetic (radio) waves as the transmission medium, the invention can also be used with optical transmission media, such as in encoding and decoding data sent in a fiber optic transmission system. Any other bit diffusion algorithms and/or symbol diffusion algorithms, and the corresponding bit diffusion reversal and symbol diffusion reversal processes, can be used in place of the bit diffusion and symbol diffusion processes and reversal processes used in the embodiments discussed above. Likewise, other bit erasing and bit inserting processes can be substituted for those shown. In still further embodiments, features such as bit diffusion, symbol diffusion and/or bit erasing can be omitted from the transmitter, and in this case the corresponding reversal process is omitted from the receiver. The Viterbi decoders discussed above can be replaced by other types of decoders. Where a convolutional code is employed, the decoder most preferably is a most likely path decoder, i.e., a decoder which determines the content of the reproduced data be determining the most likely path or series of states represented by the received data. The decoder circuit and other circuits described above can be replaced in whole or in part by programmable microprocessors programmed to perform equivalent functions. The disclosure of the copending, commonly assigned United States Patent Application of Tamotsu Ikeda entitled DATA RECEIVER USING APPROXIMATED BIT METRICS and claiming priority of Japanese Patent Application P08-231746, and the disclosure of the copending, commonly assigned United States Patent Application of Tamotsu Ikeda entitled APPARATUS AND METHOD FOR RECEIVING DATA WITH BIT INSERTION and claiming priority of Japanese Patent Application P08-233057, both of said United States Patent Applications being filed on even date herewith, are hereby incorporated by reference herein. As these and other variations and combinations of the features discussed above can be utilized without departing from the present invention, the foregoing description of the preferred embodiments should be taken as illustrating, rather than as limiting, the invention as defined by the claims. Patent Citations
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