Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS6451624 B1
Publication typeGrant
Application numberUS 09/923,144
Publication dateSep 17, 2002
Filing dateAug 7, 2001
Priority dateJun 5, 1998
Fee statusPaid
Also published asUS6501165, US6614104, US20030025188
Publication number09923144, 923144, US 6451624 B1, US 6451624B1, US-B1-6451624, US6451624 B1, US6451624B1
InventorsWarren M. Farnworth, Alan G. Wood, Mike Brooks
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
US 6451624 B1
Abstract
A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly. A method for fabricating the package includes the steps of providing the conductive layer having the conductive traces, attaching the die to the conductive traces, forming the first insulating layer on the conductive layer, forming the second insulating layer on the die, forming the conductive vias through the insulating layers, and then forming the external contacts on the planar surfaces of the insulating layers.
Images(8)
Previous page
Next page
Claims(18)
We claim:
1. A method for fabricating a semiconductor package comprising:
providing a conductive layer having a first side and an opposing second side, and comprising a plurality of conductive traces;
flip chip bonding a semiconductor die to the conductive layer in electrical communication with the conductive traces;
forming a first insulating layer on the first side;
forming a second insulating layer on the second side at least partially covering the die;
forming a plurality of external contacts on the first insulating layer and on the second insulating layer; and
forming a plurality of conductive vias in the first insulating layer and in the second insulating layer in electrical communication with the external contacts and the conductive traces.
2. The method of claim 1 wherein the first insulating layer or the second insulating layer comprises a resist.
3. The method of claim 1 wherein the first insulating layer or the second insulating layer comprises a resist and the forming the conductive vias step comprises exposing and developing the resist.
4. The method of claim 1 further comprising stacking and bonding a second semiconductor package to the semiconductor package.
5. A method for fabricating a semiconductor package comprising:
providing a conductive layer having a first side and an opposing second side and comprising a plurality of conductive traces;
attaching a semiconductor die to the conductive layer in electrical communication with the conductive traces;
forming a first insulating layer on the first side and a second insulating layer on the second side at least partially covering the die, the first insulating layer and the second insulating layer comprising a polymer resist;
forming a plurality of external contacts on the first insulating layer and on the second insulating layer; and
forming a plurality of conductive vias in the first insulating layer and in the second insulating layer in electrical communication with the external contacts and the conductive traces by exposing and developing the resist.
6. A method for fabricating a semiconductor package comprising:
providing a conductive layer having a first side and an opposing second side and comprising a plurality of conductive traces;
attaching a semiconductor die to the conductive layer in electrical communication with the conductive traces;
forming a first insulating layer on the first side, the first insulating layer comprising a glass resin and the conductive traces comprising a metal layer bonded to the first insulating layer;
forming a second insulating layer on the second side at least partially covering the die;
forming a plurality of external contacts on the first insulating layer and on the second insulating layer; and
forming a plurality of conductive vias in the first insulating layer and in the second insulating layer in electrical communication with the external contacts and the conductive traces.
7. A method for fabricating a semiconductor package comprising:
providing a conductive layer having a first side and an opposing second side and comprising a plurality of conductive traces;
attaching a semiconductor die to the conductive layer in electrical communication with the conductive traces;
forming a first insulating layer on the first side;
forming a second insulating layer on the second side at least partially covering the die;
forming a plurality of external contacts on the first insulating layer and on the second insulating layer;
forming a plurality of conductive vias in the first insulating layer and in the second insulating layer in electrical communication with the external contacts and the conductive traces; and
stacking and bonding a second semiconductor package to the semiconductor package.
8. A method for fabricating a semiconductor package comprising:
providing a conductive layer having a first side and an opposing second side and comprising a plurality of conductive traces;
attaching a semiconductor die to the conductive layer in electrical communication with the conductive traces;
forming a first insulating layer on the first side;
forming a second insulating layer on the second side at least partially covering the die;
forming a plurality of external contacts on the first insulating layer and on the second insulating layer;
forming a plurality of conductive vias in the first insulating layer and in the second insulating layer in electrical communication with the external contacts and the conductive traces; and
stacking and bonding a second semiconductor package to the semiconductor package, the second semiconductor package comprising a plurality of second conductive traces having a different configuration than the conductive traces.
9. A method for fabricating a semiconductor package comprising:
providing a conductive layer comprising a plurality of conductive traces, the conductive layer comprising a segment of a lead frame having a first surface and an opposing second surface;
attaching a semiconductor die to the conductive traces;
wire bonding a plurality of wires to the die and to the conductive traces;
forming a first insulating layer on the wires and on the first side;
forming a second insulating layer on the die and on the second side, the second insulating layer comprising a polymer resist;
forming a plurality of external contacts on the first insulating layer and on the second insulating layer;
forming a plurality of first conductive vias in the first insulating layer in electrical communication with the external contacts and the conductive traces by exposing and developing the resist; and
forming a plurality of second conductive vias in the second insulating layer in electrical communication with the external contacts and the conductive.
10. The method of claim 9 wherein the attaching the semiconductor die step comprises forming an adhesive layer between the die and the conductive layer.
11. A method for fabricating a semiconductor package comprising:
providing a conductive layer comprising a plurality of conductive traces, the conductive layer comprising a segment of a lead frame having a first surface and an opposing second surface;
attaching a semiconductor die to the conductive traces;
wire bonding a plurality of wires to the die and to the conductive traces;
forming a first insulating layer on the wires and on the first side, the first insulating layer comprising a polymer resist;
forming a second insulating layer on the die and on the second side;
forming a plurality of external contacts on the first insulating layer and on the second insulating layer;
forming a plurality of first conductive vias in the first insulating layer in electrical communication with the external contacts and the conductive traces by exposing and developing the resist; and
forming a plurality of second conductive vias in the second insulating layer in electrical communication with the external contacts and the conductive traces.
12. A method for fabricating a semiconductor package comprising:
providing a conductive layer comprising a plurality of conductive traces, the conductive layer comprising a segment of a lead frame having a first surface and an opposing second surface;
attaching a semiconductor die to the conductive traces;
wire bonding a plurality of wires to the die and to the conductive traces;
forming a first insulating layer on the wires and on the first side;
forming a second insulating layer on the die and on the second side;
forming a plurality of external contacts on the first insulating layer and on the second insulating layer;
forming a plurality of conductive vias in the first insulating layer and in the second insulating layer in electrical communication with the external contacts and the conductive traces; and
stacking and bonding a second semiconductor package to the semiconductor package.
13. A method for fabricating a semiconductor package comprising:
providing a conductive layer comprising a plurality of conductive traces, the conductive layer comprising a segment of a lead frame having a first surface and an opposing second surface;
attaching a semiconductor die to the conductive traces;
wire bonding a plurality of wires to the die and to the conductive traces;
forming a first insulating layer on the wires and on the first side;
forming a second insulating layer on the die and on the second side;
forming a plurality of external contacts on the first insulating layer and on the second insulating layer;
forming a plurality of conductive vias in the first insulating layer and in the second insulating layer in electrical communication with the external contacts and the conductive traces; and
stacking and bonding a second semiconductor package to the semiconductor package, the second semiconductor package comprising a plurality of second conductive traces having a different configuration than the conductive traces.
14. A method for fabricating a semiconductor package comprising:
providing a conductive layer comprising a plurality of conductive traces having a first surface and an opposing second surface;
flip chip bonding a semiconductor die to the conductive traces;
forming a first insulating layer on the first side;
forming a second insulating layer on the die and on the second side;
forming a plurality of external contacts on the first insulating layer and on the second insulating layer; and
forming a plurality of conductive vias in the first insulating layer and in the second insulating layer in electrical communication with the external contacts and the conductive traces.
15. The method of claim 14 wherein the providing the conductive layer step and the forming the first insulating layer step comprise providing the conductive layer and the first insulating layer as a bi-material panel.
16. The method of claim 14 wherein the first insulating layer or the second insulating layer comprises a polymer resist and the forming the conductive vias step comprises exposing and developing the resist.
17. The method of claim 14 further comprising stacking and bonding a second semiconductor package to the semiconductor package.
18. The method of claim 14 further comprising stacking and bonding a second semiconductor package to the semiconductor package, the second semiconductor package comprising a plurality of second conductive traces having a different configuration than the conductive traces.
Description
CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of application Ser. No. 09/259,861, filed Mar. 1, 1999, U.S. Pat. No. 6,271,056, which is a division of application Ser. No. 09/092,779, filed Jun. 5, 1998, U.S. Pat. No. 6,020,629.

FIELD OF THE INVENTION

This invention relates generally to semiconductor packaging. More particularly, this invention relates to a stackable semiconductor package having an internal conductive layer, to a method for fabricating the package and to an electronic assembly incorporating the package.

BACKGROUND OF THE INVENTION

Semiconductor dice or chips are typically contained in semiconductor packages. This is sometimes referred to as the first level of packaging. A package is required to support, protect, and dissipate heat from a die, and to provide a lead system for power and signal distribution to the die. Typically, the package includes a substrate for supporting the die, an encapsulant for protecting the die and external contacts that provide the lead system to the die.

For example, the substrate can comprise a lead frame for plastic packages, or a circuit board material for BGA packages. The encapsulant can comprise a plastic body which completely encloses the die and the substrate, or simply a glob top which encapsulates only the die. Depending on the type of package, the external contacts can comprise leads, solder balls, pads or pins.

Semiconductor packages can also be constructed such that several packages can be stacked with their external contacts electrically interconnected. The present invention is directed to a semiconductor package that is designed for stacking with similar packages for constructing an electronic assembly. The package includes an internal conductive layer that simplifies the fabrication process, and allows different packages of the assembly to have different circuit configurations.

SUMMARY OF THE INVENTION

In accordance with the present invention, a stackable semiconductor package, a method for fabricating the package, and an electronic assembly constructed using multiple packages are provided.

The package includes a substrate, and a semiconductor die attached to the substrate. The substrate comprises three separate layers including a conductive layer having conductive traces in a desired configuration, and first and second insulating layers on opposing sides of the conductive layer. One of the insulating layers covers the die, and one of the insulating layers covers the conductive traces. The package also includes electrically conductive vias through the insulating layers in electrical communication with the conductive traces. In addition, the package includes arrays of external contacts, such as pads or balls, arranged in matching patterns on each insulating layer in electrical communication with the conductive vias and the conductive traces.

In a first embodiment of the package, the conductive layer comprises a segment of a lead frame having lead fingers which form the conductive traces. In addition, the die is attached and wire bonded to the lead fingers, and the insulating layers are applied to the opposing sides of the lead fingers. Further, the insulating layers comprise a polymer, such as a photoimageable resist, a cured layer, or a tape material, that is etched, developed or machined with openings for the conductive vias.

In a second embodiment of the package, the conductive layer comprises a metal layer, such as copper, patterned with the conductive traces. In this embodiment, the metal layer can be deposited on, or laminated to one of the insulating layers, and then etched to form the conductive traces. In addition, the die is flip chip mounted to the conductive traces, and covered by the other insulating layer.

A method for fabricating the first embodiment package includes the steps of providing the lead frame, and then attaching and wire bonding a plurality of dice to the lead fingers. The method also includes the steps of forming the insulating layers on the lead fingers and the die, forming the openings in the insulating layers, and then depositing a conductive material into the openings to form the conductive vias. In addition, the method includes the steps of forming matching patterns of external contacts on the insulating layers in electrical communication with the conductive vias, and then singulating the lead frame into separate packages.

A method for fabricating the second embodiment package includes the steps of providing the conductive layer on the first insulating layer, and etching the conductive layer to form the conductive traces. In this embodiment the conductive layer and the first insulating layer can be provided as a bi-material panel, such as a glass resin/copper laminate. The method also includes the step of flip chip bonding a plurality of dice to the conductive traces, and then covering the dice with the second insulating layer. In addition, the method includes the steps of forming matching patterns of external contacts on the insulating layers in electrical communication with the conductive vias, and then singulating the panel into separate packages.

In either embodiment, the package is configured for stacking to substantially similar packages to form the electronic assembly. In addition, different packages of the assembly can have different configurations of conductive traces or wire bonds, that provide customized circuit configurations for the different layers of the assembly. This allows selected packages of the assembly to perform a required electronic function, such as address, while the remaining package perform other electronic functions. Rather than providing different circuit configurations in the conductive traces, different wire bonding configurations for the conductive traces can be used.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is an enlarged cross sectional view of a first embodiment semiconductor package constructed in accordance with the invention;

FIG. 1B is cross sectional view of the package taken along line 1B—1B of FIG. 1A illustrating a conductive layer of the package;

FIG. 1C is a bottom view of the package taken along line 1C—1C of FIG. 1A illustrating external contacts of the package;

FIG. 1D is a plan view of the package taken along line 1D—1D of FIG. 1A illustrating external contacts of the package;

FIGS. 2A-2E are schematic cross sectional views illustrating steps in a method for fabricating the package of FIG. 1A;

FIG. 3 is a plan view taken along line 33 of FIG. 2A illustrating the conductive layer prior to fabrication of the package;

FIG. 4 is a cross sectional view of an assembly constructed using several of the packages of FIG. 1A;

FIG. 5A is an enlarged cross sectional view of a second embodiment semiconductor package constructed in accordance with the invention;

FIG. 5B is a bottom view taken along line 5B—5B of FIG. 5A illustrating external contacts of the package;

FIG. 5C is a cross sectional view taken along line 5C—5C of FIG. 5A illustrating a conductive layer of the package;

FIG. 5D is a cross sectional view taken along section line 5D—5D of FIG. 5A illustrating flip chip bonding of bumps on a die to the conductive layer;

FIGS. 6A-6G are schematic cross sectional views illustrating steps in a method for fabricating the package of FIG. 5A;

FIG. 7A is a plan view taken along line 7A—7A of FIG. 6A illustrating a bi-material panel for fabricating the package of FIG. 5A;

FIG. 7B is a bottom view taken along line 7B—7B of FIG. 6B illustrating patterns of conductive traces on the panel; and

FIG. 8 is a cross sectional view of an assembly constructed using several of the packages of FIG. 5A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIGS. 1A-1D, a first embodiment semiconductor package 10 constructed in accordance with the invention is illustrated. The package 10 includes a substrate 12, and a semiconductor die 14 attached and wire bonded to the substrate 12. The substrate 12 comprises three separate layers including a conductive layer 16, a first insulating layer 18, and a second insulating layer 20.

The die 14 includes a semiconductor substrate, such as silicon or gallium arsenide, containing integrated circuits fabricated using well known processes. The die 14 can be a conventional semiconductor component such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static random-access memory (SRAM), an erasable programmable read-only memory (EPROM), a logic circuit (LOGIC), or any other semiconductor device that requires packaging.

The die 14 includes a circuit side 26 (face) and a back side 28. In addition, the die 14 includes a pattern of die contacts 30 on the circuit side 26 in electrical communication with the integrated circuits contained on the die 14. In the illustrative embodiment, the die contacts 30 comprise planar bond pads formed of a wire bondable material (e.g., aluminum). In addition, the die contacts 30 are arranged in a single row along a center line of the circuit side 26 (e.g., center connect). However, the die contacts 30 can comprise any type of die contact including bumped contacts arranged in any suitable pattern (e.g., edge connect, end connect). Also for illustrative purposes, the die contacts 30 are shown as being recessed below a passivation layer on the circuit side 26 of the die 14 as is conventional.

In the illustrative embodiment the die 14 has a generally rectangular peripheral outline, and the package 10 also has a generally rectangular peripheral outline. However, the die 14 and the package 10 can alternately have any peripheral outline such as square, circular or oval. Also, a thickness of the die 14 can be conventional with a thickness of between about 0.2 mm and 0.5 mm being representative.

As shown in FIG. 1B, the conductive layer 16 includes a pattern of conductive traces 22 configured for attachment to the circuit side 26 of the die 14. The conductive traces 22 are also configured for wire bonding to the die contacts 30 on the die 14, and can include plated metal layers, such as silver or gold, to facilitate wire bonding. The conductive layer 16 can comprise a highly conductive metal such as an alloy of nickel or copper selectively plated with silver. In the illustrative embodiment the conductive layer 16 comprises a segment of a lead frame similar to a lead-on-chip lead frame. As such, the conductive traces 22 are formed by the lead fingers of the lead frame.

As also shown in FIG. 1B, wires 32 are bonded to the tip portions of the conductive traces 22, and to the die contacts 30 on the die 14. In addition, an adhesive layer 24 (FIG. 1A) attaches the face side 26 of the die 14 to the conductive traces 22. The adhesive layer 24 can comprise a curable polymer, such as an epoxy, or an adhesive tape suitable for die attach.

As shown in FIG. 1A, the first insulating layer 18 is formed on a first side 34 of the conductive layer 16, and the second insulating layer 20 is formed on an opposing second side 36 of the conductive layer 16. The first insulating layer 18 covers and electrically insulates the wires 32, and the second insulating layer 20 covers and protects the die 14. The thicknesses of the insulating layers 18, 20 can be selected to just cover the wires 32 and the die 14, such that a thickness T of the package 10 can be as small as possible In addition, the exposed major surfaces 42, 44 of the insulating layers 18, 20 can be generally planar as shown, and the edges 46, 48 of the insulating layers 18, 20 generally perpendicular to the major surfaces 42, 44.

The insulating layers 18, 20 can be formed of a same material, or can be different materials. For example, the insulating layers 18, 20 can comprise a curable polymer, such as a photoimageable resist, polyimide, BCB (benzocyclobutene) or a thermal set epoxy, formed using a suitable process such as molding, or dispensing through a nozzle. Alternately, the insulating layers 18, 20 can comprise a tape material such as polyimide tape, or “KAPTON TAPE” having an adhesive surface which adheres to the conductive layer 16.

As also shown in FIG. 1A, the package 10 includes conductive vias 38 in the first insulating layer 18, and conductive vias 40 in the second insulating layer 20. The conductive vias 38, 40 comprise openings in the insulating layers 18, 20 at least partially filled with a conductive material, such as a metal or a conductive polymer. The openings for the conductive vias 38, 40 can be formed using a suitable process such as developing, etching or laser machining the insulating layers 18, 20.

The conductive vias 38 in the first insulating layer 18 terminate on the first side 34 of the conductive layer 16 in electrical communication with the conductive traces 22. In addition, as shown in FIG. 1D, a plurality of first external contacts 50, are formed on the surface 42 of the first insulating layer 18 in electrical communication with the conductive vias 38. In the illustrative embodiment, the first external contacts 50 comprise generally square shaped, planar pads arranged along the longitudinal edges of the package 10. However, the first external contacts 50 can have other shapes and can be arranged in other configurations, such as a dense grid array of rows and columns. In addition, the first external contacts 50 can comprise any suitable conductive material such as copper, aluminum or a conductive polymer. Also, the first external contacts 50 can be formed on the surface 42 using any suitable process such as plating, electroless deposition or screen printing.

The conductive vias 40 in the second insulating layer 20 terminate on the second side 36 of the conductive layer 16 in electrical communication with the conductive traces 22. In addition, as shown in FIG. 1C, a plurality of second external contacts 52, are formed on the surface 44 of the second insulating layer 20 in electrical communication with the conductive vias 40. The second external contacts 52 are arranged in a pattern that matches the pattern of the first external contacts 50. This permits the package 10 to be stacked to similar packages to form an electronic assembly 56 (FIG. 4). The second external contacts 52 can have the same configuration, and can comprise the same material as the first external contacts 52. In addition, the second external contacts 52 can include metal or conductive polymer contact balls 54 configured to facilitate bonding to the first external contacts 50 on an adjacent package of the electronic assembly 56 (FIG. 4).

Referring to FIGS. 2A-2E, steps in a method for fabricating the package 10 are illustrated. Initially, as shown in FIG. 2A, a lead frame 58 is provided. As shown in FIG. 3, the lead frame 58 includes a plurality of patterns of lead fingers 60 which are connected to one another by bus bars 64. For simplicity only two patterns of lead fingers 60 are illustrated, and only two packages 10 at a time are being fabricated. However, the lead frame 58 can include any suitable number of patterns of lead fingers 60 (e.g., 2-12), and a corresponding number of packages 10 can be fabricated at the same time. The patterns of lead fingers 60 will subsequently become the conductive layers 16, and the conductive traces 22 for the packages 10. As also shown in FIG. 3, the lead frame 58 includes spaced side rails 62 that facilitate handling by automated equipment such as die attachers and wire bonders.

Next, as shown in FIG. 2B, semiconductor dice 14 are attached to the patterns of lead fingers 60 on the lead frame 58 using adhesive layers 24. A conventional die attacher, and conventional die attach materials for the adhesive layers 24, can be used to attach the dice 14 to the lead frame 58. As also shown in FIG. 2B, wires 32 are wire bonded to the die contacts 30 on the die 14 and to bonding sites 66 on the lead fingers 60. The bonding sites 66 can comprise a wire bondable metal plating on the lead fingers 60 such as silver or gold. In addition, a conventional wire bonder can be used to wire bond the dice 14 to the lead fingers 64.

Next, as shown in FIG. 2C, the first insulating layer 18 and the second insulating layer 20 for each package 10 are formed on the lead frame 58. The insulating layers 18, 20 can comprise a curable polymer such as photoimageable resist, polyimide, BCB (benzocyclobutene) or a thermal set epoxy, formed using a suitable process such as molding, or dispensing through a nozzle. Alternately, the insulating layers 18, 20 can comprise a tape material such as polyimide tape, or “KAPTON TAPE” having an adhesive surface which adheres to the conductive layer 16. The insulating layers 18, 20 are formed with thicknesses sufficient to cover the wires 32 and the dice 14. Specifically, a thickness of the insulating layers 18 is greater than a loop height of the wires 32, and a thickness of the insulating layers 20 is greater than a thickness of the dice 14. Also, the insulating layers 18 are formed with the planar surfaces 42, and the insulating layers 20 are formed with the planar surfaces 44.

As also shown in FIG. 2C, openings 68 are formed through the surfaces 42 of the insulating layers 18 to the lead fingers 60, and openings 70 are formed through the surfaces 44 of the insulating layers 20 to the lead fingers 60. The openings 68, 70 are preferably formed in patterns that match desired patterns for the external contacts 50, 52 for the packages 10. With the insulating layers 18, 20 comprising a photoimageable resist the openings 68, 70 can be formed by exposing areas of the resist corresponding to the openings 68, 70, and then developing the resist to remove the exposed material. One suitable resist is a negative tone, thick film resist sold by Shell Chemical under the trademark “EPON RESIN SU-8”. This resist can be deposited with a thickness of from about 3-50 mils and can be developed with high aspect ratio features. The openings 68, 70 can also be formed using a mask and an etchant, or can be laser machined through the insulating layers 18, 20. A representative diameter of the openings 68, 70 can be from about 10 μm to 2 mils or greater.

Next, as shown in FIG. 2D, the openings 68, 70 can be at least partially filled with a conductive material such as a metal, or a conductive polymer, to form the conductive vias 38, 40. One method for depositing a metal in the openings is using an electrolytic deposition process. In this case the bus bars 64 (FIG. 3) on the lead frame 58 can be connected to a current source, such that a metal contained in an electrolytic solution will plate onto areas of the lead fingers 60 aligned with the openings 68, 70. This metal will also fill the openings 68, 70.

A metal can also be deposited within the openings 68, 70 using another deposition process, such as CVD or electroless deposition. A solder metal can also be screen printed in the openings 68, 70 as well as with capillary action, or with a vacuum system using a hot solder wave. In addition, the metal can completely fill the openings 68, 70, or alternately can be layers that cover just the inside surfaces or sidewalls of the openings 68, 70. Also, rather than being a metal, the conductive material can comprise a conductive polymer, such as a metal filled silicone, or an isotropic epoxy. A conductive polymer can be deposited within the openings 68, 70, as a viscous material, and then cured as required. A suitable deposition process, such as screen printing, or stenciling, can be used to deposit the conductive polymer into the openings 68, 70.

As also shown in FIG. 2D, the external contacts 50, 52 can be formed on the surfaces 42, 44 in electrical communication with the conductive vias 38, 40. The external contacts 50, 52 can have a square, rectangular, circular or other peripheral configuration. In addition, the external contacts 50, 52 can be formed during formation of the conductive vias 38, 40 of a same material using a suitable mask (not shown), such as a hard mask, or a stencil mask. Alternately, the external contacts 50, 52 can comprise a different material than the conductive vias 38, 40, and can be formed using a separate deposition process.

Next, as shown in FIG. 2E, the lead frame can be trimmed to separate the packages 10. Also, either prior to, or after the separation process, the contact balls 54 can be formed on the external contacts 52. The contact balls 54 can be attached to the external contacts 52 by soldering, laser reflow, brazing, welding, or applying a conductive adhesive. A solder ball bumper can also be used to bond the contact balls 54 to the external contacts 52. A suitable solder ball bumper is manufactured by Pac Tech Packaging Technologies of Falkensee, Germany. The contact balls 54 can also be formed on the external contacts 52 using a conventional wire bonder apparatus adapted to form a ball bond, and then to sever the attached wire. The contact balls 54 can also be formed by electrolytic deposition, or electroless deposition, of a metal to form bumps. The contact balls 54 can also comprise a conductive polymer deposited using a suitable deposition process such as screen printing. A representative diameter for the contact balls 54 can be from about 4 mils to 50 mils or more.

Referring to FIG. 4, the electronic assembly 56 is illustrated. The assembly 56 comprises three separate packages 10-1, 10-2, 10-3 that have been stacked and bonded to one another. A solder reflow process, performed in an oven or with a localized heat source, can be used to bond the contact balls 54, and the external contacts 50, on adjacent packages 10. In addition, the contact balls 54 on the lowermost package 10-3 have been bonded to electrodes 72 on a supporting substrate 74 such as a printed circuit board or a multi chip module substrate. The construction of the packages 10-1, 10-2, 10-3 allows the contact balls 54 on the middle package 10-2 to be bonded to the external contacts 50 on the lowermost package 10-3. In addition, the contact balls 54 on the top package 10-1 are bonded to the external contacts 50 on the middle package 10-2.

One feature of the assembly 56 is that the packages 10-1, 10-2, 10-3 can have different circuit arrangements. Specifically the conductive traces on each of the packages 10-1, 10-2, 10-3 can have a different configuration. Alternately, the wire bonding configuration for the packages 10-1, 10-2, 10-3 can be made to provide different circuit arrangements. In either case, with the different circuit arrangements each of the packages 10-1, 10-2, 10-3 can perform a different electronic function within the assembly 56. For example, some of the packages 10-1, 10-2, 10-3 can perform address functions while others of the packages 10-1, 10-2, 10-3 can perform memory functions.

Referring to FIGS. 5A-5D, a second embodiment semiconductor package 10A constructed in accordance with the invention is illustrated. The package 10A includes a substrate 12A, and a semiconductor die 14A flip chip mounted to the substrate 12A. The substrate 12A comprises three separate layers including a conductive layer 16A, a first insulating layer 18A, and a second insulating layer 20A.

The die 14A includes a semiconductor substrate containing integrated circuits fabricated substantially as previously described for the die 14. In addition, the die 14A includes a circuit side 26A (face) and a back side 28A. In addition, the die 14A includes a pattern of die contacts 30A (FIG. 5D) on the circuit side 26A in electrical communication with the integrated circuits contained on the die 14A. In this embodiment, the die contacts 30A comprise bond pads provided with bumps 76A made of solder or other bondable material. This type of die 14A is sometimes referred to as a “bumped die”. In addition, the die contacts 30A are arranged in an area array of rows and columns. In the illustrative embodiment the die 14A has a generally square peripheral outline, and the package 10A also has a generally square peripheral outline.

As shown in FIG. 5C, the conductive layer 16A includes a pattern of conductive traces 22A, and the die 14A is flip chip mounted to the conductive traces 22A. The conductive traces 22A can comprise a highly conductive metal such as an alloy of copper. As shown in FIG. 5D, the bumps 76A on the die contacts 30A are bonded to bonding sites 78A on the conductive traces 22A. The bonding sites 78A can include a plated metal, such as silver or gold, which facilitates bonding to the bumps 76A.

As shown in FIG. 5A, the first insulating layer 18A is formed on a first side 34A of the conductive layer 16A, and the second insulating layer 20A is formed on an opposing second side 36 of the conductive layer 16A. The first insulating layer 18A covers and electrically insulates the conductive traces 22A, and the second insulating layer 20 covers and protects the die 14A. The thickness of the insulating layer 18A can be several mils or less. The thickness of the insulating layer 20A can be selected to just cover the die 14A, such that a thickness TA of the package 10A can be as small as possible In addition, the exposed major surfaces 42A, 44A of the insulating layers 18A, 20A can be generally planar as shown, and the edges 46A, 48A of the insulating layers 18A, 20A generally perpendicular to the major surfaces 42A, 44A.

The insulating layers 18A, 20A can be formed of a same material, or can be different materials. For example, the insulating layers 18A, 20A can comprise a curable polymer, such as a photoimageable resist, polyimide, BCB (benzocyclobutene) or a thermal set epoxy, formed using a suitable process such as molding, or dispensing through a nozzle. Alternately, the insulating layers 18A, 20A can comprise a tape material such as polyimide tape, or “KAPTON TAPE” having an adhesive surface which adheres to the conductive layer 16A.

As also shown in FIG. 5A, the package 10A includes conductive vias 38A in the first insulating layer 18A, and conductive vias 40A in the second insulating layer 20A. The conductive vias 38A, 40A comprise openings in the insulating layers 18A, 20A at least partially filled with a conductive material, such as a metal or a conductive polymer. The openings for the conductive vias 38A, 40A can be formed using a suitable process such as developing, etching or laser machining the insulating layers 18A, 20A.

The conductive vias 38A in the first insulating layer 18A terminate on the first side 34A of the conductive layer 16A in electrical communication with the conductive traces 22A. In addition, a plurality of first external contacts 50A, are formed on the surface 42A of the first insulating layer 18A in electrical communication with the conductive vias 38A. In the illustrative embodiment, the first external contacts 50A comprise generally square shaped, planar pads arranged along a periphery of the package 10A in rows and columns. However, the first external contacts 50A can have other shapes and can be arranged in other configurations, such as a dense grid array of rows and columns. In addition, the first external contacts 50A can comprise any suitable conductive material such as copper, aluminum or a conductive polymer. Also, the first external contacts 50A can be formed on the surface 42A using any suitable process such as plating, electroless deposition or screen printing.

The conductive vias 40A in the second insulating layer 20A terminate on the second side 36A of the conductive layer 16A in electrical communication with the conductive traces 22A. In addition, as shown in FIG. 5B, a plurality of second external contacts 52A, are formed on the surface 44A of the second insulating layer 20A in electrical communication with the conductive vias 40A. The second external contacts 52A are arranged in a pattern that matches the pattern of the first external contacts 50A. This permits the package 10A to be stacked to similar packages to form an electronic assembly 56A (FIG. 8). The second external contacts 52A can have a same configuration and can comprise the same material as the first external contacts 52A. In addition, the second external contacts 52A can include metal or conductive polymer contact balls 54A configured to facilitate bonding to the first external contacts 50A on an adjacent package of the electronic assembly 56A (FIG. 8).

Referring to FIGS. 6A-6G, steps in a method for fabricating the package 10A are illustrated. Initially, as shown in FIG. 6A, a panel 80A which comprises a metal layer 82A and a first insulating layer 84A is provided. As shown in FIG. 7A, the panel is configured to fabricate four packages 10A as indicated by the dotted lines. As is apparent, the panel 80A can be configured to fabricate a greater or lesser number of packages 10A.

The first insulating layer 84A will subsequently become the first insulating layer 18A (FIG. 5A) for each of the packages 10A. The first insulating layer 84A can comprise an electrically insulating material such as an organic polymer resin reinforced with glass fibers. Exemplary materials include bismaleimide-triazine (BT), epoxy resins (e.g., “FR-4” and “FR-5”), and polyimide resins. These materials can be formed with a desired thickness, and then punched, machined, or otherwise formed with a required peripheral configuration, and with required features.

The metal layer 82A comprises a highly conductive metal which is blanket deposited or laminated to the first insulating layer 84A, and will be subsequently etched to form the conductive traces 22A. However, it is to be understood that an additive process, such as electroless deposition through a mask, can be used to form the conductive traces 22A in required patterns. A preferred metal for the metal layer 82A is copper. Other suitable metals include aluminum, titanium, tungsten, tantalum, platinum, molybdenum, cobalt, nickel, gold, and iridium. If desired, the metal layer 82A and the insulating layer 84A can be constructed from a commercially produced bi-material core, such as a copper clad bismaleimide-triazine (BT) core, available from Mitsubishi Gas Chemical Corp., Japan. A representative weight of the copper can be from 0.5 oz to 2 oz. per square foot.

Next, as shown in FIG. 6B, the metal layer 82A is etched to form the conductive traces 22A. The etching step can be performed by forming a mask (not shown) on the metal layer 82A, such as a resist mask, which includes openings defined by exposure and development steps, and then etching through the openings in the mask. FIG. 7B illustrates the four separate patterns of conductive traces 22A formed by the etching step. These separate patterns will be used to fabricate four separate packages 10A. Following the etching step the bonding sites 78A can also be formed on the conductive traces 22A by plating a metal such as gold or silver in areas that correspond to the location of the bumps 76A on the die 14A. Again, a mask (not shown) can be used to perform the plating step.

Next, as shown in FIG. 6C, the semiconductor dice 14A are flip chip bonded to the conductive traces 22A. During the flip chip bonding step, the bumps 76A on the dice 14A are aligned with, and then bonded to the bonding sites 78A on the conductive traces 22A. The flip chip bonding step can be performed using techniques and equipment that are known in the art. For example, flux can be applied to the bonding sites 78A to temporarily hold the dice 14A on the bonding sites 78A. The bumps 76A can then be heated in an oven, or using a localized heat source, to reflow the solder and form a metallurgical bond between the bumps 76A and the bonding sites 78A.

Next, as shown in FIG. 6D, a second insulating layer 86A can be blanket formed on the panel 80A to cover the dice 14A. The second insulating layer 86A will subsequently become the second insulating layer 20A (FIG. 5A) for each package 10A. The second insulating layer 86A can comprise a curable polymer such as photoimageable resist, polyimide, BCB (benzocyclobutene) or a thermal set epoxy, formed using a suitable process such as molding, or dispensing through a nozzle.

Next as shown in FIG. 6E, openings 68A are formed through the insulating layer 84A to the conductive traces 22A, and openings 70A are formed through the insulating layer 86A to the conductive traces 22A. The openings 68A, 70A are preferably formed in patterns that match desired patterns for the external contacts 50A, 52A for the packages 10A. The openings 68A, 70A can be formed using a developing, etching or laser machining process as previously described.

Next, as shown in FIG. 6F, the openings 68A, 70A can be at least partially filled with a conductive material such as a metal or a conductive polymer to form the conductive vias 38A, 40A. This step can also be performed as previously described. As also shown in FIG. 6F the external contacts 50A, 52A and contact balls 54A can also be formed as previously described.

Next, as shown in FIG. 6G, a singulating step can be performed to separate the packages 10A from the panel 80A. The singulating step can be performed using a suitable process such as cutting, shearing, punching or etching. In the singulated packages 10A, the first insulating layer 84A becomes the first insulating layers 18A for the packages 10A. Similarly, the second insulating layer 86A becomes the second insulating layers 20A for the packages 10A.

As also shown in FIG. 6G, prior to the singulating step, two or more panels 80A can be stacked, and the contact balls 54A and external contacts 50A on adjacent packages 10A bonded to another. A solder reflow process, performed in an oven or with a localized heat source, can be used to bond the contact balls 54A and the external contacts 50A on adjacent packages 10A. Following the bonding step, the panels 80A can be singulated to form stacked assemblies, such as the assembly 56A shown in FIG. 8.

Referring to FIG. 8, the electronic assembly 56A is illustrated. The assembly 56A comprises four separate packages 10A-1, 10A-2, 10A-3, 10A-4 that have been stacked and bonded to one another. In addition, the contact balls 54A on the lowermost package 10A-4 have been bonded to electrodes 72A on a supporting substrate 74A such as a printed circuit board or a multi chip module substrate. As previously described the different packages 10A-1, 10A-2, 10A-3, 10A-4 of the assembly 56A can have different circuit arrangements and can perform different circuit functions in the assembly 56A.

Thus the invention provides a stackable semiconductor package, a method for fabricating the package, and an electronic assembly including two or more of the packages in a stacked configuration. Although the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4505799Jul 16, 1984Mar 19, 1985General Signal CorporationPh sensitive
US4996587Mar 23, 1990Feb 26, 1991International Business Machines CorporationIntegrated semiconductor chip package
US5063177Oct 4, 1990Nov 5, 1991ComsatMethod of packaging microwave semiconductor components and integrated circuits
US5107328Feb 13, 1991Apr 21, 1992Micron Technology, Inc.Packaging means for a semiconductor die having particular shelf structure
US5123850 *Jun 7, 1991Jun 23, 1992Texas Instruments IncorporatedNon-destructive burn-in test socket for integrated circuit die
US5138434Jan 22, 1991Aug 11, 1992Micron Technology, Inc.Packaging for semiconductor logic devices
US5155067Mar 26, 1991Oct 13, 1992Micron Technology, Inc.Packaging for a semiconductor die
US5229647Sep 21, 1992Jul 20, 1993Micron Technology, Inc.High density data storage using stacked wafers
US5266912Aug 19, 1992Nov 30, 1993Micron Technology, Inc.Inherently impedance matched multiple integrated circuit module
US5334857Apr 6, 1992Aug 2, 1994Motorola, Inc.Semiconductor device with test-only contacts and method for making the same
US5384689Dec 20, 1993Jan 24, 1995Shen; Ming-TungIntegrated circuit chip including superimposed upper and lower printed circuit boards
US5444296Nov 22, 1993Aug 22, 1995Sun Microsystems, Inc.Ball grid array packages for high speed applications
US5468999May 26, 1994Nov 21, 1995Motorola, Inc.Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
US5474957Apr 28, 1995Dec 12, 1995Nec CorporationProcess of mounting tape automated bonded semiconductor chip on printed circuit board through bumps
US5517125 *Jul 9, 1993May 14, 1996Aehr Test Systems, Inc.Reusable die carrier for burn-in and burn-in process
US5562971Apr 7, 1995Oct 8, 1996Hitachi Chemical Company, Ltd.Multilayer printed wiring board
US5633530Oct 24, 1995May 27, 1997United Microelectronics CorporationMultichip module having a multi-level configuration
US5646828Aug 20, 1996Jul 8, 1997Lucent Technologies Inc.Thin packaging of multi-chip modules with enhanced thermal/power management
US5674785Nov 27, 1995Oct 7, 1997Micron Technology, Inc.Forming wire electroconnection between the patterned pads and patterned conductor through the opening; materials handling; packaging
US5677566May 8, 1995Oct 14, 1997Micron Technology, Inc.Semiconductor chip package
US5689091Sep 19, 1996Nov 18, 1997Vlsi Technology, Inc.Multi-layer substrate structure
US5696033Aug 16, 1995Dec 9, 1997Micron Technology, Inc.Method for packaging a semiconductor die
US5723900Feb 12, 1997Mar 3, 1998Sony CorporationResin mold type semiconductor device
US5739585Jul 29, 1996Apr 14, 1998Micron Technology, Inc.Single piece package for semiconductor die
US5753857Jan 17, 1997May 19, 1998Lg Semicon Co., Ltd.Charge coupled device (CCD) semiconductor chip package
US5763939Sep 18, 1995Jun 9, 1998Nec CorporationSemiconductor device having a perforated base film sheet
US5789803Apr 15, 1997Aug 4, 1998Micron Technology, Inc.Semiconductor package
US5796038Jun 16, 1997Aug 18, 1998Vlsi Technology, Inc.Technique to produce cavity-up HBGA packages
US5811579Nov 17, 1995Sep 22, 1998Eastman Kodak CompanyMethod of synthesizing a 2-substituted nitrogen-containing compound
US6013948Apr 1, 1998Jan 11, 2000Micron Technology, Inc.Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6020629Jun 5, 1998Feb 1, 2000Micron Technology, Inc.Stacked semiconductor package and method of fabrication
US6072323Mar 3, 1997Jun 6, 2000Micron Technology, Inc.Temporary package, and method system for testing semiconductor dice having backside electrodes
US6094058Oct 14, 1997Jul 25, 2000Micron Technology, Inc.Temporary semiconductor package having dense array external contacts
US6097087Oct 31, 1997Aug 1, 2000Micron Technology, Inc.Semiconductor package including flex circuit, interconnects and dense array external contacts
US6107109Dec 18, 1997Aug 22, 2000Micron Technology, Inc.Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate
US6235554May 24, 1999May 22, 2001Micron Technology, Inc.Method for fabricating stackable chip scale semiconductor package
US6271056Mar 1, 1999Aug 7, 2001Micron Technology, Inc.Stacked semiconductor package and method of fabrication
US6294837Aug 30, 1999Sep 25, 2001Micron Technology, Inc.Semiconductor interconnect having laser machined contacts
US6303981Sep 1, 1999Oct 16, 2001Micron Technology, Inc.Semiconductor package having stacked dice and leadframes and method of fabrication
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6582992Aug 15, 2002Jun 24, 2003Micron Technology, Inc.Stackable semiconductor package and wafer level fabrication method
US6611052Nov 16, 2001Aug 26, 2003Micron Technology, Inc.Wafer level stackable semiconductor package
US6614104Oct 4, 2002Sep 2, 2003Micron Technology, Inc.Stackable semiconductor package having conductive layer and insulating layers
US6620731Jan 4, 2002Sep 16, 2003Micron Technology, Inc.Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6686222 *May 17, 2002Feb 3, 2004Kabushiki Kaisha ToshibaStacked semiconductor device manufacturing method
US6740964 *Aug 31, 2001May 25, 2004Oki Electric Industry Co., Ltd.Semiconductor package for three-dimensional mounting, fabrication method thereof, and semiconductor device
US6784525Oct 29, 2002Aug 31, 2004Micron Technology, Inc.Semiconductor component having multi layered leadframe
US6784544Jun 25, 2002Aug 31, 2004Micron Technology, Inc.Semiconductor component having conductors with wire bondable metalization layers
US6791168Jul 10, 2002Sep 14, 2004Micron Technology, Inc.Semiconductor package with circuit side polymer layer and wafer level fabrication method
US6833613Sep 25, 2001Dec 21, 2004Micron Technology, Inc.Stacked semiconductor package having laser machined contacts
US6835599Dec 18, 2003Dec 28, 2004Micron Technology, Inc.Method for fabricating semiconductor component with multi layered leadframe
US6841883Mar 31, 2003Jan 11, 2005Micron Technology, Inc.Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6847109 *Apr 4, 2003Jan 25, 2005Samsung Electronics Co., Ltd.Area array semiconductor package and 3-dimensional stack thereof
US6853064May 12, 2003Feb 8, 2005Micron Technology, Inc.Semiconductor component having stacked, encapsulated dice
US6887787Jul 10, 2003May 3, 2005Micron Technology, Inc.Method for fabricating semiconductor components with conductors having wire bondable metalization layers
US6903443Dec 11, 2002Jun 7, 2005Micron Technology, Inc.Semiconductor component and interconnect having conductive members and contacts on opposing sides
US6903449 *Aug 1, 2003Jun 7, 2005Micron Technology, Inc.Semiconductor component having chip on board leadframe
US6946325 *Aug 28, 2003Sep 20, 2005Micron Technology, Inc.Methods for packaging microelectronic devices
US6949834Mar 4, 2004Sep 27, 2005Micron Technology, Inc.Stacked semiconductor package with circuit side polymer layer
US6952054Apr 8, 2004Oct 4, 2005Micron Technology, Inc.Semiconductor package having interconnect with conductive members
US6972214Nov 29, 2004Dec 6, 2005Micron Technology, Inc.Method for fabricating a semiconductor package with multi layered leadframe
US6979904Apr 19, 2002Dec 27, 2005Micron Technology, Inc.Integrated circuit package having reduced interconnects
US6995041 *Apr 30, 2003Feb 7, 2006Micron Technology, Inc.Semiconductor package with circuit side polymer layer and wafer level fabrication method
US6998344Mar 31, 2004Feb 14, 2006Micron Technology, Inc.Method for fabricating semiconductor components by forming conductive members using solder
US6998717Oct 11, 2004Feb 14, 2006Micron Technology, Inc.Multi-dice chip scale semiconductor components
US7008822Aug 27, 2003Mar 7, 2006Micron Technology, Inc.Method for fabricating semiconductor component having stacked, encapsulated dice
US7029953Feb 4, 2004Apr 18, 2006Oki Electric Industry Co., Ltd.Semiconductor package for three-dimensional mounting, fabrication method thereof, and semiconductor device
US7049173 *Mar 10, 2004May 23, 2006Micron Technology, Inc.Method for fabricating semiconductor component with chip on board leadframe
US7060526Dec 8, 2003Jun 13, 2006Micron Technology, Inc.Wafer level methods for fabricating multi-dice chip scale semiconductor components
US7109576Jun 4, 2004Sep 19, 2006Micron Technology, Inc.Semiconductor component having encapsulated die stack
US7132750Aug 23, 2004Nov 7, 2006Micron Technology, Inc.Semiconductor component having conductors with wire bondable metalization layers
US7145228Jul 21, 2005Dec 5, 2006Micron Technology, Inc.Microelectronic devices
US7148576 *Jun 13, 2005Dec 12, 2006Renesas Technology Corp.Semiconductor device and method of fabricating the same
US7157353Jun 7, 2005Jan 2, 2007Micron Technology, Inc.Method for fabricating encapsulated semiconductor components
US7180165 *Sep 5, 2003Feb 20, 2007Sanmina, Sci CorporationStackable electronic assembly
US7220507 *Jun 6, 2004May 22, 2007Antig Technology Co., Ltd.Flat panel direct methanol fuel cell and method of making the same
US7221059Feb 7, 2005May 22, 2007Micron Technology, Inc.Wafer level semiconductor component having thinned, encapsulated dice and polymer dam
US7224051Jan 17, 2006May 29, 2007Micron Technology, Inc.Semiconductor component having plate and stacked dice
US7227252Aug 17, 2005Jun 5, 2007Micron Technology, Inc.Semiconductor component having stacked, encapsulated dice and method of fabrication
US7262080 *May 21, 2004Aug 28, 2007Samsung Electronics Co., Ltd.BGA package with stacked semiconductor chips and method of manufacturing the same
US7276784 *Oct 11, 2005Oct 2, 2007Kabushiki Kaisha ToshibaSemiconductor device and a method of assembling a semiconductor device
US7279797Jan 3, 2005Oct 9, 2007Micron Technology, Inc.Module assembly and method for stacked BGA packages
US7282804 *Feb 5, 2004Oct 16, 2007Megica CorporationStructure of high performance combo chip and processing method
US7307348Dec 7, 2005Dec 11, 2007Micron Technology, Inc.Semiconductor components having through wire interconnects (TWI)
US7371676Apr 8, 2005May 13, 2008Micron Technology, Inc.Method for fabricating semiconductor components with through wire interconnects
US7382060Feb 7, 2005Jun 3, 2008Micron Technology, Inc.Semiconductor component having thinned die, polymer layers, contacts on opposing sides, and conductive vias connecting the contacts
US7393770May 19, 2005Jul 1, 2008Micron Technology, Inc.Backside method for fabricating semiconductor components with conductive interconnects
US7396702Oct 31, 2005Jul 8, 2008Micron Technology, Inc.Module assembly and method for stacked BGA packages
US7400032 *Oct 31, 2005Jul 15, 2008Micron Technology, Inc.Module assembly for stacked BGA packages
US7408255Oct 31, 2005Aug 5, 2008Micron Technology, Inc.Assembly for stacked BGA packages
US7417325Jan 20, 2006Aug 26, 2008Micron Technology, Inc.Semiconductor component having thinned die with conductive vias configured as conductive pin terminal contacts
US7432604 *Aug 15, 2005Oct 7, 2008Micron Technology, Inc.Semiconductor component and system having thinned, encapsulated dice
US7446404Dec 26, 2006Nov 4, 2008Advanced Semiconductor Engineering, Inc.Three-dimensional package and method of making the same
US7459393Aug 2, 2006Dec 2, 2008Micron Technology, Inc.Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts
US7459778Mar 27, 2006Dec 2, 2008Micron Technology, Inc.Chip on board leadframe for semiconductor components having area array
US7479413Oct 3, 2005Jan 20, 2009Micron Technology, Inc.Method for fabricating semiconductor package with circuit side polymer layer
US7482702Mar 27, 2006Jan 27, 2009Micron Technology, Inc.Semiconductor component sealed on five sides by polymer sealing layer
US7498675Feb 2, 2007Mar 3, 2009Micron Technology, Inc.Semiconductor component having plate, stacked dice and conductive vias
US7528053Dec 26, 2006May 5, 2009Advanced Semiconductor Engineering, Inc.Three-dimensional package and method of making the same
US7528475Nov 22, 2006May 5, 2009Samsung Electronics, Co., Ltd.BGA package with stacked semiconductor chips and method of manufacturing the same
US7537966Aug 28, 2006May 26, 2009Micron Technology, Inc.Method for fabricating board on chip (BOC) semiconductor package with circuit side polymer layer
US7550832Dec 12, 2006Jun 23, 2009Advanced Semiconductor Engineering, Inc.Stackable semiconductor package
US7589408Dec 12, 2006Sep 15, 2009Advanced Semiconductor Engineering, Inc.Stackable semiconductor package
US7659612Apr 24, 2006Feb 9, 2010Micron Technology, Inc.Semiconductor components having encapsulated through wire interconnects (TWI)
US7674652Sep 1, 2005Mar 9, 2010Micron Technology, Inc.Methods of forming an integrated circuit package
US7682962May 2, 2007Mar 23, 2010Micron Technology, Inc.Method for fabricating stacked semiconductor components with through wire interconnects
US7727872May 9, 2008Jun 1, 2010Micron Technology, Inc.Methods for fabricating semiconductor components with conductive interconnects
US7728443May 2, 2007Jun 1, 2010Micron Technology, Inc.Semiconductor components with through wire interconnects
US7741152Dec 26, 2006Jun 22, 2010Advanced Semiconductor Engineering, Inc.Three-dimensional package and method of making the same
US7754531Nov 15, 2006Jul 13, 2010Micron Technology, Inc.Method for packaging microelectronic devices
US7757385May 3, 2007Jul 20, 2010Micron Technology, Inc.System for fabricating semiconductor components with through wire interconnects
US7768096May 3, 2008Aug 3, 2010Micron Technology, Inc.System for fabricating semiconductor components with conductive interconnects
US7776647Jul 31, 2006Aug 17, 2010Micron Technology, Inc.Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors
US7786605Sep 23, 2007Aug 31, 2010Micron Technology, Inc.Stacked semiconductor components with through wire interconnects (TWI)
US7863100Mar 20, 2009Jan 4, 2011Stats Chippac Ltd.Integrated circuit packaging system with layered packaging and method of manufacture thereof
US7883908Oct 19, 2009Feb 8, 2011Micron Technology, Inc.Method for fabricating semiconductor component having encapsulated through wire interconnect (TWI)
US7919846Feb 10, 2010Apr 5, 2011Micron Technology, Inc.Stacked semiconductor component having through wire interconnect
US7919873Nov 12, 2008Apr 5, 2011Megica CorporationStructure of high performance combo chip and processing method
US7935991May 3, 2008May 3, 2011Micron Technology, Inc.Semiconductor components with conductive interconnects
US7951702Feb 10, 2010May 31, 2011Micron Technology, Inc.Methods for fabricating semiconductor components with conductive interconnects having planar surfaces
US7960212Aug 22, 2007Jun 14, 2011Megica CorporationStructure of high performance combo chip and processing method
US7960842Nov 12, 2008Jun 14, 2011Megica CorporationStructure of high performance combo chip and processing method
US8004848 *May 23, 2008Aug 23, 2011Samsung Electronics Co., Ltd.Stack module, card including the stack module, and system including the stack module
US8012797Aug 25, 2009Sep 6, 2011Advanced Semiconductor Engineering, Inc.Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
US8053909Jan 17, 2011Nov 8, 2011Micron Technology, Inc.Semiconductor component having through wire interconnect with compressed bump
US8076765Jul 22, 2009Dec 13, 2011Advanced Semiconductor Engineering, Inc.Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors
US8093703 *Apr 16, 2008Jan 10, 2012Samsung Electronics Co., Ltd.Semiconductor package having buried post in encapsulant and method of manufacturing the same
US8115269Feb 22, 2010Feb 14, 2012Round Rock Research, LlcIntegrated circuit package having reduced interconnects
US8120167Oct 14, 2010Feb 21, 2012Micron Technology, Inc.System with semiconductor components having encapsulated through wire interconnects (TWI)
US8124446Aug 22, 2007Feb 28, 2012Megica CorporationStructure of high performance combo chip and processing method
US8143101Mar 21, 2008Mar 27, 2012Advanced Semiconductor Engineering, Inc.Semiconductor package and the method of making the same
US8158888Jun 23, 2009Apr 17, 2012Advanced Semiconductor Engineering, Inc.Circuit substrate and method of fabricating the same and chip package structure
US8189342 *Aug 9, 2006May 29, 2012Samsung Electronics Co., Ltd.Printed circuit board for memory module, method of manufacturing the same and memory module/socket assembly
US8193646Jun 28, 2010Jun 5, 2012Micron Technology, Inc.Semiconductor component having through wire interconnect (TWI) with compressed wire
US8198131Jul 29, 2010Jun 12, 2012Advanced Semiconductor Engineering, Inc.Stackable semiconductor device packages
US8217510Oct 31, 2011Jul 10, 2012Micron Technology, Inc.Semiconductor module system having stacked components with encapsulated through wire interconnects (TWI)
US8278746Apr 2, 2010Oct 2, 2012Advanced Semiconductor Engineering, Inc.Semiconductor device packages including connecting elements
US8299592 *Jun 23, 2009Oct 30, 2012Hynix Semiconductor Inc.Cube semiconductor package composed of a plurality of stacked together and interconnected semiconductor chip modules
US8404523Jun 27, 2012Mar 26, 2013Micron Technoloy, Inc.Method for fabricating stacked semiconductor system with encapsulated through wire interconnects (TWI)
US8405212Jun 18, 2010Mar 26, 2013Advanced Semiconductor Engineering, Inc.Semiconductor package
US8513797May 25, 2012Aug 20, 2013Micron Technology, Inc.Stacked semiconductor component having through wire interconnect (TWI) with compressed wire
US8546931Mar 31, 2011Oct 1, 2013Micron Technology, Inc.Stacked semiconductor components having conductive interconnects
US8569885Sep 27, 2011Oct 29, 2013Advanced Semiconductor Engineering, Inc.Stacked semiconductor packages and related methods
US8581387Feb 20, 2013Nov 12, 2013Micron Technology, Inc.Through wire interconnect (TWI) having bonded connection and encapsulating polymer layer
US8624374Apr 2, 2010Jan 7, 2014Advanced Semiconductor Engineering, Inc.Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8643167Dec 5, 2011Feb 4, 2014Advanced Semiconductor Engineering, Inc.Semiconductor package with through silicon vias and method for making the same
US8741667Oct 10, 2013Jun 3, 2014Micron Technology, Inc.Method for fabricating a through wire interconnect (TWI) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer
US20120018879 *Dec 29, 2010Jan 26, 2012Hynix Semiconductor Inc.Stack package and method for manufacturing the same
USRE42363 *Feb 15, 2010May 17, 2011Sanmina-Sci CorporationStackable electronic assembly
Legal Events
DateCodeEventDescription
Feb 19, 2014FPAYFee payment
Year of fee payment: 12
Mar 3, 2010FPAYFee payment
Year of fee payment: 8
Feb 17, 2006FPAYFee payment
Year of fee payment: 4
Dec 10, 2002CCCertificate of correction
Aug 7, 2001ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FARNWORTH, WARREN M.;WOOD, ALAN G.;BROOKS, MIKE;REEL/FRAME:012061/0038;SIGNING DATES FROM 20010713 TO 20010720
Owner name: MICRON TECHNOLOGY, INC. 8000 SOUTH FEDERAL WAY BOI
Owner name: MICRON TECHNOLOGY, INC. 8000 SOUTH FEDERAL WAYBOIS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FARNWORTH, WARREN M. /AR;REEL/FRAME:012061/0038;SIGNING DATES FROM 20010713 TO 20010720