Publication number | US6452524 B1 |

Publication type | Grant |

Application number | US 09/779,234 |

Publication date | Sep 17, 2002 |

Filing date | Feb 8, 2001 |

Priority date | Feb 8, 2001 |

Fee status | Paid |

Also published as | EP1374415A2, US20020130800, WO2002063777A2, WO2002063777A3 |

Publication number | 09779234, 779234, US 6452524 B1, US 6452524B1, US-B1-6452524, US6452524 B1, US6452524B1 |

Inventors | Stephen Fraleigh, Douglas A. Cairns |

Original Assignee | Ericsson Inc. |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (8), Referenced by (21), Classifications (5), Legal Events (4) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 6452524 B1

Abstract

A delta-sigma converter including a multiplier. The delta-sigma converter includes a feed-forward path and a feedback path providing a feedback signal. The converter output signal is multiplied in the feedback path by a mapping function, and the multiplied signal is mapped to a digital feedback signal having the same number of bits as the input signal. There is also provided a digital-to-analog converter including a delta-sigma converter consistent with the invention, and a method of multiplying a digital signal.

Claims(28)

1. A delta-sigma converter comprising:

a feed-forward path for receiving a feed-forward signal and providing an output signal; and

a feedback path comprising a multiplying mapping function,

said mapping function being configured to multiply said output signal based on at least one multiplication factor and provide an N_{FB}-bit feedback signal representative of said multiplied output signal, said feedback signal being combined with an N-bit input signal to provide said feed-forward signal.

2. A delta-sigma converter according to claim 1 , wherein said mapping function is configured to provide said feedback signal in accordance with: ${y}_{\mathrm{FB}}\ue8a0\left[n\right]=\left\{\begin{array}{cc}\frac{{2}^{N-1}}{\alpha}& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e{y}_{q}\ue8a0\left[n\right]=1\\ \frac{-{2}^{N-1}}{\alpha}& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e{y}_{q}\ue8a0\left[n\right]=0\end{array}\right\}\ue89e\text{\hspace{1em}}$

where y_{FB}[n] is a value of said feedback signal at a discrete time n, y_{q}[n] is a value of said output signal at said discrete time n, and a is said at least one multiplication factor.

3. A delta-sigma converter according to claim 2 , wherein 0<α≦1.

4. A delta-sigma converter according to claim 1 , wherein said at least one multiplication factor is a programmable value.

5. A delta-sigma converter according to claim 1 , wherein said output signal is a single-bit output signal.

6. A delta-sigma converter according to claim 1 , wherein said feed-forward path comprises a low pass filter and a quantizer, said low pass filter for receiving said feed-forward signal and having an output coupled to an input of said quantizer, said quantizer being configured to provide said output signal.

7. A delta-sigma converter according to claim 6 , wherein said low pass filter comprises an integrator.

8. A delta-sigma converter comprising:

a feed-forward path comprising a low pass filter for receiving a feed-forward signal and a quantizer coupled to an output of said low pass filter, said quantizer being configured to provide an output signal; and

a feedback path comprising a multiplying mapping function, said mapping function being configured to provide an N_{FB}-bit feedback signal in accordance with: ${y}_{\mathrm{FB}}\ue8a0\left[n\right]=\left\{\begin{array}{cc}\frac{{2}^{N-1}}{\alpha}& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e{y}_{q}\ue8a0\left[n\right]=1\\ \frac{-{2}^{N-1}}{\alpha}& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e{y}_{q}\ue8a0\left[n\right]=0\end{array}\right\}\ue89e\text{\hspace{1em}}$

where y_{FB}[n] is a value of said N_{FB}-bit feedback signal at a discrete time n, y_{q}[n] is a value of said output signal at said discrete time n, and α is a multiplication factor, said feedback signal being combined with an N-bit input signal to provide said feed-forward signal.

9. A delta-sigma converter according to claim 8 , wherein 0<α≦1.

10. A delta-sigma converter according to claim 8 , wherein said multiplication factor is a programmable value.

11. A delta-sigma converter according to claim 8 , wherein said output signal is a single-bit output signal.

12. A delta-sigma converter according to claim 8 , wherein said low pass filter comprises an integrator.

13. A digital-to-analog converter comprising

a delta-sigma converter configured to provide a digital output signal representative of an N-bit digital input signal multiplied based on at least one multiplication factor; and

a digital to analog converter for providing an analog output signal representative of said digital output signal.

14. A digital-to-analog converter according to claim 13 , wherein said delta-sigma converter comprises:

a feed-forward path for receiving a feed-forward signal and providing said digital output signal; and

a feedback path comprising a multiplying mapping function,

said mapping function being configured to multiply said digital output signal based on said at least one multiplication factor and provide an N_{FB}-bit feedback signal representative of said multiplied output signal, said feedback signal being combined with said N-bit digital input signal to provide said feed-forward signal.

15. A digital-to-analog converter according to claim 14 , wherein said mapping function is configured to provide said feedback signal in accordance with: ${y}_{\mathrm{FB}}\ue8a0\left[n\right]=\left\{\begin{array}{cc}\frac{{2}^{N-1}}{\alpha}& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e{y}_{q}\ue8a0\left[n\right]=1\\ \frac{-{2}^{N-1}}{\alpha}& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e{y}_{q}\ue8a0\left[n\right]=0\end{array}\right\}\ue89e\text{\hspace{1em}}$

where y_{FB}[n] is a value of said N_{FB}-bit feedback signal at a discrete time n, y_{q}[n] is a value of said output signal at said discrete time n, and α is said at least one multiplication factor.

16. A digital-to-analog converter according to claim 15 , wherein 0<α≦1.

17. A digital-to-analog converter according to claim 14 , wherein said at least one multiplication factor is a programmable value.

18. A digital-to-analog converter according to claim 14 , wherein said feed-forward path comprises a low pass filter and a quantizer, said low pass filter for receiving said feed-forward signal and having an output coupled to an input of said quantizer, said quantizer being configured to provide said output signal.

19. A digital-to-analog converter according to claim 18 , wherein said low pass filter comprises an integrator.

20. A digital-to-analog converter according to claim 13 , wherein said digital output signal is a single-bit output signal.

21. A digital-to-analog converter according to claim 13 , said converter further comprising a low pass filter for receiving said output signal and providing a filtered output signal.

22. A method of multiplying an N-bit digital signal comprising:

coupling said digital signal to a delta sigma converter, said delta-sigma converter comprising a feed-forward path for receiving a feed-forward signal and providing an output signal, and a feedback path comprising a multiplying mapping function, said mapping function being configured to multiply said output signal based on at least one multiplication factor and provide an N_{FB}-bit feedback signal representative of said multiplied output signal, said feedback signal being combined with said digital signal to provide said feed-forward signal.

23. A method according to claim 22 , wherein said mapping function is configured to provide said feedback signal in accordance with: ${y}_{\mathrm{FB}}\ue8a0\left[n\right]=\left\{\begin{array}{cc}\frac{{2}^{N-1}}{\alpha}& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e{y}_{q}\ue8a0\left[n\right]=1\\ \frac{-{2}^{N-1}}{\alpha}& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e{y}_{q}\ue8a0\left[n\right]=0\end{array}\right\}\ue89e\text{\hspace{1em}}$

where y_{FB}[n] is a value of said N_{FB}-bit feedback signal at a discrete time n, y_{q}[n] is a value of said output signal at said discrete time n, and α is said at least one multiplication factor.

24. A method according to claim 23 , wherein 0<α≦1.

25. A method according to claim 22 , wherein said output signal is a single-bit output signal.

26. A method according to claim 22 , wherein said at least one multiplication factor is a programmable value.

27. A method according to claim 22 , wherein said feed-forward path comprises a low pass filter and a quantizer, said low pass filter for receiving said feed-forward signal and having an output coupled to an input of said quantizer, said quantizer being configured to provide said output signal.

28. A method according to claim 27 , wherein said low pass filter comprises an integrator.

Description

The present invention relates to digital-to-analog converters, and, more particularly, to a delta-sigma digital-to-analog converter incorporating a multiplication function.

Digital-to-analog (D/A) and analog-to-digital (A/D) converters are widely used for converting electrical signals between digital and analog formats. Communication systems, for example, typically require extensive D/A and A/D conversion for performing a variety of signal processing functions. These converters may be implemented on an integrated circuit, such as an application specific integrated circuit (ASIC).

In an ASIC implementation, a converter may be combined with several other signal processing functions for performing the desired ASIC function. One common function implemented on such an ASIC is a multiplier function. There are several known techniques for providing a multiplier on an ASIC. While implementation of a multiplier is well understood and standard multiplier fabrication methods exist, the multiplier typically requires a relatively large area of the semiconductor chip on which the ASIC is formed. As a result, the multiplier typically consumes a significant amount of power.

A delta-sigma converter consistent with the invention includes a feed-forward path for receiving a feed-forward signal and providing an output signal; and a feedback path comprising a multiplying mapping function. The mapping function is configured to multiply the output signal based on at least one multiplication factor and to provide a feedback signal representative of the multiplied output signal. The feedback signal is combined with an input signal to provide the feed-forward signal. A method of multiplying a digital signal consistent with the invention includes coupling the digital signal as the input signal to a delta-sigma converter consistent with the invention.

A digital-to-analog converter consistent with the invention includes a delta-sigma converter configured to provide a digital output signal representative of an N-bit digital input signal multiplied based on at least one multiplication factor; and a digital to analog converter for providing an analog output signal representative of the digital output signal.

Advantages of the present invention will be apparent from the following detailed description of exemplary embodiments thereof, which description should be considered in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates an exemplary digital-to-analog converter consistent with the invention;

FIG. 2 illustrates an exemplary delta-sigma converter consistent with the invention; and

FIG. 3 illustrates a sampled-data equivalent circuit for an exemplary delta-sigma converter consistent with the invention.

With reference now to FIG. 1, there is illustrated an exemplary digital-to-analog converter **100** consistent with the invention. Those skilled in the art will recognize that a converter consistent with the invention may be incorporated into a variety of systems for achieving D/A conversion. A converter consistent with the invention may, for example, be provided in transmitters and receivers for a communication network, including wire-based and cellular or wireless networks using air interfaces, such as GSM, TDMA, CDMA or FDMA.

As shown, a D/A converter **100** consistent with the invention may include: a linear system **102** for receiving a multi-bit input signal x, i.e. a stream of digital words having a word length N; a multiplying delta-sigma converter **104** for receiving the output x_{a }of the linear system; a digital-to-analog converter (DAC) **106** for receiving the output y_{q }of the delta-sigma converter; and a low- pass filter **108** for receiving the output y_{d }of the DAC. With the exception of the multiplying delta-sigma converter, the illustrated converter **100** includes elements conventionally provided in a delta-sigma-type D/A converter. A variety of configurations for the linear system **102**, the DAC **106**, and the low pass filter **108** will, therefore, be known to those skilled in the art.

The linear system **102** may, for example, be a conventional interpolator for changing the data rate of the incoming digital signal x and suppressing spectral replicas of the data in the frequency domain. In a case where an interpolator is not required, however, the linear system may simply comprise a direct connection of the digital input to the multiplying delta-sigma converter. In a known manner, a feed-forward path of the delta-sigma converter shortens the input word length, e.g. to a single bit, such that the quantization noise introduced by this process is outside of the signal baseband. As will be described in greater detail below, the delta-sigma converter is also configured to multiply the digital signal, thereby eliminating the need for a separate dedicated multiplier circuit.

The DAC **106**, typically a one-bit DAC, may be of conventional construction and coupled to the output of the delta-sigma converter **104**. The output y_{d }of the DAC **106** is an analog representation of the digital input signal y_{q}, including an amount of noise resulting from quantization error introduced by the delta-sigma converter. The noise may be significantly suppressed by the conventional low-pass filter **108** to provide an analog output y.

Turning now to FIG. 2, there is illustrated a block diagram of an exemplary multiplying delta-sigma converter **200** consistent with the invention. In general, the converter **200** incorporates a multiplying mapping function in the feedback path of a known delta-sigma converter configuration. For simplicity and ease of explanation, the present invention will be described herein in connection with a first-order delta-sigma converter configuration. It is to be understood, however, that the present invention is equally applicable to higher order delta sigma converters. Those skilled in the art will also recognize that the present invention is applicable to multi-bit, as well as single-bit, delta sigma converters.

In the illustrated exemplary embodiment, the converter **200** has a feed-forward path including a low pass filter **202** and a quantizer **204**, and a feedback path including a multiplying digital-to-digital mapping function (MDDMF) **206**. The low pass filter **202** may be provided in a variety of known configurations, and is typically an integrator. The output of the low-pass filter **202** is provided to the quantizer **204**, which also has a known configuration. The quantizer is typically a two-level quantizer, but may be a multi-level quantizer. The quantized output y_{q }is provided as the converter output and is fed back to the MDDMF **206**.

In a manner to be described in more detail below, the MDDMF **206** is configured to map the quantized output, typically one bit, to a full-scale digital signal y_{FB }representing the value of the quantized output. The signal y_{FB }may have a word size, N_{FB}, of at least the same number of bits, N, as the input signal x_{a}. The MDDMF **206** also multiplies the quantized output based on a predetermined multiplication factor. The feedback signal y_{FB }is combined with the input signal x_{a}. This feedback through the MDDMF **206** forces the average value of the quantized output y_{q }to track the average value of the input signal x_{a }multiplied by the predetermined multiplication factor.

The operation of the MDDMF will be described in greater detail in connection with FIG. 3, which illustrates the sampled-data equivalent circuit for an ASIC implementation of an exemplary delta-sigma converter **300** consistent with the invention. As shown, the feed-forward section of the converter includes a discrete time integrator **302** and a quantizer **304** that introduces quantization error e[n]. The integrator **302** and the quantizer **304** function in a known manner.

In the illustrated embodiment, the MDDMF **306** maps the quantizer output y_{q }to a full-scale digital feedback signal y_{FB}[n] having the same number of bits as the input, e.g. a one bit quantizer output y_{q }may be mapped to a 12-bit feedback value y_{FB}[n]. The MDDMF **306** also multiplies the quantizer output y_{q }based on a predefined multiplication factor α. Consistent with the present invention, the MDDMF **306** may be implemented as a lookup table indexed by the quantizer output y_{q}[n]. For example, in an exemplary embodiment y_{FB}[n] may be expressed as:

where y_{FB}[n] is the N_{FB}-bit feedback value at a discrete time n, y_{q}[n] is the quantizer output, and α is the desired multiplication factor. A delta sigma converter consistent with the invention may thus be implemented for effecting both a D/A conversion and a digital multiplication through use of an appropriate MDDMF in the converter feedback path.

The multiplication factor a may be a single static value. It is to be understood, however, that a converter consistent with the invention may be configured to implement multiple and/or programmable values for α. In the case of programmable values, the mapping circuit may be configured to receive an input from an a selector **308** for defining one or more values for α. The selector may be integral with an IC on which the converter is implemented or may comprise an external connection. Those skilled in the art will recognize that a variety of configurations may be provided to manage multiple static or programmable a values. For example, lookup tables may be constructed for α_{0}, α_{1}, . . . α_{n }and concatenated to form one large lookup table.

Those skilled in the art will also recognize that delta-sigma converters may produce artifacts if overdriven, i.e. if x[n]>y_{FB}[n]. In the illustrated exemplary embodiment, to avoid such artifacts a may be selected such that 0<α≦1. For all values of α<1, the number of bits N_{FB }will exceed N. The summing junction, the feedback path and the internal feed-forward paths should be configured to accommodate the worst case of the digital feedback word size.

The embodiments that have been described herein, however, are but some of the several which utilize this invention and are set forth here by way of illustration but not of limitation. It is obvious that many other embodiments, which will be readily apparent to those skilled in the art, may be made without departing materially from the spirit and scope of the invention.

Patent Citations

Cited Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US4086539 * | Aug 11, 1972 | Apr 25, 1978 | Massachusetts Institute Of Technology | First-order phase-lock loop |

US4562437 * | Dec 27, 1982 | Dec 31, 1985 | Fujitsu Limited | Digital loop filter |

US5087914 | Aug 22, 1990 | Feb 11, 1992 | Crystal Semiconductor Corp. | DC calibration system for a digital-to-analog converter |

US5187482 * | Mar 2, 1992 | Feb 16, 1993 | General Electric Company | Delta sigma analog-to-digital converter with increased dynamic range |

US5276764 | Jun 12, 1991 | Jan 4, 1994 | Ericsson-Ge Mobile Communications Holding Inc. | Method and device for compressing and expanding an analog signal |

US5583501 | Aug 24, 1994 | Dec 10, 1996 | Crystal Semiconductor Corporation | Digital-to-analog converter with digital linearity correction |

US5727023 | Sep 14, 1993 | Mar 10, 1998 | Ericsson Inc. | Apparatus for and method of speech digitizing |

US6313775 * | Aug 31, 2000 | Nov 6, 2001 | Nokia Mobile Phones Limited | Delta-sigma modulator with two-step quantization, and method for using two-step quantization in delta-sigma modulation |

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US7425910 * | Sep 25, 2006 | Sep 16, 2008 | Marvell International Ltd. | Transmitter digital-to-analog converter with noise shaping |

US7436337 * | Dec 8, 2006 | Oct 14, 2008 | Marvell International Ltd. | Transmitter digital-to-analog converter with noise shaping |

US7471225 * | Dec 8, 2006 | Dec 30, 2008 | Marvell International Ltd. | Transmitter digital-to-analog converter with noise shaping |

US7592939 * | May 9, 2008 | Sep 22, 2009 | Hrl Laboratories, Llc | Digital domain to pulse domain time encoder |

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US7750835 | Nov 6, 2008 | Jul 6, 2010 | Hrl Laboratories, Llc | Analog to digital converter using asynchronous pulse technology |

US7773017 | Aug 10, 2010 | Marvell International Ltd. | Transmitter digital-to-analog converter with noise shaping | |

US7822698 | Mar 23, 2007 | Oct 26, 2010 | Hrl Laboratories, Llc | Spike domain and pulse domain non-linear processors |

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US7996452 | Nov 10, 2006 | Aug 9, 2011 | Hrl Laboratories, Llc | Pulse domain hadamard gates |

US7999711 | Jul 28, 2010 | Aug 16, 2011 | Marvell International Ltd. | Transmitter digital-to-analog converter with noise shaping |

US8174425 | Jun 14, 2010 | May 8, 2012 | Hrl Laboratories, Llc | Asynchronous pulse processing apparatus and method providing signal normalization |

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US8566265 | Mar 10, 2011 | Oct 22, 2013 | Hrl Laboratories, Llc | Combined spike domain and pulse domain signal processing |

US8595157 | Jun 2, 2011 | Nov 26, 2013 | Hrl Laboratories, Llc | High-order time encoder based neuron circuit using a hysteresis quantizer, a one bit DAC, and a second order filter |

US8773295 * | Mar 22, 2011 | Jul 8, 2014 | Japan Science And Technology Agency | Data conversion method based on scale-adjusted B-map |

US9082075 | Sep 19, 2013 | Jul 14, 2015 | Hrl Laboratories, Llc | Combined spike domain and pulse domain signal processing |

US9154172 | Dec 31, 2013 | Oct 6, 2015 | Hrl Laboratories, Llc | Time encoded circuits and methods and a time encoder based beamformer for use in receiving and transmitting applications |

US20050068221 * | Sep 27, 2004 | Mar 31, 2005 | Freeman Steven R. | Ultrasonic signal acquisition in the digital beamformer |

US20130015992 * | Mar 22, 2011 | Jan 17, 2013 | Japan Science And Technology Agency | Data conversion method based on scale-adjusted b-map |

Classifications

U.S. Classification | 341/143, 341/155 |

International Classification | H03M7/32 |

Cooperative Classification | H03M7/3015 |

European Classification | H03M7/30B1S |

Legal Events

Date | Code | Event | Description |
---|---|---|---|

Feb 8, 2001 | AS | Assignment | Owner name: ERICSSON INC., NORTH CAROLINA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FRALEIGH, STEPHEN;CAIRNS, DOUGLAS A.;REEL/FRAME:011543/0812 Effective date: 20010207 |

Mar 17, 2006 | FPAY | Fee payment | Year of fee payment: 4 |

Mar 17, 2010 | FPAY | Fee payment | Year of fee payment: 8 |

Mar 17, 2014 | FPAY | Fee payment | Year of fee payment: 12 |

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