|Publication number||US6462570 B1|
|Application number||US 09/876,002|
|Publication date||Oct 8, 2002|
|Filing date||Jun 6, 2001|
|Priority date||Jun 6, 2001|
|Publication number||09876002, 876002, US 6462570 B1, US 6462570B1, US-B1-6462570, US6462570 B1, US6462570B1|
|Inventors||William J. Price, Drew G. Doblar|
|Original Assignee||Sun Microsystems, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (1), Referenced by (67), Classifications (19), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention relates to testing equipment for integrated circuits, and more particularly, to test breakout boards and their layout.
2. Description of the Related Art
There are many ways to test electronic circuits while the circuit is operating. One method, in particular, is to place the device-under-test (DUT) in a known good operational environment. While in operation, the DUT signals are monitored by test equipment, such as a logic analyzer or oscilloscope.
A common method of monitoring the DUT signals employs a printed circuit board (PCB) known as a breakout board. The breakout board typically includes a device socket, which allows the DUT to be inserted and removed without the need for soldering. The breakout board also provides a means for intercepting the DUT signals and routing them to a test connector. The breakout board is physically located between the DUT and the system board. Therefore, the breakout board also provides a means to connect to the system board in the same way that the DUT would connect to the system board if the breakout board were removed. This is sometimes accomplished by mounting a socket on the system board and a socket adapter on the breakout board.
The breakout board typically has connection areas called pads on the surface of the top layer for soldering a DUT test socket. The pads are typically arranged in a pattern that matches the DUT connection pattern, which is known as a footprint. This footprint is typically duplicated on the bottom PCB layer directly opposite the top layer.
The top layer pads and the bottom layer pads are typically connected together by connections called vias, which are described further below. Small wires called traces connect the pads to power, ground and each other. Since there are often more traces needed than can be manufactured on the surface layers alone, traces are placed on various internal layers. To connect the various internal layer traces to each other and to the surface layers, metal plated connections are used. These connections are called vias. Two types of vias are commonly used: Plated through-hole vias and blind vias.
Plated through-hole vias are holes drilled completely through all layers of the PCB and perpendicular to the surface. The holes are then plated with a conducting metal, such as copper or gold. Through-hole vias can therefore connect signals on any layer to any other layer. Blind vias are holes drilled from the surface through some of the internal layers and then plated with a conducting metal. Therefore, blind vias can connect signals on the surface layer to any internal layers through which it passes.
As shown in FIG. 1, on the breakout board PCB 10, through-hole vias 11 connect the top and bottom contact pads together. The signal traces 16 on various layers connect to the vias at right angles and are routed to the through-hole vias 21 below the test connector 14. The test connector 14 typically includes contact pins 15, which extend down through the through-hole vias 21, where they are soldered to the bottom surface of the PCB. Any test equipment connected to the connector may now receive the DUT signals.
This design works at some frequencies. However, as device clock and signal frequencies increase, circuit board layout becomes a more critical step in producing a fully operational system. Since the PCB traces are transmission lines, their lengths, widths and routing become significant with an increase in frequency in terms of signal quality and strength. In the breakout board design of FIG. 1, the internal layer trace connections to the vias act like transmission line stubs 30. These stubs can create an impedance mismatch at certain frequencies, which can adversely affect the signals. The signal degradation may cause incorrect test readings or complete failure of the DUT in the system during testing. Therefore, it is desirable to provide a better impedance match at the frequencies of interest.
The problem outlined above may in large part be solved by a breakout board design using blind vias to eliminates stubs on critical timing signal paths.
In one embodiment, a test breakout board comprising a printed circuit board (PCB), which may be implemented in multiple layers, includes a first set of contact pads on one side of the PCB and a second set of contact pads, which are directly opposite the first set of contact pads, on the other side of the PCB. Each pad in the first set of contact pads is connected to a corresponding pad in the second set of contact pads through a pair of blind vias, a pair of signal traces and a throughhole via. Each of the through-hole vias is connected to a corresponding contact pin in a test connector. The test connector is mounted on the top contact of the PCB and provides an interface to test equipment such as a logic analyzer or an oscilloscope. The breakout board may also include a test socket for holding a device-under-test (DUT), such as a microprocessor or an application specific integrated circuit (ASIC) chip. The integrated circuit chip is enclosed in a device package to protect the die. The test socket includes contacts, which are soldered to the first set of contact pads on the top surface of the breakout board. Additionally, the breakout board may also include an electrical interface adapter, which mechanically resembles the DUT. The interface adapter is soldered to the second set of contact pads on the bottom surface of the breakout board and provides the interface between the test breakout board and a system motherboard.
In another embodiment, a test breakout board is connected to a system motherboard. The system motherboard includes an additional test socket, which can hold a DUT, or in this case, a test breakout board electrical interface adapter. The electrical interface adapter mechanically fits into the additional test socket. The contacts on the adapter make contact with a set of metallic contacts in the socket, thereby providing a signal path from the system motherboard, through the breakout board, to the DUT. A test connector on the test breakout board allows test equipment, such as a logic analyzer or an oscilloscope, to be connected to the test breakout board.
The signal path from each of the contact pads through each blind via, through a signal trace, a through-hole via, a second signal trace and a second blind via, to each second contact pad may advantageously provide an impedance matched signal path from a system motherboard to a DUT and a test connector. Thus, the test breakout board may facilitate proper testing at high frequencies.
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:
FIG. 1 is a prior art diagram of one embodiment of a test system, including the breakout board PCB.
FIG. 2 is a diagram of one embodiment of a test system, including a test breakout board printed circuit board and a system motherboard.
FIG. 3 is an illustration of one embodiment of the top surface of a breakout board printed circuit board.
FIG. 3A is a diagram of one embodiment of a contact pad of FIG. 2.
FIG. 4 is an illustration of one embodiment of the bottom surface of a breakout board printed circuit board.
FIG. 5 is an illustration of an embodiment of a breakout board printed circuit board.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
Referring now to FIG. 2, one embodiment of a test system, including a test breakout board printed circuit board (PCB) 100 and a system motherboard PCB 500 is shown. A device socket 510 is mounted to motherboard PCB 500. Test breakout board PCB 100 includes a plurality of top contact pads 101 and a plurality of bottom contact pads 102. An additional device socket 110 is coupled to the plurality of top contact pads 101. Device socket 110 holds a device (DUT) 115 during testing. An electrical interface adapter 130 is mounted to the plurality of bottom contact pads 102. A test connector 120 is mounted to the top surface of the test breakout board PCB 100. A test apparatus, or test equipment 125 is connected to test connector 120 through a test cable 126.
During device testing, a DUT 115 is placed in socket 110. All device power, ground and signals come from motherboard PCB 500. These signals are routed up through the test breakout board PCB 100 to DUT 115. As will be shown in greater detail in FIG. 5, the device signals are routed from the bottom contact pads 102 up through a plurality of blind vias, through-hole vias, and signal traces to the top contact pads 101. The test breakout board 100 also routes DUT 115 signals to test connector 120. The signal traces may be routed on many of the test breakout board PCB 100 layers. Test equipment 125, such as a logic analyzer, is connected to test connector 120 to monitor DUT 115 signals.
Turning to FIG. 3, an illustration of one embodiment of the top surface of the test breakout board printed circuit board (PCB) 100 of FIG. 2 is shown. The top surface 150 includes a set of contact pads 101. The contact pads 101 are arranged in a pattern matching a device or device socket footprint (not shown). The contact pads 101 are typically connected to either a signal trace 152 or a via as shown in more detail in FIG. 3A. Contact pads 101 are typically void of solder mask to allow for soldering. Top surface 150 also includes a test connector footprint 160. The footprint includes a pattern of a plurality of through-hole vias 165.
In FIG. 3A, one embodiment of a contact pad 101 of FIG. 3 and contact pad 102 of FIG. 4 is shown in greater detail. A blind via 170 is electrically connected to contact pad 101, 102 and located near the center of contact pad 101, 102. Although the blind via 170 is shown near the center of contact pad 101, 102, it should be noted, that blind via 170 may be located outside of the actual contact pad area, but connected to contact pad 101,102 by a signal trace on the surface.
Referring now to FIG. 4, one embodiment of the bottom surface of the test breakout board printed circuit board (PCB) 100 of FIG. 2 is shown. The bottom surface 180 includes a set of contact pads 102. The contact pads 102 are arranged in a pattern matching a device or device socket footprint (not shown) and are located directly opposite the contact pads 101 of FIG. 3. The contact pads 102 are typically connected to either a signal trace 182 or a via as shown in more detail in FIG. 3A. Contact pads 102 are typically void of solder mask to allow for soldering. Bottom surface 180 also includes a plurality of through-hole vias 165 in the pattern of test connector footprint 160 of FIG. 3.
Turning now to FIG. 5, an embodiment of test breakout board printed circuit board (PCB) 100 of FIG. 2 is shown. Test breakout board PCB 100 includes a plurality of top contact pads 101 coupled to a plurality of blind vias 901. A plurality of bottom contact pads 102 is coupled to a plurality of blind vias 902. Test breakout board PCB 100 also includes a test connector 120, which is mounted to the top surface of breakout board PCB 100. Test connector 120 includes a plurality of contact pins 921. As an example, contact pin 921 extends down through a through-hole via 922 and may be soldered in place. In this example, a signal comes up from one of the bottom contact pads 930 and is coupled to through-hole via 922 through a blind via 901 and a signal trace 903. The signal is then routed through a signal trace 904 to a blind via 902 and up through one of the top contact pads 925.
During the device operation described in FIG. 1, the signal trace routing and use of the blind vias of FIG. 5 may advantageously improve the signal integrity of some critical timing path signals by eliminating the presence of transmission line stubs and therefore, the impedance mismatches caused by those stubs.
Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
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|U.S. Classification||324/756.02, 324/762.02|
|International Classification||H05K1/02, H05K3/42, H05K1/11, G01R31/28, H05K3/34|
|Cooperative Classification||H05K2201/09509, H05K2201/09627, G01R31/2808, H05K1/0268, G01R31/2818, H05K2203/1572, H05K1/113, H05K3/429, H05K2201/10189, H05K3/3447|
|European Classification||H05K1/11C2A, G01R31/28B6|
|Jun 6, 2001||AS||Assignment|
Owner name: SUN MICROSYSTEMS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PRICE, WILLIAM J.;DOBLAR, DREW G.;REEL/FRAME:011912/0212
Effective date: 20010605
|Oct 15, 2001||AS||Assignment|
Owner name: SUN MICROSYSTEMS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PRICE, WILLIAM J.;REEL/FRAME:012281/0093
Effective date: 20010925
|Mar 17, 2006||FPAY||Fee payment|
Year of fee payment: 4
|Mar 31, 2010||FPAY||Fee payment|
Year of fee payment: 8
|Mar 12, 2014||FPAY||Fee payment|
Year of fee payment: 12
|Dec 12, 2015||AS||Assignment|
Owner name: ORACLE AMERICA, INC., CALIFORNIA
Free format text: MERGER AND CHANGE OF NAME;ASSIGNORS:ORACLE USA, INC.;SUN MICROSYSTEMS, INC.;ORACLE AMERICA, INC.;REEL/FRAME:037278/0638
Effective date: 20100212