|Publication number||US6490559 B2|
|Application number||US 09/170,464|
|Publication date||Dec 3, 2002|
|Filing date||Oct 13, 1998|
|Priority date||Oct 10, 1997|
|Also published as||DE19744690A1, EP0908868A2, EP0908868A3, US20020007274|
|Publication number||09170464, 170464, US 6490559 B2, US 6490559B2, US-B2-6490559, US6490559 B2, US6490559B2|
|Inventors||Wolfgang O. Budde, Volker Steinbiss|
|Original Assignee||Koninklijke Philips Electronics N.V.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (1), Referenced by (5), Classifications (8), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to a speech recognition computer comprising a microprocessor, input and output interfaces and a data bus, in which incoming test signals converted into a digital form are subdivided into segments, and test vectors are assigned to properties of the segments, for which test vectors a distance with reference to reference vectors is computed.
The distance computation is used in speech recognition as a degree of similarity between a part of a speech utterance and a speech reference and represents a central, constantly recurrent task in sample and speech recognition. It requires the longest computation time so that a reduction of the computation time yields a considerable efficiency improvement. In picture processing and sample recognition, it is used for data compression (MPEG).
Up to now, additional, special hardware modules have been used for speech recognition. These modules are used for converting the incoming analog speech signals into digital signals, and for feature extraction in which the characteristic properties of the segmented incoming digitized speech signal are assigned to corresponding vector components. For the test vectors thus formed, the distance to the reference vectors is computed by means of a digital signal processor.
On the other hand, there are software-based speech recognition systems in which the recognition process is performed without any special hardware, i.e. with the system components of a universal computer. The incoming test signals are digitized on, for example, the sound card. The elaborate distance computation is performed on the main processor of the system. This presupposes the use of a very powerful processor and also requires a considerable part of its computation power which is then no longer available for other processes. Generally, the recognition of the spoken text is, however, realized in an off-line mode because a sufficiently powerful processor is not often available.
It is an object of the invention to provide a (universal) arrangement which allows a faster computation of the distances.
This object is solved in that a distance computer and a memory module are provided which are integrated on a common module having at least a data terminal for supplying test vectors and reference vectors and for providing computed distances.
This universal computer system according to the invention allows speech recognition with a conventional microprocessor and its customary peripheral equipment by combination with a memory and an integrated distance computer. The microprocessor is thereby relieved from the elaborate distance computation and its computing power is available for other processes.
To this end, analog data are applied to the computer system via the input and output interfaces, which data, after having been prepared for distance computation, are applied to the memory module with the integrated distance computer.
An additional advantage is the short communication path. Since the data to be compared are directly supplied from the relevant memories to the distance computer, no valuable computation time is lost. The system transfers the test vectors and receives the computed distances. Since the distance computation is locally performed within a memory module, all components of the system, with the exception of the relevant memory module, are available to the system processor for other processes.
Moreover, this integration does not require any data transfers via an external data or address bus for performing the distance computation, i.e. the memory accesses are limited to the internal local memory ranges so that the distance computation is performed directly and within a significantly shorter time. The reference data are loaded into the reference data memory before or at least not during a recognition process step. Also a possible update of this reference data file is performed at non-critical points of time.
A further advantage of this computer system is the possible reconstruction of a computer conceived for normal purposes. A conventional memory module is exchanged for a memory module with an integrated distance computer. This enables the computer system to perform speech recognition processes without any serious limitation of its efficiency.
The integration of a distance computer in a memory module involves further advantages of the optimized memory manufacturing process. Memory modules are produced as logic modules with a higher density of components, resulting in a more optimal utilization of space.
The effectiveness of this integration will be shown by way of an example. In a typical case, the distances of a test vector to, for example, 2000 reference vectors are required every 16 ms. Approximately a data rate of at least 3 Mbyte per second is required for this purpose. A standard signal processor with a clock frequency of 20 MHz would need approximately 12 ms for this purpose. A standard microprocessor requires much more time for this purpose. By integrating the distance computation, this task, performed at the same clock frequency, is reduced to approximately one tenth, i.e. approximately 1.2 ms. The speed gain relates to the optimized addressing, the compact data storage and the shorter data path.
These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.
In the drawings:
FIG. 1 shows the integration of the distance computation in a computer system,
FIG. 2 shows the formation of the distance between reference vectors and test vectors,
FIG. 3 shows the internal structure of a memory with integrated distance computation.
FIG. 1 shows the principal structure of a computer system. The Figure shows the memory with integrated distance computation 1, the system processor 2 and all further required or optional components as unit 3. The connections between said elements 1 to 3 are established via the data or address bus 4. An initialization of the distance computation 1 is performed via control lines 5. Incoming test signals are applied via interfaces in unit 3 to the overall system. These signals are converted in accordance with the type of signal and subdivided into segments. Components of a test vector are assigned to the different properties of a segment. A test vector is applied to the memory with integrated distance computation 1 via the bus 4. The distance computation between this test vector and at least a part of the reference data is performed in this memory with integrated distance computation 1, and the computed distances are applied for further processing to the overall system via the bus 4.
FIG. 2 shows a test vector 21 consisting of a plurality of components kin The reference vectors y1 to ym consist of the same number of components kn as the test vector 21. The components kn of these vectors comprise properties of the speech signal parts to be compared. The components k1 to kn of the test vector 21 are compared with the components k1 to kn of at least a part of the reference vectors y1 to ym. For the distance computation, the partial distances rn of the component values of the test vector 21 are formed with the corresponding component values of the considered reference vectors y1 to ym. The computed partial distances rn of the components kn of a reference vector y1 to ym are directly included in a distance Rym by way of summation. For forming the distance Rym, distance computations in accordance with, inter alia, Gauss or Laplace are fundamentally possible. This distance Rym represents a degree of similarity of the reference vector y1 to ym with the test vector 21. The distances Ry1 to Rym are stored in a list 22, with the number of distances Rym depending on the number of reference vectors y1 to ym which are compared with the test vector 21. FIG. 2 shows that a very large number of computations is required to compare the components kn of the test vector 21 with the relevant components kn of the reference vectors y1 to ym. Additionally, the distance Rym must be computed from the partial distances rn for each reference vector y1 to ym. A very long computing time is required for this large number of simple, constantly recurrent computations which, moreover, should be realized within a very short time.
FIG. 3 shows the internal structure of a memory module according to the invention. This memory module includes a reference memory 31 and a test memory 32 which are connected to a distance computer 34. This computer is coupled to a distance memory 33 which applies computed distances via the data output 42 and a driver 38 to the data terminal 39 and, via this connection, to a bus 4 (FIG. 1) to the system for further processing. Furthermore, this memory module comprises an address computer 36, address multiplexers 37 and a control unit 35.
Before a recognition process step, the reference memory is loaded with reference vectors via the data terminal 39. The test memory 32 receives the test vectors at the data input 43 also via the data terminal 39. The reference vectors to be compared and the relevant test vector are applied to the distance computer 34. In the distance computer 34, each reference vector and the test vector are compared with each other and the mutual distances between the components are formed. The distances between the compared vectors are stored in a distance memory 33.
The test memory 32 is implemented as a ring memory and is loaded with the test vector at the start of each distance computation by the system processor. The component to be currently compared is made available by means of a shifting process at the data output 45 of the test memory 32. Another possibility is to increment the current address of the component to be considered. The test memory has such a structure that, after a complete comparison of all components of the test vector with all components of a reference vector, the test vector is again available in its initial form in the test memory, or the current address is that of the first component of the test vector.
After a partial distance to the corresponding component of a reference vector is formed for each component of a test vector and a distance is formed from their combination, a subsequent reference vector is compared with the test vector. Both the reference memory 31 and the distance memory 33 are addressed via address multiplexers 37. The address multiplexers 37 apply the addresses, made available by the address computer 36, via address inputs 44 to the reference memory 31 and/or to the distance memory 33. The address for the distance memory can be most easily derived from the address for the reference memory by omitting the address lines required for addressing the individual vector components. The address multiplexers 37 enable the reference memory 31 and the distance memory 33 to be also addressed externally via the address terminal 40 which is connected to the external bus 4 (FIG. 1). The control unit 35 is initialized by the system via control lines 41 and takes over the control of the address multiplexers 37, the distance computer 34 and the test memory 32. After the distance computation has been performed, the control unit 35 indicates by means of the status line 46 to the system that the distances Rym are available.
The reference memory 31 may also be loaded with reference vectors via an I2C interface. Via this double-wire terminal, the reference memory 31 may also be loaded with reference vectors in the off-line state, or the data file may be updated. The reference memory 31 may be implemented as an EEPROM so that the reference vectors need not be loaded whenever the memory is switched on. The reference vectors are not transferred to the reference memory 31 during a recognition process step. Thus, this loading process does not require any computation time during the recognition process step. After the relevant test vector has been loaded via the data terminal 39, the recognition process step starts, computing the distances between this test vector and the reference vectors loaded in the reference memory 31. The computed distances are read by the system from the distance memory 33 via the data terminal 39, and are further processed.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4620316 *||Nov 19, 1985||Oct 28, 1986||Hitachi, Ltd.||Speech recognition system|
|US5014327 *||Feb 16, 1988||May 7, 1991||Digital Equipment Corporation||Parallel associative memory having improved selection and decision mechanisms for recognizing and sorting relevant patterns|
|US5027407 *||Jan 23, 1990||Jun 25, 1991||Kabushiki Kaisha Toshiba||Pattern recognition apparatus using a plurality of candidates|
|US5216748||Nov 4, 1991||Jun 1, 1993||Bull, S.A.||Integrated dynamic programming circuit|
|US5459798 *||May 12, 1993||Oct 17, 1995||Intel Corporation||System and method of pattern recognition employing a multiprocessing pipelined apparatus with private pattern memory|
|US5581485||Dec 8, 1994||Dec 3, 1996||Omni Microelectronics, Inc.||Analog vector distance measuring and vector quantization architecture|
|DE3239171A1||Oct 22, 1982||May 11, 1983||Sharp Kk||Integrierte einchip-schaltung fuer elektronische geraete mit tongeneratoreinrichtungen|
|DE3829032A1||Aug 26, 1988||Jul 5, 1990||Fraunhofer Ges Forschung||Device for storing and reproducing analog signals, preferably audio signals|
|DE6891495A||Title not available|
|EP0295876A2||Jun 15, 1988||Dec 21, 1988||Digital Equipment Corporation||Parallel associative memory|
|WO1995033259A1||May 26, 1995||Dec 7, 1995||Kurzweil Applied Intelligence, Inc.||Speech recognition system utilizing pre-calculated similarity measurements|
|1||*||Sung-Nam Kim, et al. "A VLSI Chip for Isolated Speech Recognition System," IEEE Trans. Consumer Electronics, vol. 42, No. 3, p. 458-467, Aug. 1996.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8818802||Aug 9, 2010||Aug 26, 2014||Spansion Llc||Real-time data pattern analysis system and method of operation thereof|
|US9135918||Oct 7, 2009||Sep 15, 2015||Cypress Semiconductor Corporation||Real-time data pattern analysis system and method of operation thereof|
|US9142209||Apr 22, 2014||Sep 22, 2015||Cypress Semiconductor Corporation||Data pattern analysis|
|US20110082694 *||Apr 7, 2011||Richard Fastow||Real-time data pattern analysis system and method of operation thereof|
|US20110208519 *||Oct 7, 2009||Aug 25, 2011||Richard M. Fastow||Real-time data pattern analysis system and method of operation thereof|
|U.S. Classification||704/238, 704/239, 704/E15.043|
|International Classification||G10L15/10, G10L15/26|
|Cooperative Classification||G10L15/10, G10L15/26|
|Mar 3, 1999||AS||Assignment|
Owner name: U.S. PHILIPS CORPORATION, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BUDDE, WOLGANG;STEINBIB, VOLKER;REEL/FRAME:009792/0237;SIGNING DATES FROM 19990126 TO 19990127
|Jun 7, 2002||AS||Assignment|
Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., NETHERLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:U.S. PHILIPS CORPORATION;REEL/FRAME:012968/0921
Effective date: 20020523
|Jun 21, 2006||REMI||Maintenance fee reminder mailed|
|Dec 4, 2006||LAPS||Lapse for failure to pay maintenance fees|
|Jan 30, 2007||FP||Expired due to failure to pay maintenance fee|
Effective date: 20061203