|Publication number||US6514672 B2|
|Application number||US 09/877,325|
|Publication date||Feb 4, 2003|
|Filing date||Jun 11, 2001|
|Priority date||Jun 17, 1999|
|Also published as||US6255022, US20010046632|
|Publication number||09877325, 877325, US 6514672 B2, US 6514672B2, US-B2-6514672, US6514672 B2, US6514672B2|
|Inventors||Bao-Ju Young, Chia-Shiung Tsai, Ying-Ying Wang|
|Original Assignee||Taiwan Semiconductor Manufacturing Company|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Referenced by (88), Classifications (10), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a division of patent application Ser. No. 09/334,904, filing date Jun. 17, 1999 now U.S. Pat No. 6,255,022. A Novel Dry Development Process For A Bi-Layer Resist System, assigned to the same assignee as the present invention.
(1) Field of the Invention
The invention relates to a method of fabricating a photoresist mask, and more particularly, to a method of fabricating a bi-layer photoresist mask that will improve critical dimension control in the manufacture of integrated circuits.
(2) Description of the Prior Art
Device sizes continue to shrink as semiconductor manufacturing processes are improved. Continuing advancement in the production of ever smaller devices is limited by photolithography techniques. Dry development processes can increase the overall process window for micro-patterning techniques. Dry development processes can improve resolution and depth of focus and result in more vertical resist profiles. However, the critical dimension bias between isolated and dense lines is too large. That is, because of microloading, isolated lines etch faster than dense lines resulting in an unacceptable difference in critical dimension. Also, after dry development in the bi-layer resist process, the resist line edge is very rough. This will cause imprecision in etching.
U.S. Pat. No. 5,545,512 to Nakato and U.S. Pat. No. 5,286,607 to Brown teach a bi-layer resist process in which a silylated layer is formed between the bi-layers. O2 dry development is used. U.S. Pat. No. 4,882,008 to Garza et al disclose a silylation process and O2 dry development of the resist using NO as the oxygen source.
A principal object of the present invention is to provide an effective and very manufacturable method of providing improved critical dimension control in photolithography.
Another object of the present invention is to provide a method of fabricating a photoresist mask with improved critical dimension control.
A further object of the present invention is to provide a method of fabricating a bi-layer photoresist mask with improved critical dimension control.
A still further object of the invention is to provide a method of fabricating a bi-layer photoresist mask with a reduced critical dimension bias between isolated and dense lines.
Yet another object of the invention is to provide a method of fabricating a bi-layer photoresist mask with a reduced critical dimension bias between isolated and dense lines by using a high SO2 gas dry development process.
Yet another object is to reduce edge roughness of a bi-layer photoresist mask after dry development.
A still further object of the invention is to reduce edge roughness of a bi-layer photoresist mask after dry development by adding an ashing step.
Yet another object of the invention is to provide a method of fabricating a bi-layer photoresist mask with a reduced critical dimension bias between isolated and dense lines and reduced edge roughness.
In accordance with the objects of this invention a new method of forming a bi-layer photoresist mask with a reduced critical dimension bias between isolated and dense lines and reduced edge roughness is achieved. A layer to be etched is provided on a semiconductor substrate wherein the surface of the layer has an uneven topography. The layer to be etched is coated with a first planarized photoresist layer which is baked. The first photoresist layer is coated with a second silicon-containing photoresist layer which is baked. Portions of the second photoresist layer not covered by a mask are exposed to actinic light. The exposed portions of the second photoresist layer are developed away. Then, portions of the first photoresist layer not covered by the second photoresist layer remaining are developed away in a dry development step wherein sufficient SO2 gas is included in the developing recipe to reduce microloading to form a bi-layer photoresist mask comprising the first and second photoresist layers remaining. Thereafter, the bi-layer photoresist mask is ashed to smooth its sidewall edges. This completes formation of a bi-layer photoresist mask having a reduced critical dimension bias between isolated and dense lines and reduced edge roughness.
In the accompanying drawings forming a material part of this description, there is shown:
FIGS. 1 through 7 schematically illustrate in cross-sectional representation a preferred embodiment of the present invention.
FIG. 8 schematically illustrates in cross-sectional representation a completed integrated circuit device fabricated by the process of the present invention.
Referring to FIGS. 1-8, fabrication and use of a photoresist mask for etching polysilicon gate electrodes will be illustrated and discussed. However, it will be appreciated by those skilled in the art that the process of the present invention can be used in any other photolithography applications as well, such as in local oxidation of silicon (LOCOS) or shallow trench isolation (STI), and other applications.
Referring now more particularly to FIG. 1, a portion of a partially completed integrated circuit device is illustrated. A semiconductor substrate 10 is shown, preferably composed of monocrystalline silicon. Field oxide regions 12 have been formed as is conventional in the art in the semiconductor substrate 10 resulting in an uneven topography of the surface of the substrate.
A layer of gate silicon oxide 14 is grown over the surface of the semiconductor substrate. A layer 16 of polysilicon or polycide is deposited over the uneven surface of the substrate to a thickness of, for example, between about 2000 and 3000 Angstroms.
Referring now to FIG. 2, a first underlayer of photoresist 18 is coated onto the polysilicon layer 16 to a thickness of between about 4000 and 5000 Angstroms. This photoresist layer is thick enough to be planarized at its top surface. The photoresist layer 18 may be an acrylic polymer, for example. The photoresist underlayer 18 is baked at a temperature of between about 120 and 130° C. for a duration of between about 2 and 3 minutes.
Referring now to FIG. 3, the second photoresist layer 20 is coated overlying the first photoresist underlayer 18. Photoresist layer 20 may be a methacrylate ter-polymer or a silicon-containing monomer, for example, having a thickness in the range of 2000 to 3000 Angstroms. The second photoresist 20 is baked at a temperature of between about 120 and 130° C. for a duration of between about 2 and 3 minutes. If the second photoresist layer does not contain silicon as deposited, the second photoresist layer is silylated. Silylation will make the exposed portion of the photoresist layer resistant to dry etchants, such as O2 reactive ion etching (RIE). During silylation, the photoresist is heated in an atmosphere containing a silylation agent. Typical silylation agents include N,N Diethylamino-trimethylsilane (TMSDEA), 1,1,3,3-Tetramethyldisilazane (TMDS), Trimethylsilyldimethylamine (TMSDMA), Dimethylsilyl-diethylamine (DMSDEA), and Dimethylsilyldimethylamine (DMSDMA). The hydrogen-containing radicals in the exposed portion of the photoresist 20 are displaced by silicon atoms in the silylating agent to form silylated layer 20.
Referring now to FIG. 4, the photoresist layer 20 is exposed to actinic light through a mask 22. The portions 26 not blocked by the mask 22 are exposed.
Referring now to FIG. 5, the exposed portions of the photoresist 26 are developed away using a conventional developer leaving the unexposed portions 20 of the photoresist as a photomask.
Next, referring to FIG. 6, an oxygen dry etching is used to remove the photoresist underlayer 18 not covered by the photomask. The silicon-containing photoresist layer 20 blocks the dry etchant so that the underlying resist remains.
In the prior art, this etching may be done using O2/SO2, where O2 is flowed at about 40 sccm and SO2 is flowed at about 10 sccm. However, in the process of the present invention, a new dry O2 development recipe is used. SO2 is a passivating gas. It is desired that the SO2 passivate the resist sidewalls in order to reduce the microloading effect especially in the area of dense lines, such as in area 30. Thus, the process of the present invention increases the SO2 gas content of the development recipe. This adjusts the concentration of the O2 gas, passivates the resist sidewalls, and hence reduces microloading. The result is that the critical dimension bias between the dense lines 30 and the isolated lines 32 will be minimized.
The O2 dry development recipe of the present invention comprises flowing O2 at 30 to 40 sccm and preferably about 40 sccm, flowing He at 50 to 60 sccm and preferably about 50 sccm, and flowing SO2 at 60 to 70 sccm and preferably about 60 sccm. A pressure of between about 5 and 6 mTorr is maintained and a power of 400 to 500 watts is applied. That is, the top power is about 450 watts and the bottom power is about 120 watts.
After dry development, the remaining top resist layer 20 has been changed to silicon dioxide and the bi-layer photomask 18/20 is complete.
An unwanted side effect of the dry development of the silicon-containing photoresist layer 20 is roughened edges of the resist lines at 36. This roughness can be seen by scanning electron microscope (SEM). The process of the present invention improves this edge roughness by applying an ashing step after dry development of the resist underlayer.
The ashing step of the present invention comprises flowing HBr at 30 to 40 sccm and flowing O2 at 10 to 20 sccm under a pressure of 5 to 6 mTorr and top power of 270 to 280 watts and 120 to 130 watts bottom power for 10 to 15 seconds. This is a conventional ashing recipe, but it is not conventional to use ashing at this point. Ashing is normally used to remove a photoresist mask. Photomask 20 will not be removed by the ashing step because it has been changed to silicon dioxide. The ashing does remove the sidewall surface roughness of the edges of the resist lines.
After the ashing step of the invention, it can be seen by SEM that the edges 36 of the resist lines are smooth.
Now the bi-layer photoresist mask 18/20 is ready to be used in etching t he underlying layer 16. For example, as shown in FIG. 7, the layers 16 and 14 are etched away where they are not covered by the photomask 18/20 to form polysilicon or polycide gates and lines 16.
The bi-layer photoresist mask 18/20 is removed. Processing continues as is conventional in the art. For example, as shown in FIG. 8, source and drain regions may be formed in the semiconductor substrate, such as N+ regions 32. Silicon oxide spacers 34 may be formed on the sidewalls of the gate electrodes 16. The semiconductor device structures may be covered by a thick dielectric layer 36. Openings are made through the dielectric layer 36 to underlying semiconductor structures such as source/drain region 32. A conducting layer may be deposited and patterned to complete electrical connections 38 to the underlying device structures. A passivation layer 40 completes the device.
The process of the present invention results in a uniform circuit critical dimension. The bi-layer photoresist mask of the invention allows for an increased process window for micro-patterning techniques without a critical dimension bias due to microloading. Line edge performance of the photoresist mask is improved by the ashing process of the present invention.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4882008||Jul 8, 1988||Nov 21, 1989||Texas Instruments Incorporated||Dry development of photoresist|
|US5286607||Dec 9, 1991||Feb 15, 1994||Chartered Semiconductor Manufacturing Pte Ltd.||Bi-layer resist process for semiconductor processing|
|US5318877 *||Nov 22, 1993||Jun 7, 1994||Cornell Research Foundation, Inc.||Bilayer resist and process for preparing same|
|US5545512||May 9, 1995||Aug 13, 1996||Sharp Microelectronics Technology, Inc.||Method of forming a pattern of silylated planarizing photoresist|
|US5756256 *||Jan 16, 1997||May 26, 1998||Sharp Microelectronics Technology, Inc.||Silylated photo-resist layer and planarizing method|
|US5935762 *||Oct 14, 1997||Aug 10, 1999||Industrial Technology Research Institute||Two-layered TSI process for dual damascene patterning|
|US6045981 *||Feb 6, 1998||Apr 4, 2000||Kabushiki Kaisha Toshiba||Method of manufacturing semiconductor device|
|US6074568 *||Jan 5, 1998||Jun 13, 2000||Sharp Kabushiki Kaisha||Dry etching method|
|US6255022 *||Jun 17, 1999||Jul 3, 2001||Taiwan Semiconductor Manufacturing Company||Dry development process for a bi-layer resist system utilized to reduce microloading|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6605519 *||May 2, 2001||Aug 12, 2003||Unaxis Usa, Inc.||Method for thin film lift-off processes using lateral extended etching masks and device|
|US6764946 *||Oct 1, 2003||Jul 20, 2004||Advanced Micro Devices, Inc.||Method of controlling line edge roughness in resist films|
|US6787455 *||Dec 21, 2001||Sep 7, 2004||Taiwan Semiconductor Manufacturing Co., Ltd||Bi-layer photoresist method for forming high resolution semiconductor features|
|US6842229||Dec 29, 2003||Jan 11, 2005||Board Of Regents, The University Of Texas System||Imprint lithography template comprising alignment marks|
|US6871558||Dec 12, 2002||Mar 29, 2005||Molecular Imprints, Inc.||Method for determining characteristics of substrate employing fluid geometries|
|US6873087 *||Oct 27, 2000||Mar 29, 2005||Board Of Regents, The University Of Texas System||High precision orientation alignment and gap control stages for imprint lithography processes|
|US6881534 *||Sep 11, 2002||Apr 19, 2005||Tdk Corporation||Method of forming mask, method of forming patterned thin film, and method of fabricating micro device|
|US6887649 *||Mar 7, 2002||May 3, 2005||Fujitsu Limited||Multi-layered resist structure and manufacturing method of semiconductor device|
|US6900881||Jul 11, 2002||May 31, 2005||Molecular Imprints, Inc.||Step and repeat imprint lithography systems|
|US6902853||May 11, 2004||Jun 7, 2005||Board Of Regents, The University Of Texas System||Dual wavelength method of determining a relative position of a substrate and a template|
|US6919152||May 27, 2003||Jul 19, 2005||Board Of Regents, The University Of Texas System||High resolution overlay alignment systems for imprint lithography|
|US6926929||Jul 9, 2002||Aug 9, 2005||Molecular Imprints, Inc.||System and method for dispensing liquids|
|US6955868||Feb 24, 2004||Oct 18, 2005||Board Of Regents, The University Of Texas System||Method to control the relative position between a body and a surface|
|US6986975||Apr 5, 2004||Jan 17, 2006||Board Of Regents, The University Of Texas System||Method of aligning a template with a substrate employing moire patterns|
|US7060324||Jan 13, 2004||Jun 13, 2006||Board Of Regents, The University Of Texas System||Method of creating a dispersion of a liquid on a substrate|
|US7060402||Feb 27, 2004||Jun 13, 2006||Board Of Regents, The University Of Texas System||Method of orientating a template with respect to a substrate in response to a force exerted on the template|
|US7115517||Sep 29, 2003||Oct 3, 2006||Applied Materials, Inc.||Method of fabricating a dual damascene interconnect structure|
|US7338275||May 11, 2005||Mar 4, 2008||Molecular Imprints, Inc.||Formation of discontinuous films during an imprint lithography process|
|US7413990||Jun 12, 2006||Aug 19, 2008||Applied Materials, Inc.||Method of fabricating a dual damascene interconnect structure|
|US7608541 *||Oct 27, 2009||Lg Display Co., Ltd.||Method of forming fine pattern, liquid crystal display device having a fine pattern and fabricating method thereof|
|US7670529||Mar 2, 2010||Molecular Imprints, Inc.||Method and system for double-sided patterning of substrates|
|US7670530||Mar 2, 2010||Molecular Imprints, Inc.||Patterning substrates employing multiple chucks|
|US7723235 *||Jun 10, 2005||May 25, 2010||Renesas Technology Corp.||Method for smoothing a resist pattern prior to etching a layer using the resist pattern|
|US7727453||May 11, 2005||Jun 1, 2010||Molecular Imprints, Inc.||Step and repeat imprint lithography processes|
|US7780893||Aug 24, 2010||Molecular Imprints, Inc.||Method of concurrently patterning a substrate having a plurality of fields and a plurality of alignment marks|
|US7802978||Mar 30, 2007||Sep 28, 2010||Molecular Imprints, Inc.||Imprinting of partial fields at the edge of the wafer|
|US7803308||Dec 1, 2005||Sep 28, 2010||Molecular Imprints, Inc.||Technique for separating a mold from solidified imprinting material|
|US7906058||Dec 16, 2005||Mar 15, 2011||Molecular Imprints, Inc.||Bifurcated contact printing technique|
|US7906180||Mar 15, 2011||Molecular Imprints, Inc.||Composition for an etching mask comprising a silicon-containing material|
|US8012395||May 12, 2009||Sep 6, 2011||Molecular Imprints, Inc.||Template having alignment marks formed of contrast material|
|US8016277||Sep 13, 2011||Board Of Regents, The University Of Texas System||Flexure based macro motion translation stage|
|US8076386||Feb 23, 2004||Dec 13, 2011||Molecular Imprints, Inc.||Materials for imprint lithography|
|US8142850||Mar 27, 2012||Molecular Imprints, Inc.||Patterning a plurality of fields on a substrate to compensate for differing evaporation times|
|US8211214||Jul 3, 2012||Molecular Imprints, Inc.||Single phase fluid imprint lithography method|
|US8349241||Oct 4, 2002||Jan 8, 2013||Molecular Imprints, Inc.||Method to arrange features on a substrate to replicate features having minimal dimensional variability|
|US8850980||Mar 30, 2007||Oct 7, 2014||Canon Nanotechnologies, Inc.||Tessellated patterns in imprint lithography|
|US9223202||Jul 9, 2007||Dec 29, 2015||Board Of Regents, The University Of Texas System||Method of automatic fluid dispensing for imprint lithography processes|
|US20020093122 *||Aug 1, 2001||Jul 18, 2002||Choi Byung J.||Methods for high-precision gap and orientation sensing between a transparent template and substrate for imprint lithography|
|US20020094496 *||Feb 12, 2002||Jul 18, 2002||Choi Byung J.||Method and system of automatic fluid dispensing for imprint lithography processes|
|US20020150398 *||Aug 21, 2001||Oct 17, 2002||Choi Byung J.||Flexure based macro motion translation stage|
|US20030003392 *||Jan 19, 2001||Jan 2, 2003||Hiroyuki Niwa||Positive type radiation-sensitive composition and process for processing for producing pattern with the same|
|US20030059722 *||Sep 11, 2002||Mar 27, 2003||Tdk Corporation||Method of forming mask, method of forming patterned thin film, and method of fabricating micro device|
|US20030119330 *||Dec 21, 2001||Jun 26, 2003||Taiwan Semiconductor Manufacturing Co., Ltd.||Bi-layer photoresist method for forming high resolution semiconductor features|
|US20030205657 *||May 1, 2002||Nov 6, 2003||Voisin Ronald D.||Methods of manufacturing a lithography template|
|US20030215577 *||May 16, 2002||Nov 20, 2003||Willson Carlton Grant||Method and system for fabricating nanoscale patterns in light curable compositions using an electric field|
|US20030235787 *||Jun 24, 2002||Dec 25, 2003||Watts Michael P.C.||Low viscosity high resolution patterning material|
|US20040009673 *||Jul 11, 2002||Jan 15, 2004||Sreenivasan Sidlgata V.||Method and system for imprint lithography using an electric field|
|US20040022888 *||Aug 1, 2002||Feb 5, 2004||Sreenivasan Sidlgata V.||Alignment systems for imprint lithography|
|US20040038552 *||Aug 23, 2002||Feb 26, 2004||Watts Michael P.C.||Method for fabricating bulbous-shaped vias|
|US20040053146 *||May 27, 2003||Mar 18, 2004||University Of Texas System Board Of Regents, Ut System||Method of varying template dimensions to achieve alignment during imprint lithography|
|US20040065976 *||Oct 4, 2002||Apr 8, 2004||Sreenivasan Sidlgata V.||Method and a mold to arrange features on a substrate to replicate features having minimal dimensional variability|
|US20040089979 *||Nov 13, 2002||May 13, 2004||Molecular Imprints, Inc.||Method of reducing pattern distortions during imprint lithography processes|
|US20040104641 *||Jul 10, 2003||Jun 3, 2004||University Of Texas System||Method of separating a template from a substrate during imprint lithography|
|US20040112153 *||Dec 12, 2002||Jun 17, 2004||Molecular Imprints, Inc.||Method and system for determining characteristics of substrates employing fluid geometries|
|US20040112861 *||Dec 11, 2002||Jun 17, 2004||Molecular Imprints, Inc.||Method for modulating shapes of substrates|
|US20040124566 *||Jul 11, 2002||Jul 1, 2004||Sreenivasan Sidlgata V.||Step and repeat imprint lithography processes|
|US20040168588 *||Feb 27, 2004||Sep 2, 2004||Board Of Regents, The University Of Texas System||Method of orientating a template with respect to a substrate in response to a force exerted on the template|
|US20040168613 *||Feb 27, 2003||Sep 2, 2004||Molecular Imprints, Inc.||Composition and method to form a release layer|
|US20040170770 *||Feb 27, 2003||Sep 2, 2004||Molecular Imprints, Inc.||Method to reduce adhesion between a polymerizable layer and a substrate employing a fluorine-containing layer|
|US20040170771 *||Jan 13, 2004||Sep 2, 2004||Board Of Regents, The University Of Texas System||Method of creating a dispersion of a liquid on a substrate|
|US20040188381 *||Mar 25, 2003||Sep 30, 2004||Molecular Imprints, Inc.||Positive tone bi-layer imprint lithography method|
|US20040189996 *||Apr 5, 2004||Sep 30, 2004||Board Of Regents, The University Of Texas System||Method of aligning a template with a substrate employing moire patterns|
|US20040198062 *||Sep 29, 2003||Oct 7, 2004||Applied Materials, Inc.||Method of fabricating a dual damascene interconnect structure|
|US20040209177 *||May 11, 2004||Oct 21, 2004||Board Of Regents, The University Of Texas System||Dual wavelength method of determining a relative position of a substrate and a template|
|US20040211754 *||Apr 25, 2003||Oct 28, 2004||Molecular Imprints, Inc.||Method of forming stepped structures employing imprint lithography|
|US20040256764 *||Jun 17, 2003||Dec 23, 2004||University Of Texas System Board Of Regents||Method to reduce adhesion between a conformable region and a pattern of a mold|
|US20050067379 *||Sep 25, 2003||Mar 31, 2005||Molecular Imprints, Inc.||Imprint lithography template having opaque alignment marks|
|US20050072755 *||Oct 2, 2003||Apr 7, 2005||University Of Texas System Board Of Regents||Single phase fluid imprint lithography method|
|US20050089774 *||Feb 24, 2004||Apr 28, 2005||Board Of Regents, The University Of Texas System||Method to control the relative position between a body and a surface|
|US20050160934 *||Jan 23, 2004||Jul 28, 2005||Molecular Imprints, Inc.||Materials and methods for imprint lithography|
|US20050187339 *||Feb 23, 2004||Aug 25, 2005||Molecular Imprints, Inc.||Materials for imprint lithography|
|US20050274219 *||Jun 1, 2004||Dec 15, 2005||Molecular Imprints, Inc.||Method and system to control movement of a body for nano-scale manufacturing|
|US20050275311 *||Jun 1, 2004||Dec 15, 2005||Molecular Imprints, Inc.||Compliant device for nano-scale manufacturing|
|US20050277066 *||Jun 10, 2004||Dec 15, 2005||Le Ngoc V||Selective etch process for step and flash imprint lithography|
|US20060145398 *||Dec 30, 2004||Jul 6, 2006||Board Of Regents, The University Of Texas System||Release layer comprising diamond-like carbon (DLC) or doped DLC with tunable composition for imprint lithography templates and contact masks|
|US20060216926 *||Jun 12, 2006||Sep 28, 2006||Applied Materials, Inc.||Method of fabricating a dual damascene interconnect structure|
|US20070001961 *||Jun 13, 2006||Jan 4, 2007||Lg.Philips Lcd Co., Ltd.||Method of forming fine pattern, liquid crystal display device having a fine pattern and fabricating method thereof|
|US20070126150 *||Dec 16, 2005||Jun 7, 2007||Molecular Imprints, Inc.||Bifurcated contact printing technique|
|US20070126156 *||Dec 1, 2005||Jun 7, 2007||Molecular Imprints, Inc.||Technique for separating a mold from solidified imprinting material|
|US20070132152 *||Nov 30, 2006||Jun 14, 2007||Molecular Imprints, Inc.||Method and System for Double-Sided Patterning of Substrates|
|US20070170617 *||Jan 19, 2007||Jul 26, 2007||Molecular Imprints, Inc.||Patterning Substrates Employing Multiple Chucks|
|US20070228610 *||Apr 3, 2007||Oct 4, 2007||Molecular Imprints, Inc.||Method of Concurrently Patterning a Substrate Having a Plurality of Fields and a Plurality of Alignment Marks|
|US20070243655 *||Mar 29, 2007||Oct 18, 2007||Molecular Imprints, Inc.||Self-Aligned Process for Fabricating Imprint Templates Containing Variously Etched Features|
|US20080045022 *||Jun 10, 2005||Feb 21, 2008||Masaru Kurihara||Semiconductor Device Manufacturing Method|
|US20080141862 *||Feb 5, 2008||Jun 19, 2008||Molecular Imprints, Inc.||Single Phase Fluid Imprint Lithography Method|
|US20080199816 *||Jul 9, 2007||Aug 21, 2008||The University Of Texas Board Of Regents||Method of Automatic Fluid Dispensing for Imprint Lithography Processes|
|US20090037004 *||Sep 11, 2008||Feb 5, 2009||Molecular Imprints, Inc.||Method and System to Control Movement of a Body for Nano-Scale Manufacturing|
|US20090250840 *||May 12, 2009||Oct 8, 2009||Molecular Imprints, Inc.||Template Having Alignment Marks Formed of Contrast Material|
|U.S. Classification||430/314, 430/312, 430/317, 430/316, 430/318, 430/329, 430/330|
|Jul 7, 2006||FPAY||Fee payment|
Year of fee payment: 4
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Year of fee payment: 8
|Jul 9, 2014||FPAY||Fee payment|
Year of fee payment: 12