US 6560749 B1 Abstract An apparatus and method for implementing a decoder for convolutionally encoded symbols (e.g., a viterbi decoder) is described. In one embodiment, a file of all the initial states (or their equivalents) and the nth surviving states associated with the initial states is stored along with the path metric. The initial states (or their equivalents) are an index to a previous file. A new file or files are then generated. An appropriate criterion is utilized to select a final surviving state. The path can be traced back through a plurality of files and the “most likely” path determined. The identifying binary numbers of the final states of each file and the binary numbers of an original initial state determine the “most likely” sequence of convolutionally-encoded symbols received by the decoder.
Claims(9) 1. A method of block-decoding a convolutionally-encoded sequence of symbols, the method comprising:
for each symbol received, generating a plurality of transition metrics, wherein each transition metric is associated with a state;
for each state, selecting one transition metric for each of the plurality of possible transitions from the state;
performing a series of butterfly operations to update tables of state information for said each state;
for each group of a preselected number of symbols, generating a fixed length table that is updated by a plurality of butterfly operations, wherein each entry of the fixed length table includes a history entry, an index entry and a path metric entry for each state;
for said each group of a preselected number of symbols, generating a summary table, the summary table having a variable length; and
upon identification of a predetermined condition, concatenating indexed history entries from the summary tables;
each index entry identifying a history entry in the summary table, the history entry being generated for the next previous group of symbols, wherein concatenating indexed history entries from the summary tables includes using the index entries to backtrack a sequence of history entries and at least a portion of the summary tables are transferred to system memory prior to backtracking.
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Description U.S. application Ser. No. 09/493,767 filed on Jan. 28, 2000, and entitled “Digital Signal Processor Implementation of a Decoder for Convolutionally Encoded Symbols” is a related U.S. Application is incorporated by reference herewith. 1. Field of the Invention This invention relates generally to communication techniques and, more particularly, to the decoding of digital signals in a communication system. In the communication system envisioned by the present invention, each bit of information has been encoded in a multiplicity of transmitted signals. The resulting signals are generally referred to as convolutionally encoded symbols. 2. Description of the Related Art Communications channels in general and digital wireless communications in particular must counteract noise which may obliterate individual transmitted symbols. Conceptually, there are two approaches to this problem: one, by introducing redundancy and another, by smearing the transmitted information over multiple symbols. These approaches are not entirely separate since any redundancy makes it easier to spread the information over a plurality of signals, but neither are the two approaches identical. Convolution codes are often used to implement the smearing of information over several symbols. Simply put, the EXCLUSIVE_OR (XOR) logic operation is applied to several recent information bits (equivalently, the information bits are summed modulo Referring to FIG. 1, an example of channel coding used for IS-95 is illustrated. The IS-95 encoder Note that, for the exemplary IS-95 channel encoder, a single input bit affects the next 9 output bit pairs, no one of which reflects exactly the information of that single input bit. The convolution codes smear the information of the single input bit over eighteen bits of output bit pairs. The virtue of this smearing of information is that, when a single symbol (or even more than one symbol) is corrupted in transmission, the decoder often can still recover the input information bit. Computing Metrics Pairs of output bits become symbols that have some physical representation on the communications channel. These symbols are transmitted and the receiver makes a measurement of the resulting signal that it receives. Of course, the received signal differs from the signal that is transmitted and the difference between the two signals is called noise. The receiver can calculate the distance between the received signal and each of the four symbols that might have been transmitted. The details of the computation of this metric depend on the particular communications channel and how the states are represented physically. In the receiver's computation of metrics, a first option provides for the conversion of the received signal to a digital signal (in this case a pair of bits) and then computation of the metric. Apparatus using this approach is called a hard decision decoder. The other option, which is more complex computationally but which generally results in fewer errors, is the computation of the metric from the original signal levels; this process being provided by a soft decision decoder. Trellis Decoding Referring next to FIG. 2, a four-state trellis diagram, according to the prior art, is illustrated. Each column of the trellis diagram represents a Viterbi decoder at an instant of time and the arrows in the diagram represent the transitions of that decoder from one instant of time to the next. Notice that the nodes of the diagram are labeled with a pair of binary digits, 00, 01, 10, 11, the binary digits representing the state numbers 0, 1, 2, and 3. Also observe that the arrows between nodes are labeled either 0 or 1 and that the label of each node is always formed by concatenating the labels any pair of arrows from two columns earlier that lead to that node. Expressed another way, the number of each node specifies the last two (because this is a four-state decoder) transitions made to get to that state. Of course multiple paths lead to each state, but these paths differ only at earlier transitions. Referring once again to FIG. 2, in moving from one increment of time to the next, the Viterbi decoder, i.e., a decoder that decodes convolutionally encoded symbols, receives or computes metrics representing the distance from the received signal to what would be transmitted for an information bit of “0” and for an information bit of “1”. This computation is performed for each possible history of transmitted bits as encoded by the various state identification numbers. These metrics are referred to as transition metrics and they include the noise for a current symbol. The transition metrics are summed along the paths and these sums are called path metrics. Two arrows represent transitions that can enter each node and two other arrows represent transitions that can leave each node. At each node, path metrics are associated with each incoming arrow. The trellis decoder selects the smaller path metric, i.e., the path metric representing the smaller noise figure of the two incoming signals. All of the paths associated with the non-selected arrow (i.e., transition) are permanently abandoned by the trellis decoder. The transition metric corresponding to an information bit of “1” is added to the surviving incoming path metric and the sum is forwarded to the node at the next time instant along the arrow labeled Referring to FIG. 3, examples of butterfly diagrams are shown for a 16-state encoder. For each butterfly diagram, two states serve as input transitions to determine two states for the next time increment. For example, for the butterfly diagram represented by the solid lines, the states 0001 and 1001 serve as inputs to the determine the states 0100 and 0011 for the next time increment. Unfortunately, a significant amount of memory is needed to specify each state. In implementing the decoding algorithm, not only is the history information associated with each state retained, but the path metrics are also retained, i.e., for selecting between two input transitions that terminate on the same state. If the butterfly operations are processed as indicated in FIG. 3, two copies of these data groups would be required to be saved in order that the storage resulting from one butterfly diagram does not corrupt the input data needed to process the result of a different butterfly diagram. An alternative to the doubling of the required memory is to re-assign the state table at each iteration as illustrated in FIG. The primary, but not sole advantage to re-arranging the order of the state memories is that, as the data for a state is updated, the new data can be stored in the same locations that were used, although for a different state number, at the previous stage. In more visual terms, referring to FIG. 4, the inputs and outputs for each butterfly operation lie at the same positions of the arrays, i.e., the transitions are horizontal. By selecting the transition with the smaller path metric in the decoder, at each step in time, the number of paths stays constant in the following sense. Half of the entering paths are abandoned, but the surviving paths are appended with both 0 and with 1, creating two paths for each of the surviving paths. After a sufficient period of time, various paths are abandoned and the number of surviving paths that (at a fixed earlier time t In implementing a Viterbi decoder, two practical difficulties are present: computational load and the demand for memory. The computational load is more a result of the high symbol rates than of the complexity of the calculation, but a strong incentive still exists to design the algorithms to be as efficient as possible. The memory demands of a Viterbi decoder derive from the need to maintain an indefinitely long history of the paths surviving to each of the states. Maintaining long histories for each of the 256 states of an IS-95 decoder, for example, can require large amounts of memory. A common solution to the problem of maintaining long histories has been to force the decoder to make decisions prematurely and therefore guarantee a fixed history length. However, such truncations introduce errors and, in order to avoid excessive errors with this approach, history lengths of 4-5 times the constraint length are generally recommended. Traditional Viterbi decoders, i.e., decoders of convolutionally encoded symbols, record (as a single bit in “trace-back” memory) each decision that is made. At a later time, the decoder must work backward through this historical record, one bit at a time, to determine the final decoded record. This trace-back operation can be computationally intensive. Often, data is encoded in “frames” consisting of a fixed number of bits and with several zero's added to the end. This procedure allows the decoder to assume that the final state of the frame is zero. Having a known final state greatly simplifies the trace-back problem. A need has been felt for an apparatus and a method having the feature that the implementation of the decoding of convolutionally encoded symbols is improved. Another feature of the apparatus and method would be that the implementation of the decoding of convolutionally encoded symbols requires less memory. Still another feature of the apparatus and method would permit path trace-back to be performed in units of more than one bit at a time (viz., {constraint_length The aforementioned and other features are accomplished, according to the present invention, by providing a unit, hereinafter called a block trellis decoder, that makes decoding decisions determined by the multiple paths entering and exiting from the nodes of a Viterbi trellis diagram. In the present invention, rather than maintain a full history for each node, linked lists of histories are maintained. A procedure for selecting paths based on path metrics is used. Because paths are abandoned at each step, the histories for more distant past events can be compressed to become ever-shorter tables. A set of paths can be summarized in a single file. Each file includes, for each state through which a surviving path passes: a state binary number, the state binary number indicating the set transition history; an index number pointing to a state binary number in the previous file; and a path metric quantity. Forcing the decoder to make premature decisions may still be necessary, but this will be because the total memory describing the transition history has been exhausted. Because this memory is used flexibly and efficiently, forcing premature decision will be necessary less often than when all history back to a fixed point in the past is maintained. The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. FIG. 1 is an example of channel or convolutional encoding according to the prior art. FIG. 2 illustrates a 4-state Viterbi trellis diagram according to the prior art. FIG. 3 illustrates examples of butterfly diagrams for a 16 state decoder unit according to the prior art. FIG. 4 illustrates the cyclic nature of the butterfly diagrams for a 16 state decoder unit wherein the state designation is altered from the processing of one symbol to the next symbol according to the prior art. FIG. 5 illustrates s a block diagram of a Viterbi decoder according to the present invention. FIGS. 6A-6B illustrate the multiplicity of paths that are described by the state identification numbers for a four state Viterbi decoder according to the present invention. FIG. 7 illustrates the processing of a symbol in a four-state decoder according to the present invention. FIG. 8 illustrates how the files transferred to the history tracker and merger unit by the trellis decoder for a four state decoder for convolutionally encoded symbols are generated according to the present invention. FIG. 9A illustrates a format for files maintained for a plurality of symbols received by the decoder unit for a two state convolutional encoder, while FIG. 9B identifies the path that is illustrated by the files according to the present invention. FIG. 10A illustrates a second format for files maintained for the same plurality of symbols illustrated in the FIG. 9A, while FIG. 10B identifies the path that is illustrated by the files according to the present invention. FIG. 11A is a flow diagram illustrating the operation of the metric server; FIG. 11B is a flow diagram of the operation of the trellis decoder unit; and FIG. 11C is a flow diagram illustrating the operation of the metric tracker and server unit, according to the present invention. FIG. 12 illustrates one communication system incorporating the present invention. The use of the same reference symbols in different drawings indicates similar or identical items. FIG. 1, FIG. 2, FIG. In the preceding description, the terms Viterbi and trellis were both used in a generally accepted manner. The device that decodes convolutionally encoded symbols is typically called a Viterbi decoder. However, a term is needed for a specific type of Viterbi decoder. This designation is needed for a unit that makes decisions illustrated by the multiple paths in and out of the nodes of FIG. The input to a Viterbi decoder inherently has a bit-at-a-time nature, but the consumer of its output is a processor that works more naturally and efficiently with data that is organized into bytes or even 16-bit words. As was discussed above, for a decoder with 2 Referring to FIG. 5, a block diagram, illustrating the overall operation of the inventive block trellis decoder In FIG. 5, all three units may be implemented in software, just, as it is possible that all three units may be implemented in hardware; however, for many if not most applications, units Referring once again to FIG. 5, the operation of one embodiment of the metric server
where P is a power factor, which for the duration of a frame can be treated as a constant, s The metric server
For decoding a single frame at a particular rate, using only the middle term (with the constant, The four choices of signs in the expression ±R An equivalent (but computationally simpler) means for computing the same signed transition metrics is summarized as follows. Given an pair of input signals, R A A B B It follows that TR00=A TR01=A TR10=A TR11=A As will be clear, the transition metrics can be calculated in a manner different from the examples described above for the IS-95 example. For the present invention, it is useful that the values be unsigned and critical that the larger metric correspond to a less likely transition. After generating the transition metrics in the metric server Before proceeding, it should be recalled that the state number is determined by the sequence of recent transitions that comprise the binary identification of the state number. For example, referring to FIG. 6, for the four state encoder, the (10) state is reached by 0-transition preceded by a 1 -transition. However, as can be seen from FIG. 6A, two paths have the 1-transition followed by a 0-transition. Referring to FIG. 6B, two more paths are possible that provide a 1-transition followed by a 0-transition. However, as will be clear by review of FIG. Let the states of a path through the 2
As noted above, the fact that “the path assumes states S The operation of the decoder in processing a single symbol is illustrated using a four-state decoder as an example. Referring to FIG. 7, at time t
At the same time, H(01:t Trellis decoder unit In either embodiment, the paths through the other states are handled analogously. Likewise, in a decoder with more states (e.g., the IS-95 decoder with 256 states), the operation is exactly the same for each state. As will be clear to those skilled in the art of Viterbi decoders, it is possible to conserve memory in the trellis decoder unit and simplify computations by operating on pairs of states together so as to update the path metrics, history and (in the case of the first embodiment) index values for the two states at the same time, keeping the same memory locations. This implies that the data associated with a given state moves from one location to another from one time interval to another; however, at the end of (constraint_length Each time a table of metrics arrives, the trellis decode unit must update the state information (i.e., the path metric, history and, in the first realization, the index) for each state. These operations are most conveniently performed on pairs of states in what is called a butterfly operation. For example in a 256 state decoder, 128 butterfly operations are performed each time a table of metrics arrives (i.e., for each symbol). The state information resides at the two indices lo and hi in the tables of state information inside the trellis decode unit
The trellis decoder unit Recall that the path metrics are unsigned and that arithmetic relating to the path metrics is in all cases saturated. One consequence of this is that there is a maximum value for the path metric, MAX, which is characterized by having all bits equal to 1. A path with a metric of MAX is regarded as no longer surviving. Consider the first realization in which the index values have been updated. For k=0, 1, 2, 3, H
and in this case, the index table will be revised to the values I
and revise the index table to the values I In the second embodiment in which the index values have not been updated, we again observe that for k=0, 1, 2, 3, H
and in this case, the index table will be revised to the values I
and revise the index table to the values I More generally, for a decoder with N=2 In the history merger and tracker unit, the object is to determine the most probable path through the multiplicity of states and transitions. The path determines a sequence of states. When each state is determined, the logic signals that generate that state are generally the logic signals that were originally transmitted. When the transmitted logic signals are determined, the sequence of logic signals that was applied to the convolutional encoder can be determined. The operation of the two pointer-indexes is illustrated in FIG. 9A, FIG. 9B, FIG. FIG. 11A, FIG. 11B, and FIG. 11C provide flow charts illustrating the operation of portions of the invention. Referring now to FIG. 11A, the operation of the metric server is illustrated. In step Referring now to FIG. 11B, the operation of one implementation of the trellis decoder is illustrated. In step Referring now to FIG. 11C, the activity of the history tracker and merger unit depends on the transfer of the tables created in the trellis decoder unit, and has a counter part to step Referring to FIG. 12, an implementation of the present invention is illustrated. The encoded symbols are transmitted through channel The decoding of convolutionally-encoded symbols is provided, according to the present invention, in three stages. In the first stage, the transition metrics are generated in response to the receipt of the transmitted symbols. The internal state of the block trellis decoder unit is maintained in several tables. The table entries include a history field, a field that is determined by the possible paths of the group of symbols, an index field, a field that identifies a history field in the preceding table, and a path metric field, a field that establishes the deviation of the path from the path most likely to have been followed by the encoded symbols. In the important IS-95 protocol, the table entries of the tables can be expressed in fields having 8 bits, a field length particularly convenient for manipulation by modern data processing systems. A single surviving path is identified by some criterion, e.g., only one path survives, the remaining possible paths having been discarded. By retracing the table entries of the surviving path, the transmitted symbols can be determined and, based on the determination of the transmitted symbols, the original signals can be determined. The procedure is summarized in FIGS. 11A-11C. As will be clear from FIG. 12, the division of the present invention into a metric server unit, a trellis decoder unit, and a history tracker and merger unit, while useful for describing the operation of the present invention, is, in some implementations, artificial. For example, in the purely software implementation, this division would find expression in the modules of the software program. However, no specific part of the processing unit could be identified with a particular unit. The present invention is particularly well suited to the IS-95 conventions. In this convention, the states are determined by an eight-bit binary number. Because the processing device is typically implemented in a byte, or multiple byte format, the use of eight-bit quantities is particularly advantageous. As will be clear to those skilled in the art, the partition between the portion of the invention implemented in hardware and the portion of the invention implemented in software is flexible. The entire invention can be implemented in software and in some applications, such as the software modem, such an implementation is necessary. However, to accelerate the computation for higher data rates, hardware can be used to implement the entire decoder. For the IS-95 application, experience suggests that the most advantageous partition used DSP software to compute the vector of the four metrics and to perform the later trace-back operation, but implemented the rest of the decoding in hardware. It will be further clear that the processing of transition metrics in blocks of symbols having B (=constraint length−1) members to provide tables having partial path information is particularly convenient, however, the division of the symbols in groups of B symbols is not essential. Blocks of symbols having a different number of members can be similarly processed. For instance, the number of members can be an integer times B. Such a division on symbols can be useful when B is small, wherein tables can be generated that more fully populate word-length data fields. In the modified decoder, the variable length tables are transferred every n*B symbols, where B is (constraint length−1). The first table is transferred after (n+1)*B symbols rather than after Those skilled in the art will readily implement the steps necessary to provide the structures and the methods disclosed herein, and will understand that the process parameters, materials, dimensions, and sequence of steps are given by way of example only and can be varied to achieve the desired structure as well as modifications that are within the scope of the invention. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the spirit and scope of the invention as set forth in the following claims. Patent Citations
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