US 6580294 B1 Abstract A differential logic stage includes a precharge circuit, a first evaluate circuit and a second evaluate circuit. The precharge circuit is connected to a first potential and a differential output defined by a first output node and a second output node. The second evaluate circuit is connected to a second potential and a first output node. The second evaluate circuit is connected to the second potential and the second output node. The second evaluate circuit is symmetric with the first evaluate circuit, and in one embodiment each evaluate circuit includes a transistor stack and an input transistor. The transistor stack is connected between the second potential and one of the output nodes. The input transistor is connected in parallel with the transistor stack.
Claims(17) 1. A logic stage comprising:
a precharge circuit connected to a first potential and a differential output defined by a first output node and a second output node;
a first evaluate circuit connected to a second potential and the first output node; and
a second evaluate circuit connected to the second potential and the second output node, the second evaluate circuit being symmetric with the first evaluate circuit, each evaluate circuit including a transistor stack connected between the second potential and one of the output nodes, and an input transistor connected in parallel with the transistor stack, each transistor stack including a first series transistor connected to the second potential, and a second series transistor connected between the first series transistor and one of the output nodes, the first series transistor being larger than the second series transistor.
2. The logic stage of
3. The logic stage of
4. The logic stage of
5. The logic stage of
6. The logic stage of
7. The logic stage of
8. Implemented in a differential domino logic stage having a precharge circuit and a true evaluate circuit, a not true evaluate circuit comprising:
a transistor stack connected between a potential and one of a pair of output nodes, the transistor stack to receive a not true generate input corresponding to a less significant bit of an adder circuit and a not true generate input corresponding to a more significant bit; and
an input transistor connected in parallel with the transistor stack, the input transistor to receive a not true propagate input corresponding to the more significant bit.
9. The not true evaluate circuit of
10. The not true evaluate circuit of
a first series transistor connected to the potential; and
a second series transistor connected between the first series transistor and one of the output nodes.
11. The not true evaluate circuit of
12. The not true evaluate circuit of
13. The not true evaluate circuit of
14. The not true evaluate circuit of
15. A logic stage comprising:
a precharge circuit connected to a first potential and a differential output defined by a first output node and a second output node;
a first evaluate circuit connected to a second potential and the first output node; and
a second evaluate circuit connected to the second potential and the second output node, the second evaluate circuit being symmetric with the first evaluate circuit, each evaluate circuit including a transistor stack connected between the second potential and one of the output nodes, and an input transistor connected in parallel with the transistor stack, each transistor stack including a first series transistor connected to the second potential, and a second series transistor connected between the first series transistor and one of the output nodes, the second series transistor to receive a signal that is located in a path that is more critical than a path including a signal received by the first series transistor.
16. The logic stage of
17. The logic stage of
Description 1. Technical Field The present invention generally relates to semiconductor circuits. More particularly, the invention relates to differential domino logic stages for digital adders. 2. Discussion Fundamental to the operation of virtually all digital microprocessors is the function of digital (i.e., binary) addition. Addition is used not only to provide numerical sums, but also in the implementation of numerous logic functions. In a typical microprocessor, many adders are used for these functions. When two digital words are added, the carry bit that results from the addition of lessor significant bits must be considered when adding more significant bits. The carry bit can easily be considered by rippling a carry signal through the entire addition chain as the addition is performed. A problem with such an approach, particularly for relatively large words (e.g., 64 bits) is that substantial time is required to ripple the carry signal. Since adders are often performing logic functions in critical time paths, the time needed to ripple the carry signal can slow up the microprocessor. In response to the above concerns, techniques such as the static carry look-ahead (CLA) adder described in U.S. Pat. No. 5,847,984 to Mahurin have evolved. A difficulty associated with such a static adder, however, is that there typically is relatively high input loading on the circuit. High input loads can compromise speed. Domino circuits use clock signals to dynamically obtain “precharge” and “evaluation” phases for the domino circuits. These phases enable a reduction in input loading resulting in higher gain per stage and considerable speed increases. Two types of domino circuits are single ended and differential circuits. Single ended domino circuits use fewer transistors than the equivalent evaluate circuits, but require two stages of logic when constructing exclusive OR (XOR) gates. This characteristic can be important considering the fact that XOR gates are used in the fabrication of arithmetic logic units (ALUs). Domino circuits such as the p-type polysilicon (or metal oxide) semiconductor (PMOS) circuit Traditionally, each differential domino logic stage has a precharge circuit The various advantages of the present invention will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which: FIG. 1 is a transistor level diagram of an example of a logic stage in accordance with one embodiment of the present invention; FIG. 2 is a transistor level diagram of an example of a logic stage in accordance with an alternative embodiment of the present invention; FIG. 3 is a transistor level diagram of an example of a conventional logic stage useful in understanding the invention; and FIG. 4 is a transistor level diagram of an alternative conventional logic stage, useful in understanding the invention. FIG. 1 shows a logic stage It can generally be seen that the precharge circuit It can be therefore be seen that each evaluate circuit Each transistor stack includes a first series transistor connected to the second potential Returning now to FIG. 2, it can be seen that similar benefits can be achieved with an n-type polysilicon (or metal oxide) semiconductor (NMOS) logic stage With continuing reference to FIGS. 1 and 2, it can be seen that the precharge circuit The logic stages described herein can be used to construct adders that are faster, more robust and less difficult to manufacture. For example, by alternating PMOS and NMOS logic stages with relatively fast clock inverters disposed between the stages, XOR functions can be performed more easily and critical paths are significantly reduced. Those skilled in the art can now appreciate from the foregoing description that the broad techniques of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims. Patent Citations
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