|Publication number||US6583021 B2|
|Application number||US 10/141,713|
|Publication date||Jun 24, 2003|
|Filing date||May 9, 2002|
|Priority date||Jun 30, 2001|
|Also published as||US20030003648|
|Publication number||10141713, 141713, US 6583021 B2, US 6583021B2, US-B2-6583021, US6583021 B2, US6583021B2|
|Original Assignee||Hynix Semiconductor Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (16), Referenced by (23), Classifications (22), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the invention relates to a method for fabricating a capacitor thereof.
2. Brief Description of Related Technology
As an integration of a semiconductor device becomes higher recently, studies are conducted to increase the charge storage area by forming a capacitor in a complicated structure such as a cylinder, fin, stack or hemispheric silicon (HSG) to secure sufficient capacitance. In addition, a dielectric layer of capacitor is formed of materials HfO2, Al2O3, Ta2O5, SrTiO3, (Ba,Sr)TiO3, BLT, etc., of which dielectric constants are higher than SiO2 or Si3N4. In particular, a hafnium oxide (HfO2) layer is a high dielectric layer currently studied for a gate insulation layer and a dielectric layer of a capacitor.
FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for fabricating a capacitor.
Referring to FIG. 1A, an inter-layer dielectric layer (ILD) 12 is formed on a surface of a semiconductor substrate 11 having transistors and bit lines, and a storage node contact mask (not shown) is formed on inter-layer dielectric layer (ILD) 12. After that, a storage node contact hole is formed to expose a predetermined area of the surface of the semiconductor substrate 11 by etching the inter-layer dielectric layer 12 with the storage node contact mask.
Subsequently, a polysilicon layer is formed on the entire surface including the storage node contact hole, and then an etch-back process is carried out in order to form a polysilicon plug 13 in the contact hole to a predetermined depth.
After that, a titanium silicide (TiSi2) 14 and a titanium nitride (TiN) layer 15 are formed on the polysilicon plug 13. The TiSi2 layer 14 forms an ohmic contact with a following bottom electrode, and the TiN layer 15 serves as an anti-diffusion layer that prevents oxygen remaining inside the bottom electrode from diffusing into the polysilicon plug 13, the storage node contact plug, or into the semiconductor substrate 11.
Referring to FIG. 1B, a sacrificial oxide layer 16 that determines the height of the bottom electrode is formed on the inter-layer dielectric layer 12 and the TiN layer 15, and then a storage node mask (not shown) using a photoresist is formed on the sacrificial oxide layer 16.
Subsequently, the sacrificial oxide layer 16 is selectively etched with the storage node mask to form an opening in which a bottom electrode is aligned on the polysilicon plug 13 to be formed.
Thereafter, a bottom electrode 17 is formed of metal over the surface of the sacrificial oxide layer 16 including the opening. After that, the bottom electrode is made to remain in the opening only through the process of etch-back or chemical mechanical polishing method so that the bottom electrode in the concavity is isolated from the neighboring bottom electrodes.
Referring to FIG. 1C, on the entire surface including the bottom electrode 17, a dielectric layer 18 and a top electrode 19 are formed successively. Here, the bottom electrode 17, dielectric layer 18 and top electrode 19 are formed by the chemical vapor deposition (CVD) method, and the dielectric layer 18 is mostly made of a high dielectric layer, such as HfO2.
In the conventional method described above, a capacitor is formed connected to a plug by using a storage node contact mask.
However, in a dynamic RAM (DRAM) over 4 Gbits that a fine design rule should be applied to, the storage node contact plug and the bottom electrode should not be misaligned. Also, to secure a sufficient capacitance, the height of the bottom electrode should be increased. This is a difficult because the plug height for interconnection becomes higher as the height of the bottom electrode gets higher. In addition, because the isolation gap from the neighboring bottom electrode is reduced, the current technology forming a bottom electrode, dielectric layer and top electrode by the CVD method has reached its limitation, so an atomic layer deposition (ALD) method is under development recently.
However, the ALD method has a shortcoming that an extra thermal treatment, or plasma treatment should be performed in every step to improve the quality of the layers. This is because the ALD method conducts depositions at a low temperature to improve the step coverage. Due to such complicated processes and investment for new equipments, the production costs are high for the ALD method.
It would be desirable to provide a method for fabricating a capacitor that avoids a rise in the production cost and complexity in production processes caused by performing a deposition and a subsequent treatment thereof whenever a layer is formed.
It also would be desirable to provide a method for fabricating a capacitor that avoids a misalignment in masking or etching processes for connecting transistors and the capacitor.
Accordingly, disclosed herein is a method of fabricating a capacitor, comprising the steps of: (a) forming a Ti1−xHfxN layer on a substrate, wherein x is in a range from 0 to 0.5; (b) forming an electrode layer on the Ti1−xHfxN layer; and, (c) forming a HfO2 layer on an interface between the electrode layer and the Ti1−xHfxN layer by performing a thermal treatment in an oxygen gas-containing atmosphere. Such a capacitor will include a bottom electrode formed from the Ti1−xHfxN layer, a dielectric layer formed from the HfO2 layer, and a top electrode formed from the electrode layer.
Also disclosed herein is a method for fabricating a capacitor, comprising the steps of: (a) forming an inter-layer dielectric layer on a silicon semiconductor substrate; (b) forming a contact hole that exposes a surface of the semiconductor substrate by selectively etching the inter-layer dielectric layer; (c) forming a Ti1−xHfxN layer in the contact hole, wherein x is in a range from 0 to about 0.5; (d) forming an electrode layer on the Ti1−xHfxN layer; and forming a HfO2 layer on an interface between the electrode layer and the Ti1−xHfxN layer by performing a thermal treatment in an oxygen atmosphere. Such a capacitor will include a bottom electrode formed from the Ti1−xHfxN layer, a dielectric layer formed from the HfO2 layer, and a top electrode formed from the electrode layer.
Additional features of the invention will become apparent from the following description of the preferred embodiments taken in conjunction with the appended claims and the accompanying drawings, in which:
FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for fabricating a capacitor;
FIGS. 2A to 2C are cross-sectional views depicting a method for fabricating a capacitor in accordance with an embodiment of the present invention; and,
FIG. 3 is a graph showing a phase stability of TiO2 and HfO2.
Referring to FIG. 2A, an inter-layer dielectric layer 22 is deposited on a semiconductor substrate 21 having transistors and bit lines to insulate the substrate 21 from a capacitor to be formed subsequently. Thereafter, a storage node contact mask (not shown) is formed on the inter-layer dielectric layer 22 by using a photoresist. The inter-layer dielectric layer 22 is formed with an oxide layer to a thickness of about 5000 Å to about 20000 Å.
Subsequently, a storage node contact hole is formed to expose a predetermined part of the semiconductor substrate 11 by etching the inter-layer dielectric layer 22 with the storage node contact mask. Here, the storage node contact hole can be formed in a shape of a circle, stick, rectangle or polygon.
Thereafter, a titanium layer is deposited on the entire surface including the storage node contact hole. After performing a rapid thermal process (RTP), an ohmic layer 23 of titanium silicide (TiSi2) is formed on the exposed semiconductor substrate 21 in the storage node contact hole to improve the contact resistance between the substrate 21 and a bottom electrode to be formed. The titanium layer is deposited by a method of sputtering, a chemical vapor deposition (CVD), or an atomic layer deposition (ALD) to a thickness of about 100 Å to about 500 Å. The rapid thermal process for forming the titanium silicide (TiSi2) 23 is performed in a nitrogen or argon atmosphere at a temperature of about 700° C. to about 900° C. for about 10 seconds to about 180 seconds. After that, non-reacted titanium is removed by wet-etching with ammonium hydroxide or sulphuric acid. At this moment, the wet-etching is carried out for about one minute to about 40 minutes. Meanwhile, after the deposition of titanium layer, an extra layer of titanium nitride (TiN) can be formed to a thickness of about 100 Å to about 500 Å by sputtering, CVD, or ALD methods.
After removing any non-reacted titanium, a Ti1−xHfxN layer 24 layer is formed by a sputtering, CVD, or ALD method, to a thickness of about 100 Å to about 300 Å. In case of depositing Ti1−xHfxN layer 24 by the CVD or ALD methods, it can be deposited by gradually increasing the molar fraction of Hf relative to TiN to Ti0.5Hf0.5N.
Referring to FIG. 2B, a Ti1−xHfxN layer 24 a is made to remain only in the storage node contact hole by removing the Ti1−xHfxN layer 24 from the inter-layer dielectric layer 22. At this moment, a photo-resist layer or a spin-on-glass (SOG) layer is coated on the entire surface including on the Ti1−xHfxN layer 24, and the photo-resist layer or the SOG layer is selectively removed in order to leave the photo-resist layer or the SOG layer in the storage node contact hole only. After that, the Ti1−xHfxN layer 24 is etched back or polished chemically and mechanically using the photo-resist or the SOG as an etch mask or an anti-polish layer until the surface of the inter-layer dielectric layer 22 is exposed.
Subsequently, an electrode layer 25 is formed on the entire surface including Ti1−xHfxN layer 24 a which remains in the storage node contact hole. Here, the electrode layer 25 is formed of a noble metal such as platinum, iridium, and ruthenium, and the electrode layer may be formed of a conductive oxide, or a complex layer of a noble metal and a conductive oxide. The electrode layer 25 is deposited by a sputtering, CVD, or ALD method to a thickness of about 50 Å to about 2000 Å.
Here, the conductive oxides are IrO2, RuO2, SrRuO3, (Ba,Sr)RuO3, (Sr,Ca)RuO3, A1−xRexBzO3 (0≦x≦0.5, 0≦y≦0.5, 0.9≦z≦1.1, A═Y, La; Re═Sr, Ca; B═Cr, Mn, Fe) or La1−xSrxCo1−yCryO3(0≦x≦0.5, 0≦y≦0.5).
Referring to FIG. 2C, the substrate is thermally treated in an atmosphere containing a gaseous mixture of O2+N2 or O2+Ar at a temperature of about 400° C. to about 800° C. for about 10 seconds to about 10 minutes.
In a thermal treatment performed an O2-containing gaseous atmosphere, the Ti1−xHfxN 24 a is oxidized, thus forming a HfO2 layer 26 to a thickness of about 50 Å to about 300 Å on the interface of the Ti1−xHfxN 24 a and the electrode layer 25.
The non-reacted Ti1−xHfxN 24 a that has not participated in the formation of the HfO2 layer 26 is used as a bottom electrode 24 b, and the thermally-treated electrode layer 25 is used as a top electrode 25 a, the HfO2 layer 26 being used as a dielectric layer of the capacitor.
Just as mentioned above, the Ti1−xHfxN layer 24 a forms the HfO2 layer 26 and the bottom electrode 24B. So, the Ti1−xHfxN layer 24 a which is a storage node contact and anti-diffusion layer, is utilized as a bottom electrode 24 b as well. Moreover, it simplifies a capacitor fabrication process by using the anti-diffusion Ti1−xHfxN layer 24 a as a bottom electrode 24 b, and forming a top electrode 25 a on top of the Ti1−xHfxN layer 24 a. That is, by forming only two layers (i.e., the Ti1−xHfxN layer 24 and the electrode layer 25) and performing a thermal treatment (unlike the conventional technology that forms the five layers of a titanium silicide/titanium nitride/bottom electrode/dielectric layer/top electrode in order), it is possible to simplify the fabrication procedure.
If the Ti1−xHfxN layer 24 is exposed in the O2 atmosphere without an electrode layer thereon and oxidized, the surface reacts with O2 so it becomes rough. Also, because the surface does not receive any compressive stress from outside, the Ti1−xHfxN layer 24 becomes swollen during the oxidation and forms fine cracks, thus inhibiting the obtainment of a quality HfO2 as good as can be used for a dielectric layer.
Also, in the case of forming HfO2 by the CVD method or the ALD method, a high-temperature thermal treatment is necessary to improve the quality of HfO2 layer, because the oxidation reaction occurs at a low temperature. However, in an embodiment of the present invention, since the oxygen atom (O), which diffused through the electrode layer 25 on the Ti1−xHfxN layer 24 a is made to react with the Ti1−xHfxN layer 24 a, the reaction time is very fast. Also, covered with the electrode 25, the Ti1−xHfxN layer 24 a receives compressive stress from it and the interface between the HfO2 and the electrode layer 25 is smooth. Besides, with HfO2 formed through a thermal treatment, the lattice mismatch is relieved as much as possible, and the amount of surface charges that adversely affects leakage current is minimized.
Extra nitrogen atoms (N) generated while the HfO2 is formed resolve back into the Ti1−xHfxN layer 24 a, so no void is generated between the HfO2 layer 26 and the electric layer 25.
The capacitor formed in the above processes uses an electrode layer 25 as its top electrode 25A; non-reacted Ti1−xHfxN layer 24 as its bottom electrode 24A; and the reaction product HfO2 layer 26 as its dielectric layer. A desired thickness of the dielectric layer can be obtained by controlling the temperature and time of a thermal treatment.
The oxide layer generated during the oxidation of Ti1−xHfxN is not a TiO2 layer but a HfO2 layer can be known by a thermodynamic observation.
FIG. 3 is a graph showing the phase stability of TiO2 and HfO2.
With reference to FIG. 3, since the partial pressure of oxygen (PO2) in the present of Hf/HfO2 is lower than the partial pressure of oxygen (PO2) in the present of Ti/TiO2, HfO2 is more stable than TiO2 thermodynamically. Accordingly, when Hf and Ti are mixed and thermally treated in an oxygen atmosphere, Hf which is less stable thermodynamically, is oxidized faster than Ti because the oxidation potential of Hf is bigger than that of Ti.
Likewise, in case Ti1−xHfxN is oxidized, HfO2 is more stable thermodynamically than the TiO2 formed on the surface.
A sacrificial oxide layer for a bottom electrode need not he formed, because the bottom electrode is directly formed in the storage node contact hole by the present invention, thus simplifying the processes by lowering the deposition height of the capacitor as well as ensuring the alignment of depositions.
Also, this invention can obtain high quality of HfO2 and low leakage current by a solid reaction method through one-time thermal treatment with no need for a chemical vapor deposition (CVD) device or atomic layer deposition (ALD) device to form the HfO2.
The present invention also simplifies the fabrication process as well by forming a HfO2, bottom electrode, top electrode through one-time thermal treatment after depositing a Ti1−xHfxN and a conductive layer successively.
While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.
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|U.S. Classification||438/396, 438/386, 257/E21.274, 257/E21.008, 257/E21.168, 438/768, 257/E21.011, 438/244, 148/DIG.14, 257/E21.29|
|International Classification||H01L21/316, H01L21/285, H01L21/02, H01L27/108|
|Cooperative Classification||Y10S148/014, H01L28/60, H01L21/31604, H01L28/40, H01L21/31683, H01L21/28568|
|European Classification||H01L21/316B, H01L21/316C3|
|Aug 16, 2002||AS||Assignment|
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SONG, CHANG-ROCK;REEL/FRAME:013191/0810
Effective date: 20020517
|Dec 1, 2006||FPAY||Fee payment|
Year of fee payment: 4
|Dec 2, 2010||FPAY||Fee payment|
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|Jan 30, 2015||REMI||Maintenance fee reminder mailed|
|Jun 24, 2015||LAPS||Lapse for failure to pay maintenance fees|
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Effective date: 20150624