|Publication number||US6624079 B2|
|Application number||US 09/931,953|
|Publication date||Sep 23, 2003|
|Filing date||Aug 20, 2001|
|Priority date||Aug 20, 2001|
|Also published as||CN1190822C, CN1402303A, US20030036276|
|Publication number||09931953, 931953, US 6624079 B2, US 6624079B2, US-B2-6624079, US6624079 B2, US6624079B2|
|Inventors||Yuan-Li Tsai, Marcus Yang, Ralph Chen, Heng-Chun Kao, Ching-Chun Hwang|
|Original Assignee||United Microelectronics Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (2), Classifications (18), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a method for forming high resistance resistor. More particularly, the present invention relates to a method for forming a high resistance resistor with integrated high voltage device process.
2. Description of the Prior Art
Isolation is provided in a semiconductor between transistors on a semiconductor chip to prevent unwanted electrical connections there between. On the development of ultra-large-scale-integrated (ULSI), layout rule will shrink and the application of product is going to invent on multi-chip of integrated function.
In conventional methods, a substrate 10 comprise a implemented N-well 12, and a field oxide area 20 is formed on the substrate 10, wherein the N-well is a high resistance area of high voltage device such as shown in FIG. 1. A mixed-mode process can provide a process flow with embedded capacitor in logic circuit. The additional capacitor can be used for RC analog circuit or other special applications. A first electrode 30 of capacitor is formed on the field oxide area 20. An interpoly dielectric layer 40 such as oxide-nitride-oxide (ONO) layer is formed on the first electrode 30. A second electrode 50 of capacitor is formed on the oxide-nitride-oxide layer 40. The first electrode 30 and second electrode 50 are comprised polysilicon layer. An interlevel dielectric layer 70 is formed over the substrate 10 and capacitor. Then etch interlevel dielectric layer 70 to form a plurality contact hole. A conductive material is deposited to form contacts. Such as a contact 65 connect to high concentration area of N-well 60, a contact 32 connect to first electrode 30 and contact 52 connect to second electrode 50 of capacitor.
However, in the conventional process to form a high resistance resistor with an integrated high voltage device process, the high resistance area of N-well is pre-formed in the substrate. Then to be continued process to a formed capacitor has several thermal treatments then will induce a variation of devices. They will cause different bias voltage.
It is therefore an objective of the invention to provide a method of manufacturing a high voltage device. The capacitor and high resistance resistor are formed by the same fabricating step.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a high resistance resistor with an integrated high voltage device process.
In this invention, a process in the formation of a high resistance resistor with an integrated high voltage device process is desired. A substrate comprised explanation a field oxide area. An un-doped polysilicon layer is deposited on the field oxide area. An interpoly dielectric layer such as oxide-nitride-oxide (ONO) layer is formed on the un-doped polysilicon layer. Then etch oxide-nitride-oxide layer and processing ion implant process by BF2 implant to the un-doped polysilicon layer. Adjusting dosage of BF2 controls the resistance of resistor. An interlevel dielectric layer such as silicon oxide is formed on the substrate and the resistor. The silicon oxide layer is etched to form contact holes. An ion implant process is performed to reduce resistance between contact and resistor by BF2 radical. The thermal rapid processing (RTP) increased ion diffusion of ion implant and a metal is deposited to formed contact.
In this invention, the high voltage device combined with mixed mode processes by using un-doped polysilicon layer instead of the conventional polysilicon layer. First the source region and drain region is formed, then the high resistance area with ion implant. In this high resistance area: first, etch oxide-nitride-oxide layer, second, ion implant process by using BF2 radical to the un-doped polysilicon layer to form resistor. Adjusting dosage of BF2 controls the resistance. Next performing contact etched, the high dosage of BF2 implant to high resistance area to reduce resistance between contact and resistor.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a cross sectional view of convention method illustrating for forming high resistance resistor with integrated high voltage process, wherein the N-well as resistor is formed in the substrate;
FIGS. 2A through FIG. 2H are cross sectional view of this invention illustrating for forming high resistance resistor with integrated high voltage process; and
FIG. 3 is correlation curve of ion implant dosage with resistance.
The present invention will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout.
First, as shown in FIG. 2A, a substrate 100 is provided. A first field oxide area 105 a and second field oxide area 105 b are formed on the substrate 100 by using a conventional method such as a thermal oxidation method. Between the first field oxide area 105 a and second field oxide area 105 b comprises a transistor structure (not shown in the figure). Polysilicon layers 110 a and 110 b are deposited over the substrate 100 and field oxide area 105 a, 105 b, wherein the polysilicon layer 110 a, 110 b are un-doped polysilicon layer with a thickness about 1500 angstroms.
Next, as shown in FIG. 2B, a photoresist layer 115 is formed on the polysilicon layer 110 a, wherein the photoresist layer 115 has a resistance pattern. Utilizing the photoresist layer 115 as a mask, a procedure using first, an ion implant process on the polysilicon layer 110 b is performed. Then, the polysilicon layer 110 b becomes a doped polysilicon layer. The first ion implant process is performed by using a phosphorous implant and improved ion diffusion with an annealing temperature of about 1000° C.-1100° C.
Next step as shown in FIG. 2C, the photoresist layer 115 is removed. An interpoly dielectric layer such as oxide-nitride-oxide (ONO) layer is formed on the polysilicon layer by a conventional method. Then, the oxide-nitride-oxide layer and the polysilicon layer are etched with a conventional etching method. The un-doped polysilicon layer resistor 120 a on the first field oxide area 105 a. The interpoly dielectric layer 125 a on the resistor 120 a. The resistor 120 a on the first field oxide area 105 a serve as high resistance area. The doped polysilicon layer 120 b after first ion implant process on the second field oxide area 105 b. The doped polysilicon layer 120 b serves as first electrode of capacitor. The interpoly dielectric layer 125 b on the first electrode 120 b. In the same step, gate structure is formed any area except the field oxide area 105 a, 105 b. The source region and drain region are formed by standard process after this step (not shown in figure).
Next step as shown in FIG. 2D, a second polysilicon layer 130 is formed on the oxide-nitride-oxide layer 125 b, wherein the second polysilicon layer is doped. The second polysilicon layer 130 serve as second electrode of capacitor. A second photoresist layer 135 is formed on the substrate 100, capacitor and high resistance area 120 a wherein the photoresist layer 135 has an opening pattern 137 to expose the high resistance area 120 a.
Dry etching or wet etching method removes the oxide-nitride-oxide layer 125; this is an important step of this invention. In this embodiment, dry etching is the preferred method. The resistance of the un-doped polysilicon layer 120 a is very high after the removal of the oxide-nitride-oxide layer 125 a. Then, utilizing the second ion implant process the resistance is therefore controlled. In this invention the second ion implant process to the un-doped polysilicon layer 120 a is achieved by using BF2 radical. The correlation curve of resistance and ion implant dosage is shown in FIG. 3. Adjusting the dosage of BF2 controls the resistance. The function is:
Y: resistance (Ohms/Sq)
X: implant dosage (e−/cm2)
Next, as shown in FIG. 2F, the second photoresist layer 135 is removed. An interlevel dielectric layer 140 such as silicon oxide is formed on the substrate 100, the high resistance area 120 a and the capacitor. Silicon oxide 140 is achieved by using the spin-on-glass (SOG) method or another suitable method. The interlevel dielectric layer 140 processing re-flow step temperature is controlled to about 850° C. At the same time the re-flow step can improve the second ion implant process diffusion to resistor 120 a. Next, using a standard process in the interlevel dielectric layer 140 forms a plurality of contact hole 122, 132, and 126. The contact hole 126 connects to resistor 120 a. The contact hole 122 connects to the first electrode and the contact hole 132 connects to the second electrode of the capacitor.
Next, as shown in FIG. 2G, a third photoresist layer 150 is formed on the interlevel dielectric layer 140, wherein the third photoresist layer 140 has an opening pattern 152 to expose the contact hole 126. To reduce the resistance of interface between the contact hole 126 and resistor 120 a there must be a third ion implant process by using BF2 radical. The dosage of the third ion implant process is more than second ion implant process by over 2 times. The third photoresist layer 150 is removed. After the third ion implant process, performing rapid thermal processing (RTP) to improved ion diffuse. The rapid thermal process temperature is about 900° C.
Next, as shown in FIG. 2H, a conductive material is deposited to fill contact holes 122, 132, 126 in order to form contacts 160, 162, and 164. The contact 164 connect to resistor 120 a. The contact 160 connect to first electrode 120 b and contact 162 connect to second electrode 130 of capacitor. Next, an interconnect layer such as 170, 172, and 174 is formed on the interlevel dielectric layer 140.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4291328 *||Jun 15, 1979||Sep 22, 1981||Texas Instruments Incorporated||Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon|
|US5352923 *||Aug 12, 1993||Oct 4, 1994||Northern Telecom Limited||Trench resistors for integrated circuits|
|US5677228 *||Jan 24, 1997||Oct 14, 1997||Vanguard International Semiconductor Corporation||Method of fabricating a resistor in an integrated circuit|
|US5705418 *||Jul 9, 1996||Jan 6, 1998||Winbond Electronics Corporation||Process for fabricating reduced-thickness high-resistance load resistors in four-transistor SRAM devices|
|US6054359 *||Jun 14, 1999||Apr 25, 2000||Taiwan Semiconductor Manufacturing Company||Method for making high-sheet-resistance polysilicon resistors for integrated circuits|
|US6211031 *||Oct 1, 1998||Apr 3, 2001||Taiwan Semiconductor Manufacturing Company||Method to produce dual polysilicon resistance in an integrated circuit|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7241663||Apr 19, 2005||Jul 10, 2007||Texas Instruments Incorporated||Maskless multiple sheet polysilicon resistor|
|US20060234439 *||Apr 19, 2005||Oct 19, 2006||Texas Instruments Incorporated||Maskless multiple sheet polysilicon resistor|
|U.S. Classification||438/694, 438/702, 257/E21.004, 438/719, 257/E27.047, 257/E27.024, 257/E27.048|
|International Classification||H01L27/06, H01L21/02, H01L27/08|
|Cooperative Classification||H01L28/20, H01L27/0676, H01L27/0805, H01L27/0802|
|European Classification||H01L28/20, H01L27/08B, H01L27/06D6V, H01L27/08C|
|Aug 20, 2001||AS||Assignment|
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TSAI, YUAN-LI;YANG, MARCUS;CHEN, RALPH;AND OTHERS;REEL/FRAME:012099/0172;SIGNING DATES FROM 20010720 TO 20010726
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