|Publication number||US6624643 B2|
|Application number||US 09/733,461|
|Publication date||Sep 23, 2003|
|Filing date||Dec 8, 2000|
|Priority date||Dec 8, 2000|
|Also published as||US20020070739|
|Publication number||09733461, 733461, US 6624643 B2, US 6624643B2, US-B2-6624643, US6624643 B2, US6624643B2|
|Inventors||Terrence J. Dishongh, Prateek Dujari, Bin C. Lian, Damion T. Searls|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (14), Classifications (5), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates generally to silicon devices and integrated circuits, and in particular but not exclusively, relates to reading output information from a backside of a silicon device.
2. Background Information
Communication from a silicon device or integrated circuit to external components on a motherboard is typically done via use of electrical connections between the silicon and a substrate material. Examples of such electrical connections include wire bonding and controlled collapse chip carrier (C4) connections.
In instances where faster communication from the silicon device to the motherboard is needed, directed chip attachment (DCA) technology has been considered. Unfortunately, DCA technology has serious reliability issues with regards to thermal mismatches and production/inventory control.
With the ever-increasing need for high-speed applications, such as those beyond 2.5 Gbits/second, the above-mentioned electrical connections and DCA connections face severe limitations due to thermal dissipation, skin effect attenuation, jitter and noise issues, etc. Such limitations significantly degrade signal and performance characteristics associated with communication between silicon devices and external components, particularly when reading output information/signals from the silicon devices.
Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
FIG. 1 is an exploded view of an embodiment of the present invention.
FIG. 2 is a view illustrating operation of the embodiment shown in FIG. 1.
FIG. 3 is a view illustrating an example connection between a substrate and a photodetector array of the embodiment of FIGS. 1-2.
FIG. 4 is a view illustrating another example connection between a substrate and the photodetector array of the embodiment of FIGS. 1-2.
FIG. 5 is a view illustrating an example placement of optical transmitters for the connection shown in FIG. 4.
FIG. 6 is a view illustrating an example connection of optical receivers to the optical transmitters of FIG. 5.
Embodiments of an apparatus and method to read output information from a backside of a silicon device are described herein. In the following description, numerous specific details are provided, such as various mounting and connection components in FIGS. 2-6, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
As an overview, an embodiment of the invention detects photon emissions from a backside of a silicon device or integrated circuit, with the photon emissions forming part of an output signal path from the integrated circuit. The photon emissions are detected by a photodetector array, which in one embodiment comprises a photodiode array, and then signals representing the photon emissions (and their underlying information) can be sent by optical transmitters to optical receivers for subsequent processing.
Referring first to FIG. 1, shown generally at 10 is an exploded view of an assembly according to one embodiment of the invention. The assembly 10 includes a photodetector array 12 fused to a cooling block 14. An example of the photodetector array 12 that can be used by an embodiment of the invention is an indium gallium arsenide (InGaAs) PIN photodiode array. In another embodiment photodetectors such as for example an array of charge coupled devices 15 can be used. It is understood that other suitable photodetectors such as for example phototransistors may also be used.
The cooling block 14 is used for thermal cooling of the various components of the assembly 10, and can be made of aluminum or copper material, for example. The cooling block 14 has through-holes or input route(s) 16 and output route(s) 18 for coolant fluid. The coolant fluid can comprise any number of readily available coolant fluids, such as water.
The assembly 10 further includes a mask 20, which in one embodiment is made from a carbon material. Other types of materials that may be used for the mask 20 include materials that are thermally conductive and that can act as thermal transfer element and as an electromagnetic shield. The mask 20 includes a plurality of openings or holes 22. As will be described below, the holes 22 allow photons emitted from underlying transistors to reach corresponding photodetectors of the photodetector array 12, while the remaining portions of the mask 20 prevent passage of photons emitted from non-corresponding transistors.
The assembly 10 includes an integrated circuit device 24, which may include one or more silicon devices, such as transistors that emit photons. The device 24 can be in the form of one or more die having a backside 26. An example of the device 24 is an organic land grid array (OLGA) component, and it is understood that other types of devices may be implemented by embodiments of the invention.
An embodiment of the assembly 10 thus combines use of backside photon emissions with thermal cooling, thereby allowing output signals to be read from the backside 26 of the device 24 and allowing the device 24 to be cooled by the cooling block 14. FIG. 2 illustrates operation of the assembly 10 in connection with reading or detecting photon emissions from the backside 26 of the device 24. A magnified portion 28 shows interaction/operation of the various parts of the assembly 10 in more detail.
An electrical signal, such those signals that are generated during normal operation of the device 24, travels from a source of a transistor (formed in the device 24) to a drain, as a result of standard electrical fields applied to a gate of the transistor. That is, the gate allows electrons to pass from the source to the drain. As a result of this electrical transmission, photon(s) 30 move or radiate from the source towards the drain.
After the photons 30 are emitted, they travel through the holes 22 of the mask 20. An infrared-transparent fluid may be disposed in or may cover the holes 22. Examples of infrared-transparent fluids that can be used include olive oil, or Galden™ or Fomblin™ fluids manufactured by Ausimont of Italy.
After passing through the holes 22 and the infrared-transparent fluid, the photons 30 reach an N-type region 32 of the photodetector array 12. The photons 30 travel through the N-type region 32 until they are collected by a plurality of P-type receivers 34 of the photodetector array 12. Once the photons 30 reach the P-type receivers 34, the P-type receivers 34 generate an electrical current, which can be amplified by electronic circuitry (not shown) disposed on a substrate 36 of the photodetector array 12.
Operation of the assembly 10 described above with reference to FIG. 2 can occur during a testing stage during a manufacturing process of the assembly 10 (e.g., to test if the transistors in the device 24 are functioning properly) or during actual use of the assembly 10. For these operating environments, FIGS. 3 and 4 show example connections of the photodetector array 12 to exterior substrates, as well as showing examples of how the assembly 10 can be mounted to a printed circuit board (PCB) or to a motherboard.
As an initial consideration, proper alignment of the photodetector array 12 to the transistors of the device 24 can improve the accuracy of photon reception. In some situations, exact one-to-one alignment between transistors and their corresponding photodetectors may be difficult to achieve. Therefore, an embodiment of the invention places the photodetector array 12 in a general position, such that a group of photodetectors in the photodetector array 12 is dedicated to one transistor of the device 24. An example of this group of photodetectors is an array of 25 photodiodes (e.g., a 5×5 array), with all 25 photodiodes subsequently being tied to a single/same output from the photodetector array 12. Thus, it is not necessary to have exact one-to-one correlation in this embodiment. A plurality of set screws 38, shown in FIGS. 3 and 4, may be used to hold down the cooling block 14 and to move the photodetector array 12 to a general position.
FIG. 3 shows the assembly 10 mounted to a PCB, motherboard, or other board/card 40. The assembly 10 may be mounted to the board 40 via solder joints 42, retention screws 44, or via other suitable attachment techniques. A magnified portion 46 illustrates an embodiment of a connection technique to connect the photodetector array 12 to an exterior substrate 48. From the exterior substrate 48, electrical signals can be carried from the photodetector 12 to other devices on the board 40.
As shown by the magnified portion 46, wires 50 couple metal interconnect pads 52 of the exterior substrate 48 to the P-type receivers 34 of the photodetector array 12. In this manner, the wires 50 can carry electrical signals that represent the photons 30 detected by the photodetector array 12. Standard wire bond technology may be used to connect the wires 50 between the pads 52 and the P-type receivers 34. The wires 50 may be made from a gold material or other high-conductivity material. The photodetector array 12 (e.g., its substrate 36) may be epoxied to the exterior substrate 48 using silver epoxy or other suitable adhesive.
A magnified portion 54 in FIG. 4 illustrates an embodiment of a C4 connection technique to connect the photodetector array 12 to an exterior substrate 56. Metal portions/layers 58 are disposed over the P-type receivers 34 of the photodetector array 12. Solder joints 60 connect the metal portions 58 to metal pads 62 of the exterior substrate 56.
Shown next in a magnified portion 64 in FIG. 5 is an example placement of one or more optical transmitters 66 for the C4 connection embodiment of FIG. 4. The optical transmitters 66 can comprise fiber optic transmitters such as those that are commercially available. The optical transmitters 66 are placed over the exterior substrate 56, and are coupled to receive the electrical signals from the photodetector array 12 and to convert the received electrical signals into optical signals for transmission to other devices on the board 40. Through-holes 68 may be made in the exterior substrate 56 for mounting the optical transmitters 66 and for routing interconnection paths.
FIG. 6 illustrates connection of optical receivers 70 to the optical transmitters 66, via fiber optic cables 72. The optical receivers 70 can be coupled to devices, such as a processor, on the board 40 that process the information read from the backside 26 of the device 24. The fiber optic cables 72 provide flexibility that allows them to extend over the cooling block 14 and to make interconnections to the optical receivers 70 without interference.
In conclusion, an embodiment of the invention is able to read information from the backside 26 of the device 24 by detecting photon emissions. Such an embodiment effectively utilizes these photon emissions, as compared to existing systems that do not use the photon emissions and thus “waste” information. Use of the photon emissions as a technique to read output information is useful in silicon processor and memory technology that use large numbers of input/output. Furthermore, use of the cooling block 14, in combination with the reading of photon emissions, address heat and power dissipation requirements that are associated with higher levels of input and output of silicon devices.
Current photo-electronic systems that use optical channels to extract information from silicon devices have structures that crowd the existingly tight footprint of a C4 electronic device. One embodiment of the assembly 10 avoids this crowding by extracting information from the backside of the silicon where no input/output channels currently exist. Furthermore, this embodiment uses natural device physics to extract output information without changing a silicon process.
The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
For instance, FIGS. 5-6 show an example placement of the optical transmitters 66 with regards to the substrate 56 that is connected to the photodetector array 12 using C4 connection techniques. It is understood that the optical transmitters 66 can be placed on substrates that are connected to the photodetector array 12 via connection techniques that are different from C4.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
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|U.S. Classification||324/750.08, 324/762.02|
|Dec 8, 2000||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DISHONGH, TERRENCE J.;DUJARI, PRATEEK;LIAN, BIN C.;AND OTHERS;REEL/FRAME:011361/0310;SIGNING DATES FROM 20001121 TO 20001130
|Mar 16, 2007||FPAY||Fee payment|
Year of fee payment: 4
|Mar 17, 2011||FPAY||Fee payment|
Year of fee payment: 8
|May 1, 2015||REMI||Maintenance fee reminder mailed|
|Sep 23, 2015||LAPS||Lapse for failure to pay maintenance fees|
|Nov 10, 2015||FP||Expired due to failure to pay maintenance fee|
Effective date: 20150923