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Publication numberUS6627519 B2
Publication typeGrant
Application numberUS 09/963,440
Publication dateSep 30, 2003
Filing dateSep 27, 2001
Priority dateJan 18, 2001
Fee statusLapsed
Also published asCN1366331A, EP1225625A1, US20020094663
Publication number09963440, 963440, US 6627519 B2, US 6627519B2, US-B2-6627519, US6627519 B2, US6627519B2
InventorsYong-Bum Kwon, Jong-Hyun Lee
Original AssigneeComtecs Co., Ltd., Yong-Bum Kwon, Jong-Hyun Lee
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of manufacturing an SOI (silicon on insulator) wafer
US 6627519 B2
This invention is to manufacturing of SOI (Silicon On Insulator) wafer; with respect to manufacturing of SOI wafer, preparation process of silicon wafer with desired thickness (100), deposition of Alumina (Al2O3) as insulator by an ALE (Atomic Layer Epitaxial) method such as ALCVD, ALD, ASCVD, etc . . . (110), bonding of this wafer with another silicon wafer by various bonding methods (120), Cutting of this bonded wafer by various methods of cutting (130), Polishing the surface of the cut wafer (140). For the insulator material, titanium oxide (TiO2) or tantalum oxide (Ta2O5) can be used other than Alumina (Al2O3) and such bonding process can be done by unibonding method and cutting method can be done by Smart Cut process.
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What is claimed is:
1. A method of manufacturing an SOI (Silicon On Insulator) wafer, comprising the steps of:
preparing a first silicon wafer with designed thickness and diameter;
forming alumina (Al2O3) or other dielectric as an insulator layer on the surface of the prepared first silicon wafer by ALE process such as ALCVD, ALD, ASCVD, thereby forming a first resulting structure;
bonding a second silicon wafer on the alumina of the first resulting structure by a bonding method, thereby forming a second resulting structure;
cutting the bonded second resulting structure by a cutting method, thereby forming a third resulting structure; and
polishing the surface of the third resulting structure.
2. The method of claim 1, wherein subject of said insulator layer can be titanium oxide (TiO2) and tantalum oxide (Ta2O5) instead of alumina (Al2O3).

This invention is to suggest a different method of manufacturing SOI wafer and more specifically, to improve chemical, mechanical , and electrical properties of SOI wafer, to diversify the structure and composition of the wafer, and to improve on fabrication process of such wafers.

Silicon On Insulator type of wafers is widely used in wafer manufacturing process. This process is to form an insulator on top of the semiconductor wafer and then to form single crystal silicon layer before fabrication of semiconductor device.

SOI wafer is known to offer lateral and vertical isolation of integrated components and also to provide devices with superior electrical properties.

In a SOI wafer, two different processes are widely used in general. One of them is so called BE (Bond and Etch) method, which is to bond two wafers and etch back one of them in order to make a thin layer. The other is called SIMOX(Separation By Implantation of oxygen) method, which is to implant oxygen deep into the silicon wafer and form a buried oxide and a thin silicon layer by post-implantation heat treatment.

Smart Cut process is to implant hydrogen ions into an oxidized wafer A (through the insulator) by controlling the energy (depth) of hydrogen ions in order to control the film thickness. This wafer A is then bonded to another silicon wafer B. During subsequent annealing, bonded wafers separate at the region where the implanted hydrogen ions have stopped. This separation results in a thin Si film separated from the wafer B by a buried oxide. Finally, CMP process is applied in order to obtain a smoother surface and the desired thickness of the silicon film. This method is relatively easier than other processes such as SIMOX method and therefore, is being widely used recently.

In the Smart Cut technology mentioned above, the Smart Cut process disclosed in U.S. Pat. No. 5,882,987 (Smart Cut process with thin film semiconductor material on insulating film) claims to use CMP process in order to solve non-uniform surface problem and thin film formation problem, which are known problems associated with Smart Cut processes.

In case where SiO2 is used as an insulation film, the thickness and quality of the buried insulator is controlled with conventional technologies (oxidation), as shown in FIG. 4. Since the chemical properties change by heating above 1000° C. in dry oxygen ambient (see table 4), such a control is not perfect.


The invention is to generate SOI wafer despite all the known problems associated with it. It is the purpose of this invention to improve the film properties, to generate uniform surface structure without requiring high process temperature, and to diversify the nature of the insulating film. This new invention of SOI wafer manufacturing method includes steps of: (100) Preparation of silicon wafers with designed thickness and diameter; (110) forming alumina (Al2O3) insulation film or other dielectric film on the surface of the prepared silicon wafer by atomic layer epitaxial method such as ALCVD, ALD, ASCVD, etc.; (120) Bonding this wafer with another silicon wafer (oxidized or not) by various methods; (130) Cutting one of the bonded wafers by various methods; (140) Polishing the cut surface of the wafer.


These and other features, aspects and advantages of the present invention will become better understood with reference to the accompanying drawings, wherein:

FIG. 1 indicates a partial side view of the wafer, showing sequential manufacturing process of the invention;

FIG. 2 indicates a partial side view of the wafer, done by the SOI wafer manufacturing process of the invention;

FIG. 3 indicates the process flowchart explaining the SOI wafer manufacturing process of the invention ; and

FIG. 4 represents a conventional SiO2 film generating method.


The basic concept of the system configuration and methods of manufacturing are explained more in detail by the drawings. FIG. 1 indicates a partial side view of the wafer, showing sequential manufacturing process of the invention; FIG. 2 indicates a partial side view of the wafer, done by the SOI wafer manufacturing process of the invention; FIG. 3 indicates the process flowchart explaining the SOI wafer manufacturing process of the invention; and FIG. 4 represents conventional SiO2 film generating method.

The characteristic of this invention is that various methods are used for bonding and cutting wafers in order to achieve SOI-like structures using dielectric films such as alumina (Al2O3), titanium oxide (TiO2), tantulum oxide (Ta2O5), etc . These films are easy to fabricate by ALCVD and have more applications than conventional SiO2 films in subsequent circuit integration processes. According to this invention, besides the conventional Smart Cut® processes, other methods can be used such as BE (Bond & Etch) and Eltran (Separation By using Porous Silicon). This invention uses alumina instead of SiO2 and also utilizes atomic layer epitaxial method instead of conventional CVD process or oxygen implantation. Alumina is a lot easier to make thin films since it is more ductile and has greater conductivity than SiO2. Furthermore, it's more corrosion-resistant due to its superior chemical reactivity than with SiO2. Other key advantages are the better thermal conductivity and increased dielectric constant.

Other insulating materials suggested in this invention are titanium oxide(TiO2), tantalum oxide(Ta2O5), hafnium oxide, etc. Their characteristics are known to be either similar or better than that of alumina(Al2O3). One method of Atomic Layer Epitaxial (ALE) is a process where films are generated by stack of atomic layers using chemical absorption and desorption. ALE is preferred since it is by using surface saturated reaction to deposit the desired material by sequential deposition in order to produce very thin film thus able to achieve precise control of film thickness. The main difference as compared to conventional silicon-on-sapphire material is that instead of growing Si on Sapphire (which generates many defects), in this invention alumina is grown on silicon.

By using the proposed method in this invention, it is possible to generate alumina films at below 700° C. which is significantly lower than 1000° C. required for SiO2 film, with 1000 times less current leakage rate than that of SiO2 film. Furthermore, the life of the film is increased due to corrosion-resistant characteristics of alumina film, and it is also possible to vary the film aracteristics by varying the film thickness due to precise control of atomic layers.

The following is a detailed description of the exemplary embodiment and only is an example of this invention. Other ideas and purpose can be derived from this invention and such derivatives are all included within the technical aspect of this invention.


Process 1:

(100) Prepare a silicon wafer with desired thickness/diameter

Process 2:

(110) Generate alumina film (or other dielectric) as an insulator on top of the wafer via ALE process such as ALCVD, ALD, ASCVD, etc.

Process 3:

(120) Bonding the first wafer, having the alumina insulator, with another silicon wafer (oxidized or not) via Unibond® or other bonding methods

Process 4:

(130) Cut one of the bonded wafers via Smart Cut® method or other cutting methods

Process 5

(140) Polish the cut surface of the bonded wafers to make it smooth. This new method of manufacturing SOI water is by using alumina, titanium oxide, tantalum oxide or other oxides instead of SiO2 as insulator. The new SOI wafers will be fabricated with less than ⅔ of the heat required for SiO2 process. By doing so, it is possible to achieve both cost reduction and superior characteristics of the Si film and buried dielectric (high thermal conductivity and dielectric constant, good quality Si—Al2O3 interface, etc.)

In this new manufacturing method, leakage current can be reduced more than 1000 times, as compared to SiO2, thus achieving significant improvement in electrical properties and flexibility.

In addition, improvement in design application and longer lifetime can be achieved by utilizing the ability of the ALCVD process to control atomic scale level and high breakdown voltage.

It will be apparent to those skilled in the art that various controls and variations can be made in the present invention without deviating from the spirit or scope of the invention. Thus, it is intended that the present invention covers the controls and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Patent Citations
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US7772062Feb 8, 2005Aug 10, 2010Taiwan Semiconductor Manufacturing Co., Ltd.MOSFET having a channel mechanically stressed by an epitaxially grown, high k strain layer
US7790569 *Nov 29, 2004Sep 7, 2010X-Fab Semiconductor Foundries AgProduction of semiconductor substrates with buried layers by joining (bonding) semiconductor wafers
US7858494 *Aug 24, 2006Dec 28, 2010Sumco CorporationLaminated substrate manufacturing method and laminated substrate manufactured by the method
US8044471Jul 20, 2010Oct 25, 2011Taiwan Semiconductor Manufacturing Co., Ltd.MOSFET having a channel mechanically stressed by an epitaxially grown, high K strain layer
US8093136Dec 22, 2008Jan 10, 2012Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing SOI substrate
US8330245 *Feb 4, 2011Dec 11, 2012Memc Electronic Materials, Inc.Semiconductor wafers with reduced roll-off and bonded and unbonded SOI structures produced from same
US8440541Feb 4, 2011May 14, 2013Memc Electronic Materials, Inc.Methods for reducing the width of the unbonded region in SOI structures
US20050184400 *Feb 7, 2005Aug 25, 2005Kobrinsky Mauro J.Method and structure for interfacing electronic devices
US20060081902 *Oct 17, 2005Apr 20, 2006Seiko Epson CorporationFerroelectric memory and method of manufacturing the same
US20060175671 *Feb 8, 2005Aug 10, 2006Taiwan Semiconductor Manufacturing Company, Ltd.MOSFET having a channel mechanically stressed by an epitaxially grown, high k strain layer
US20070048971 *Aug 24, 2006Mar 1, 2007Akihiko EndoLaminated Substrate Manufacturing Method and Laminated Substrate Manufactured by the Method
US20080036041 *Nov 29, 2004Feb 14, 2008Roy KnechtelProduction Of Semiconductor Substrates With Buried Layers By Joining (Bonding) Semiconductor Wafers
US20090170287 *Dec 22, 2008Jul 2, 2009Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing soi substrate
US20100283109 *Jul 20, 2010Nov 11, 2010Taiwan Semiconductor Manufacturing Co., Ltd.Mosfet having a channel mechanically stressed by an epitaxially grown, high k strain layer
US20110204471 *Aug 25, 2011Memc Electronic Materials, Inc.Semiconductor wafers with reduced roll-off and bonded and unbonded soi structures produced from same
U.S. Classification438/459, 257/E21.568, 438/785
International ClassificationH01L27/12, H01L21/02, H01L21/762, H01L21/20
Cooperative ClassificationH01L21/76254
European ClassificationH01L21/762D8B
Legal Events
Sep 27, 2001ASAssignment
Oct 16, 2006FPAYFee payment
Year of fee payment: 4
Mar 30, 2011FPAYFee payment
Year of fee payment: 8
May 8, 2015REMIMaintenance fee reminder mailed
Sep 30, 2015LAPSLapse for failure to pay maintenance fees