US 6628215 B2 Abstract A method and apparatus for state assignment of a logic circuit comprises receiving internal state representations for the logic circuit, determining binary code for the internal state representations by successively dividing the states into disjoint sets of ever decreasing size Each disjoint set of a pair is assigned a one bit at each division step. The division can continue for all bits to be encoded, or the division can be halted and exact encoding used for the encoding of the final number of bits.
Claims(125) 1. A method of state assignment of a logic circuit, the method comprising:
receiving state transition data for the logic circuit the state transition data including internal state representations;
encoding the internal state representations by determining binary code comprising a plurality of bits for said internal state representations one bit at a time until a predetermined number of bits is left to be encoded to provide an encoding of said internal state representations; and
exhaustively evaluating possible encodings for the predetermined number of bits left to be encoded having regard to the determined binary code or codes for said internal state representations to determine an optimum state assignment for the logic circuit.
2. The method according to
3. The method according to
4. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
5. The method according to
6. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
7. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
8. The method according to
determining binary code for said internal state representations one bit at a time by repeatedly dividing the internal state representations into disjoint sets by reference to next states transited to from present states in response to an input to the logic circuit and assigning a binary code to each bit in dependence upon the divisions;
where the sets of internal state representations become repeatedly smaller after each division, and the divisions of the internal state representations are determined in dependence upon the encoding of any previous divisions.
9. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
10. The method according to
identifying for a first bit at least one set of internal state representations for next states to which a set of internal state representations for present state transit upon an input to the logic circuit, the or each identified set being one of a pair of disjoint sets dividing said internal state representations into two sets;
assigning a binary code to the first bit for each internal state representation dependent upon which set of the pair of disjoint sets the internal state representations belongs to;
for any subsequent bits, subsequently identifying for each previously identified disjoint set for a previous bit, at least one set of internal state representations for next states to which a set of internal state representations for present states contained within the previously identified disjoint set of internal state representations transit upon an input to the logic circuit and using the assigned binary code of a previous bit as an input, the or each subsequently identified set being one of a pair of disjoint sets dividing the previously identified disjoint set of internal state representations into two sets; and
assigning a binary code to any subsequent bit for each said internal state representation dependent upon which set of the or each pair of disjoint sets the internal state representation belongs.
11. The method according to
12. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
13. The method according to
14. The method according to
15. A computer system for the state assignment of a logic circuit, the computer system composing:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
16. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
17. The method according to
18. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
19. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
20. The method according to
(a) determining the set of said internal state representations which has a smallest number of internal state representations for next states transited to upon an input which are not in the set and which require encoding of said predetermined number of bits left to be encoded;
(b) defining default encodings for the predetermined number of bits left to be encoded for any said internal state representations for next states not in the set of internal state representations;
(c) exhaustively evaluating the possible encodings for the predetermined number of bits left to be encoded for said set of internal state representations to determine optimum encodings;
(d) combining said set of internal state representations with each logically adjacent partially encoded set to form a new set of internal state representations; and
(e) repeating steps (a) to (d) until said predetermined number of bits left to be encoded for all of said internal state representations have been encoded.
21. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
22. Computer program code for controlling a computer to implement the method of
23. A carrier medium carrying the computer program code of
24. A method of constructing a logic circuit comprising the method of
25. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
26. An apparatus for the state assignment of a logic circuit, the apparatus comprising:
receiving means for receiving state transition data for the logic circuit, the state transition data including internal state representations;
determining means for encoding the internal state representations by determining binary code comprising a plurality of bits for said internal state representations one bit at a time until a predetermined number of bits is left to be encoded to provide an encoding of said internal state representations; and
evaluation means for exhaustively evaluating all possible encodings for the predetermined number of bits left to be encoded having regard to the determined binary code or codes for said internal state representations to determine an optimum state assignment for the logic circuit.
27. The apparatus according to
28. The apparatus according to
29. The apparatus according to
30. The apparatus according to
31. The apparatus according to
identifying means for identifying for a first encoded bit at least one set of internal state representations for next states to which a set of internal state representations for present states transit upon an input to the logic circuit, the or each identified set being one of a pair of disjoint sets dividing said internal state representations into two sets; and
assigning means for assigning a binary code to the first bit for each internal state representation dependent upon which set of the pair of disjoint sets the internal state representation belongs to;
wherein said identifying means is adapted, for any subsequent bits and for each previously identified disjoint set, to subsequently identify at least one set of internal state representations for next states to which a set of internal state representations of present states contained within the previously identified disjoint set of internal state representations transit upon an input to the logic circuit and using the assigned binary code of a previous bit as an input, the or each subsequently identified set being one of a pair of disjoint sets dividing the previously identified disjoint set of internal state representations into two sets; and
said assigning means is adapted to assign a binary code to any subsequent bit for each said internal state representation dependent upon which set of the or each pair of disjoint sets the internal state representation belongs.
32. The apparatus according to
33. The apparatus according to
34. The apparatus according to
35. The apparatus according to
36. The apparatus according to
(a) determine the set of said internal state representations which has a smallest number of internal state representations for next states transited to upon an input which are not in the set and which require encoding of said predetermined number of bits left to be encoded;
(b) define default encodings for the predetermined number of bits left to be encoded of any said internal state representations for next states not in the set of internal state representations;
(c) exhaustively evaluate the possible encodings for the predetermined number of bits left to be encoded for said set of internal state representations to determine optimum encodings;
(d) combine said set of internal state representations with each logically adjacent partially encoded set to form a new set of internal state representations; and
(e) repeat (a) to (d) until said predetermined number of bits left to be encoded for all of said internal state representations have been encoded.
37. A method of state assignment for a logic circuit, the method comprising:
receiving state transition data for the logic circuit, the state transition data including internal state representations;
determining binary code for said internal state representations one bit at a time by repeatedly dividing the internal state representations into disjoint sets by reference to next states transited to from present states in response to an input to the logic circuit and assigning a one bit code to each of the states of the disjoint sets in dependence upon the divisions;
where the sets of internal state representations become repeatedly smaller after each division, and the divisions of the internal state representations are determined in dependence upon code determined as a result of any previous divisions.
38. The method according to
identifying for a first bit at least one set of internal state representations for next states to which a set of internal state representations for present states transit upon an input to the logic circuit, the or each identified set being one of a pair of disjoint sets dividing said internal state representations into two sets;
assigning a binary code to the first bit for each internal state representation dependent upon which set of the pair of disjoint sets the internal state representations belongs to;
for any subsequent bits, subsequently identifying for each previously identified disjoint set for a previous bit, at least one set of internal state representations for next states to which a set of internal state representations for present states contained within the previously identified disjoint set of internal state representations transit upon an input to the logic circuit and using the assigned binary code of a previous bit as an input, the or each subsequently identified set being one of a pair of disjoint sets dividing the previously identified disjoint set of internal state representations into two sets; and
assigning a binary code to any subsequent bit for each said internal state representation dependent upon which set of the or each pair of disjoint sets the internal state representation belongs.
39. The method according to
40. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
41. The method according to
42. The method according to
43. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
44. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
45. The method according to
46. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
47. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
48. Computer program code for controlling a computer to implement the method of
49. A method of constructing a logic circuit comprising the method
50. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
51. An apparatus for the state assignment of a logic circuit, the apparatus comprising:
receiving means for receiving state transition data for the logic circuit, the state transition data including internal state representations;
determining means for determining binary code for said internal state representations one bit at a time by repeatedly dividing the internal state representations into disjoint sets by reference to next states transited to from present states in response to an input to the logic circuit and for assigning a one bit code to each state of the disjoint sets in dependence upon the divisions;
said determining means being adapted to make the sets of internal state representations become repeatedly smaller after each division, and to determine the divisions of the internal state representations in dependence upon the encoding of any previous divisions.
52. The apparatus according to
identifying means for identifying for a first encoded bit at least one set of internal state representations for next states to which a set of internal state representations for present states transit upon an input to the logic circuit, the or each identified set being one of a pair of disjoint sets dividing said internal state representations into two sets; and
assigning means for assigning a binary code to the first bit for each internal state representation dependent upon which set of the pair of disjoint sets the internal state representation belongs to;
wherein said identifying means is adapted, for any subsequent bits and for each previously identified disjoint set, to subsequently identify at least one set of internal state representations for next states to which a set of internal state representations of present states contained within the previously identified disjoint set of internal state representations transit upon an input to the logic circuit and using the assigned binary code of a previous bit as an input, the or each subsequently identified set being one of a pair of disjoint sets dividing the previously identified disjoint set of internal state representations into two sets; and
said assigning means is adapted to assign a binary code to any subsequent bit for each said internal state representation dependent upon which set of the or each pair of disjoint sets the internal state representation belongs.
53. The apparatus according to
54. The apparatus according to
55. The apparatus according to
56. The apparatus according to
identifying means for identifying, for a first encoded bit, at least one set of internal state representations for next states to which a set of internal state representations for present states transit upon an input to the logic circuit, the or each identified set being one of a pair of disjoint sets dividing said internal state representations into two sets; and
assigning means for assigning a binary code to the first bit for each internal state representation dependent upon which set of the pair of disjoint sets the internal state representation belongs to;
wherein said identifying means is adapted, for any subsequent bits and for each previously identified disjoint set, to subsequently identify at least one set of internal state representations for next states to which a set of internal state representations of present states contained within the previously identified disjoint set of internal state representations transit upon an input to the logic circuit and using the assigned binary code of a previous bit as an input, the or each subsequently identified set being one of a pair of disjoint sets dividing the previously identified disjoint set of internal state representations into two sets; and
said assigning means is adapted to assign a binary code to any subsequent bit for each said internal state representation dependent upon which set of the or each pair of disjoint sets the internal state representation belongs.
57. A method of optimising state assignments of a logic circuit, the method comprising:
receiving state data for the logic circuit, the state data including internal state representations each being encoded with a plurality of binary bits;
encoding the plurality of binary encoded bits of each internal state representation as at least one symbolic representation; and
determining optimum binary codes for the symbolic representations of the or each set having regard to any binary codes for each representation.
58. The method according to
exhaustively evaluating possible encodings for the predetermined number of bits left to be encoded having regard to the determined binary code or codes for said internal state representations to determine an optimum state assignment.
59. The method according to
(a) determining the set of said internal state representations which has the smallest number of internal state representations for next states transited to upon an input which are not in the set and which require encoding of said predetermined number of bits;
(b) defining default encodings for the predetermined number of bits of any said internal state representations for next states not in the set;
(c) exhaustively evaluating the possible encodings for the predetermined number of bits for said set of internal state representations to determine optimum encodings;
(d) combining said set with each logically adjacent partially encoded set to form a new set; and
(e) repeating steps (a) to (d) until said predetermined number of bits for all of said internal state representations have been encoded.
60. Computer program code for controlling a computer to implement the method of
61. A method of constructing a logic circuit comprising the method
62. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
63. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
64. The method according to
65. The method according to
66. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
67. The method according to
68. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
69. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
70. The method according to
determining binary code for said internal state representations one bit at a time by repeatedly dividing the internal state representations into disjoint sets by reference to next states transited to from present states in response to an input to the logic circuit and assigning a binary code to each bit in dependence upon the divisions;
where the sets of internal state representations become repeatedly smaller after each division, and the divisions of the internal state representations are determined in dependence upon the encoding of any previous divisions.
71. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
72. The method according to
identifying for a first bit at least one set of internal state representations for next states to which a set of internal state representations for present state transit upon an input to the logic circuit, the or each identified set being one of a pair of disjoint sets dividing said internal state representations into two sets;
assigning a binary code to the first but for each internal state representation dependent upon which set of the pair of disjoint sets the internal state representations belongs to;
for any subsequent bits, subsequently identifying for each previously identified disjoint set for a previous bit, at least one set of internal state representations for next states to which a set of internal state representations for present states contained within the previously identified disjoint set of internal state representations transit upon an input to the logic circuit and using the assigned binary code of a previous bit as an input, the or each subsequently identified set being one of a pair of disjoint sets dividing the previously identified disjoint set of internal state representations into two sets; and
assigning a binary code to any subsequent bit for each said internal state representation dependent upon which set of the or each pair of disjoint sets the internal state representation belongs.
73. The method according to
74. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
75. The method according to
76. The method according to
77. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
78. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
79. The method according to
80. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
81. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
82. Computer program code for controlling a computer to implement the method of
83. A method of constructing a logic circuit comprising the method
84. A computer system for the state assignment of a logic circuit, the computer system comprising:
a program store for storing processor readable and implementable instructions; and
a processor for reading and implementing the instructions in the program store;
wherein the instructions stored in the program store comprise instructions for controlling the processor to carry out the method of
85. An apparatus for optimising state assignments of a logic circuit, the apparatus comprising:
receiving means for receiving state data for the logic circuit, the state data including internal state representations each being encoded with a plurality of binary bits;
symbolic means for encoding the plurality of binary encoded bits of each internal state representation as at least one set of symbolic representations; and
determining means for determining optimum binary codes for the symbolic representations of the or each set having regard to any binary codes for each representation.
86. The apparatus according to
evaluation means for exhaustively evaluating all the possible encodings for the predetermined number of bits having regard to the determined binary code or codes for said internal state representations to determine the optimum state assignment for the logic circuit.
87. The apparatus according to
88. The apparatus according to
89. The apparatus according to
90. The apparatus according to
(a) determine the set of said internal state representations which has the smallest number of internal state representations for next states transited to upon an input which are not in the set and which require encoding of said predetermined number of bits;
(b) define default encodings for the predetermined number of bits of any said internal state representations for next states not in the set;
(c) exhaustively evaluate the possible encodings for the predetermined number of bits for said set of internal state representations to determine optimum encodings;
(d) combine said set with each logically adjacent partially encoded set to form a new set; and
(e) repeat (a) to (d) until said predetermined number of bits for all of said internal state representations have been encoded.
91. The apparatus according to
92. The apparatus according to
identifying means for identifying for a first encoded bit at least one set of internal state representations for next states to which a set of internal state representations for present states transit upon an input to the logic circuit, the or each identified set being one of a pair of disjoint sets dividing said internal state representations into two sets; and
wherein said identifying means is adapted for any subsequent bits and for each previously identified disjoint set to subsequently identify at least one set of internal state representations for next states to which a set of internal state representations of present states contained within the previously identified disjoint set of internal state representations transit upon an input to the logic circuit and using the assigned binary code of a previous bit as an input, the or each subsequently identified set being one of a pair of disjoint sets dividing the previously identified disjoint set of internal state representations into two sets; and
93. The apparatus according to
94. The apparatus according to
95. The apparatus according to
96. The apparatus according to
97. A carrier medium carrying computer readable code for controlling a computer to execute a method of state assignment of a logic circuit, the method comprising:
receiving state transition data for the logic circuit, the state transition data including internal state representations;
encoding the internal state representations by determining binary code comprising a plurality of bits for said internal state representations one bit at a time until a predetermined number of bits is left to be encoded to provide an encoding of said internal state representations; and
exhaustively evaluating possible encodings for the predetermined number of bits left to be encoded having regard to a least one determined binary code for said internal state representations to determine an optimum state assignment for the logic circuit.
98. The carrier medium according to
99. The carrier medium according to
100. The carrier medium according to
101. The carrier medium according to
determining binary code for said internal state representations one bit at a time by repeatedly dividing the internal state representations into disjoint sets by reference to next states transited to from present states in response to an input to the logic circuit and assigning a binary code to each bit in dependence upon the divisions;
where the sets of internal state representations become repeatedly smaller after each division, and the divisions of the internal state representations are determined in dependence upon the encoding of any previous divisions.
102. The carrier medium according to
identifying for a first bit at least one set of internal state representations for next states to which a set of internal state representations for present state transit upon an input to the logic circuit, each identified set being one of a pair of disjoint sets dividing said internal state representations into two sets;
assigning a binary code to the first bit for each internal state representation dependent upon which set of the pair of disjoint sets the internal state representations belongs to;
for any subsequent bits, subsequently identifying for each previously identified disjoint set for a previous bit, at least one set of internal state representations for next states to which a se of internal state representations for present states contained within the previously identified disjoint set of internal state representations transit upon an input to the logic circuit and using the assigned binary code of a previous bit as an input, the or each subsequently identified set being one of a pair of disjoint sets dividing the previously identified disjoint set of internal state representations into two sets; and
103. The carrier medium according to
104. The carrier medium according to
105. The carrier medium according to
106. The carrier medium according to
107. The carrier medium according to
(a) determining the set of said internal state representations which has a smallest number of internal state representations for next states transited to upon an input which are not in the set and which require encoding of said predetermined number of bits left to be encoded;
(b) defining default encodings for the predetermined number of bits left to be encoded for any said internal state representations for next states not in the set of internal state representations;
(c) exhaustively evaluating the possible encodings for the predetermined number of bits left to be encoded for said set of internal state representations to determine optimum encodings;
(d) combining said set of internal state representations with each logically adjacent partially encoded set to form a new set of internal state representations; and
(e) repeating steps (a) to (d) until said predetermined number of bits left to be encoded for all of said internal state representations have been encoded.
108. A carrier medium carrying computer readable code for controlling a computer to carry out a method of state assignment for a logic circuit, the method comprising the steps of:
receiving state transition data for the logic circuit, the state transition data including internal state representations; and
determining binary code for said internal state representations one bit at a time by repeatedly dividing the internal state representations into disjoint sets by reference to next states transited to from present states in response to an input to the logic circuit and assigning a one bit code to each of the states of the disjoint sets in dependence upon the divisions;
wherein the sets of internal state representations become repeated smaller after each division, and the divisions of the internal state representations are determined in dependence upon code determined as a result of any previous divisions.
109. The carrier medium according to
identifying for a first bit at least one set of internal state representations for next states to which a set of internal state representations for present states transit upon an input to the logic circuit, the or each identified set being one of a pair of disjoint sets dividing said internal state representations into two sets;
110. The carrier medium according to
111. The carrier medium according to
112. The carrier medium according to
113. The carrier medium according to
114. A carrier medium carrying computer readable code for controlling a computer to carry out a method of optimizing state assignments of a logic circuit, the method comprising:
receiving state data for the logic circuit, the state data including internal state representations each being encoded with a plurality of binary bits;
encoding the plurality of binary encoded bits of each internal state presentation as at least one symbolic representation; and
determining optimum binary codes for the symbolic representations of the or each set having regard to any binary codes for each representation.
115. The carrier medium according to
encoding the internal state representations by determining binary code for said internal state representations one bit at a time until a predetermined number of bits is left to be encoded to provide an encoding of said internal state representations; and
exhaustively evaluating possible encodings for the predetermined number of bits left to be encoded having regard to the determined binary code or codes for said internal state representations to determine an optimum state assignment.
116. The carrier medium according to
(a) determining the set of said internal state representations which has the smallest number of internal state representations for next states transited to upon an input which are not in the set and which require encoding of said predetermined number of bits;
(b) defining default encodings for the predetermined number of bits of any said internal state representations for next states not in the set;
(c) exhaustively evaluating the possible encodings for the predetermined number of bits for said set of internal state representations to determine optimum encodings;
(d) combining said set with each logically adjacent partially encoded set to form a new set; and
(e) repeating steps (a) to (d) until said predetermined number of bits for all of said internal state representations have been encoded.
117. The carrier medium according to
118. The carrier medium according to
119. The carrier medium according to
120. The carrier medium according to
121. The carrier medium according to
identifying for a first bit at least one set of internal state representations for next states to which a set of internal state representations for present state transit upon an input to the logic circuit, the or each identified set being one of a pair of disjoint sets dividing said internal state representations into two sets;
assigning a binary code to the first but for each internal state representation dependent upon which set of the pair of disjoint sets the internal state representations belongs to;
122. The carrier medium according to
123. The carrier medium according to
124. The carrier medium according to
125. The carrier medium according to
Description The present invention generally relates to the design automation of electronic logic circuits e.g. combinational circuits, finite state machines, and cascaded circuits. More particularly, the present invention relates to the synthesis of logic from symbolic high level languages. It is known that in high level descriptions of logic circuits the ability to represent the values of some signals at a higher level of abstraction (i.e. with mnemonics) is greatly desirable. However, to construct a physical circuit the mnemonics must be assigned unique binary codes. It is known that the choice of binary codes has a dramatic effect on the speed, silicon area, and power consumption of the final implemented circuit. Table 1 below gives an example of the binary encoding of 7 mnemonics of a logic circuit.
The minimum number of bits necessary to encode the mnemonics is p, where p is the smallest power of 2 such that 2 The above formula for p gives the minimal number of bits necessary for the encoding of the states of a logic circuit given by mnemonics. Thus, for 5 to 8 mnemonics at least 3 bits are needed, for 9 to 16 mnemonics at least 4 bits are needed, for 17 to 32 mnemonics at least 5 bits are needed, etc. In the example given in Table 1, a unique binary encoding is given to each mnemonic. However, the choice of the binary encoding to be given to each mnemonic affects the speed area and power consumption of the implemented circuit. Thus, the task of choosing the binary codes is a key step in the implementation of circuits. Unfortunately, this task is very complex. Table 2 below shows the number of distinct minimal length encodings for circuits with various numbers of mnemonics.
As Table 2 shows, for circuits with nine mnemonics there are at least 10,810,800 distinct minimal length encodings. An exhaustive evaluation of each encoding is thus not feasible. The solution to the problem of the assignment of encodings to the mnemonics of the circuits have been the target of a great deal of work in the prior art. However, the problem of the prior art methods is that they are wholly heuristic and yield slow, area hungry and power hungry circuits. In one prior art method disclosed in a paper by G De Micheli et al entitled “Optimal State Assignment of Finite State Machines” (IEEE Transactions on Computer Aided Design, Vol. CAD-4, No. 3, July 1985, pages 269-285), a heuristic technique is used in which states which have the same next state and output for a given input are noted. These states are to be given adjacent assignments. Another heuristic is then used to define the complete code of each of the states so as to satisfy as many of the adjacency conditions as possible. This technique attempts to minimise the literal count. This technique is however limited since although it is known that the literal count is related to the area of the final circuit implementation in certain technologies, in other technologies such as field programmable gate arrays, literal count bears a weak relationship to the quality of the final implementation. In another prior art method disclosed in a paper by T Villa and A Sangiovanni-Vincentelli entitled “NOVA: State Assignment of Finite State Machine for Optimal Two-level Logic Implementations” (26 In another prior art method disclosed in a paper by J. Monterio et al entitled “Bitwise Encoding of Finite State Machines” (7 FIG. 1 is a schematic diagram of a finite state machine which receives primary inputs and outputs primary outputs. The major component of the finite state machine is the combinational logic circuit Thus the inventors of the present invention have identified that in the approach of Monterio et al the omission of the consideration of the primary outputs and previously determined encoding bits in the heuristic reduces the effectiveness of the technique. The approach by Monterio et al is also restricted to minimal length encoding and this does not always result in the best circuit from the viewpoint of area and/or speed. Further, this approach uses a technique for the state assignment of finite state machines in which the finite state machine is decomposed by partitioning. This technique suffers from the disadvantage of the need to find preserved partitions in the set of mnemonic states. Such partitions are not always present. It is thus an object of the present invention to provide a circuit design method and apparatus in which the disadvantages of the prior art methods are overcome and circuits of desired speeds, silicon area, and power consumption can be produced. In accordance with a first aspect of the present invention, there is provided a method and apparatus for determining the binary encodings of a circuit which is in part heuristic and in part exact. In this aspect of the present invention the inventors have realised that the assignment of binary encodings to a circuit can benefit from the use of the exact technique when the number of bits to be encoded is reduced. The number of bits to be encoded can be reduced by initially using a heuristic technique to determine the encodings of a number of bits thereby leaving only a limited number of bits left to be encoded. The exact technique can be used for the encoding of the last few bits to be determined. The exact evaluation can be carried out using information on the preferred logic implementation e.g. Application Specific Integrated Circuits (ASIC's) or Field Programmable Gate Arrays (PPGA's). Thus this allows the preferred implementation to be taken into account during the state assignment. In this aspect of the present invention, any conventional heuristic technique can be used for the encoding of the initial bits. In this aspect of the present invention, the search can be successively divided into blocks by the encoding of initial bits using the heuristic technique. Each block is exhaustively evaluated in a determined sequence. Either the literal count can be evaluated, or the evaluation can be made on any conventional synthesis tool relative to any conventional vendors library. As each block is evaluated, it is combined with the next block in the sequence and the mnemonics of this block are encoded relative to the encodings already obtained for the preceding block. In this way, the complete circuit is encoded in an incremental manner block-by-block so that the resulting circuit has the sane functionality as the original circuit. The sequence of blocks to be evaluated is, in an embodiment, determined by identifying the block for which the number of next states not in the present states of the block is a minimum. For any next states which are not in the present states of the block, default encodings are used for these states thus allowing the evaluation of a virtual machine for which a small number of present states transit to unencoded next states within the set. When the block has been encoded, it is combined with the logically adjacent blocks as defined by the partial encodings to determine a larger block which has the minimum number of unencoded next states not in the present states set for the large block. This large block then evaluated by setting any next states not in the set to the default value as before. In this way the encodings for the blocks are incrementally determined relative to the encodings already obtained for previous blocks. An alternative way to determine the sequence of blocks is simply to order them according to the order of the gray code of the partial encoding. In a second aspect of the present invention, the symbolic state representations for a circuit are encoded one bit at a time by repeatedly dividing the symbolic state representations into disjoint sets and assigning a one bit code to each of the states of the disjoint sets in dependence upon the divisions. The disjoint sets become smaller after each division and the divisions are determined in dependence upon the encoding of previous divisions. Thus, in the repeated one bit encoding, a one bit code is assigned to each of the two disjoint sets generated by the division of either the state set or a previously generated disjoint set. The one bit code depends upon the manner in which the two disjoint sets were determined. At each repetition the combination of the thus far determined n divisions leads to at most 2 The divisions are determined by identifying the set of next states transited to from a set of present states in response to some combination of the primary and feedback inputs. This set and its compliment define a division. This division is encoded with a one bit binary code. In a preferred embodiment the identified set is encoded with 1 and its compliment with 0. The encoded disjoint sets are subsequently themselves divided as more divisions are calculated. The divisions can be made sequentially for the necessary number of bits to binary encode the symbolic state representation. Alternatively, the division of the disjoint sets can stop when the set size reaches a predetermined set size at which the encoding of the states in the disjoint sets can be determined exactly as described hereinabove with regard to the previous aspect of the present invention. The divisions do not necessarily comprise preserved partitions since they need not preserve cover in the set of next states. The set of next states for a set of present states can include other states not in the present state set. When assigning binary codes to the sets resulting from the division, in order to evaluate a block of the logic circuit resulting from the division of the circuit a default value can be used for these next states lying outside the present state set. The repeated determination of divisions results in the repeated division of the logic circuit into blocks using the next state table. When there are a number of candidate divisions, a division can be chosen to save logic i.e. to reduce the number of literals. At each stage of the division of the symbolic states into disjoint sets, there can be a number of possible divisions. In order to avoid having to proceed with encoding a larger number of possible divisions, in accordance with an embodiment of the present invention, for each encoded bit i.e. for each division, a cost of outputs of the circuit is determined and this is used in the determination of the optimum binary code for the encoded bit. The cost preferably comprises the cost of the primary outputs and any previously encoded bits. The cost can comprise the number of literals for the outputs and any previously encoded bits which form feedback outputs, and the optimum binary code is determined to minimise the number of literals. Thus in accordance with this embodiment, divisions can be chosen to take into account the number of literals. This can aid a search for the optimum encoding. The identification of a set of next states which is a subset of all states is preferably achieved for a plurality of logically adjacent possible inputs. It is known that larger blocks of logically adjacent is result in a saving of logic. This aspect of the present invention is applicable to both minimal length encoding and non minimal length encoding. For minimal length encoding, the number of bits used to binary encode the symbolic representations is a minimum. A non minimal length encoding, any number of bits can be used for encoding the symbolic representations. Whilst minimal length encoding will result in a minimum number of flip-flops, it may not result in the optimum circuit from the viewpoint of speed, area, or power consumption. For example, in field programmable gate array (FPGA's), each logical component has built into it a flip-flop and whether this flip-flop is used or not does not affect the overall area of the circuit. For many implementations, non-minimal length encoding, whilst requiring more flip-flops, can result in a higher speed circuit. Thus, for non minimal length encoding, any subsequent division, when combined with all previous divisions, need only result in encoded disjoint sets in which at least one of the sets is smaller than before. For minimal length encoding, the number of next states in the disjoint sets must be up to half the number of present states rounded up to the nearest power of 2 and the compliment set must also contain up to half the number of present states rounded up to the nearest power of 2. For minimal length encoding, where disjoint sets of the required size cannot be identified for an input, i.e. the sets are too small, sets of states for a plurality of different inputs can be unioned to form disjoint sets of the required size. Such disjoint sets do not in general result in the same logic saving since the plurality of inputs require a respective plurality of terms to define them. Logical adjacency is however provided for the unioned sets since they are assigned the same code for a binary bit (i.e. a feedback output). In accordance with a third aspects the present invention provides a method and apparatus for optimising state assignments for a circuit. A full binary encoding of a circuit can be optimised using this technique. A plurality of the binary encoded bits are encoded at a least one symbolic representation. Thus, for a 32 bit binary encoded representation, any number of bits can be encoded symbolically and any number of symbolic representations can be provided for segments of the code. For example the first and last 16 bits can be encoded separately as segment x and segment y, the last 16 bits only can be encoded as segment y, or the first 8, next 8 and last 16 bits can be encoded as segment x, segment y, segment z. Each of the symbolic representations resulting from this symbolic encoding can then be evaluated to determine the optimum binary codes for this symbolic representation having regard to any binary codes already provided. The determination of the optimum binary codes can be achieved using any conventional technique including the techniques of the previously described aspects of the present invention. This aspect of the present invention enables the tuning of the encoding already provided to obtain a more optimum binary encoding. Any number of the bits can be selected for optimisation and this can be repeated any number of times on various combinations of bits in order to try to optimise the encoding. This aspect of the present invention is applicable to any type of logic circuit not just sequential logic circuits e.g. finite state machines. When the technique is applied to logic circuits for which the next state depends on the present state the technique of the previous aspects can be employed for the encoding. Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: FIG. 1 is a schematic diagram of the finite state machine; FIG. 2 is a functional diagram of the apparatus in accordance with an embodiment of the present invention; FIG. 3 is a schematic diagram of a computer system for implementing the functional system of FIG. 2; FIG. 4 is a diagram illustrating the process of division to form disjoint sets of states; FIG. 5 is a flow diagram illustrating the process of minimal length state assignment for a finite state machine in accordance with a first embodiment of the present invention; FIG. 6 is a flow diagram illustrating the step of determining new divisions in FIG. 5 in more detail; FIG. 7 is a flow diagram illustrating the step of evaluating the new divisions in FIG. 5 in more detail; FIG. 8 is a flow diagram illustrating the step of processing the union list in FIG. 5 in more detail; FIG. 9 is a flow diagram illustrating the step of ordering the virtual finite state machines in FIG. 5 in more detail; FIG. 10 is a flow diagram illustrating the step of encoding the virtual finite state machines of FIG. 5 in more detail; FIG. 11 is a flow diagram illustrating a second embodiment of the present invention; FIG. 12 is a flow diagram illustrating the process of non-minimal length state assignment for a finite state machine in accordance with a third embodiment of the present invention; FIG. 13 is a flow diagram illustrating the step of determining new divisions in FIG. 12 in more detail; FIGS. 14 FIG. 15 is a flow diagram illustrating the step S FIG. 16 is a flow diagram illustrating the step S FIG. 17 is a flow diagram illustrating a sixth embodiment of the present invention. The first embodiment of the present invention will now be described in detail with reference to FIGS. 2 to This embodiment of the present invention implements minimal length encoding for symbolic (mnemonic) state representation. In this embodiment of the present invention the symbolic representations comprise states 1 to 7 of a sequential circuit (finite state machine—FSH). Conventionally, the state transition data for finite state machines can be given as a “KISS” table. The KISS table used in this embodiment of the present invention is illustrated in the form of a state transition table in Table 3 below.
The KISS table gives the next states in symbolic form and primary outputs in binary for present states in symbolic form and primary inputs in binary. The circuit can be considered as 6 interconnected logic functions: 3 for the primary outputs and 3 for the next states. Tables 4, 5 and 6 below illustrate the 3 logic functions for the three primary outputs.
Table 4 illustrates the primary output bit
Table 5 illustrates the primary output bit
Table 6 illustrates the primary output bit Table 7 below illustrates the logic function for the next states from present states for primary inputs.
The apparatus for implementing this embodiment of the present invention will now be described with reference to FIGS. 2 and 3. FIG. 2 is a schematic diagram of the functional components of this embodiment of the present invention. A finite state machine (FSM) data input device A union list processor A technology mapper A physical embodiment of the present invention will now be described with reference to FIG. 3 which illustrates a computer system The computer system The computer system The program storage device The working memory The method of operation of this embodiment of the present invention will now be described with reference to FIGS. 4 to Before considering the detailed implementation of this embodiment, an overview of the strategy of the technique of this embodiment will now be described with reference to FIG. Given a state machine with n states, we seek to divide the n states into two disjoint subsets each containing at most half the total number of states (minimal length encoding). The first bit of this state assignment will be set to 1 for states in one of the two sets and 0 for the states in the other set. This process is then repeated to determine the second bit of the state assignment. However, additional restrictions apply to this second division, namely that the two disjoints subsets are divided in half so that each of the resulting four sets are disjoint and contain at most a quarter of the smallest power of two no smaller than the number of states. This process is repeated until the resulting sets contain a predetermined number of states at which point an exact technique is used to evaluate the remaining encodings The predetermined number of states can be 0 in which case the process is repeated until the complete assignment is determined. FIG. 4 illustrates the division process for this embodiment. The finite state machine state set {1,2,3,4,5,6,7} can be divided as illustrated in FIG. 4 in two different ways. The state set {1,2,3,4,5,6,7} can be divided into the two disjoint sets {1,2,3,5} and {4,6,7} or the two disjoint sets {1,5,6,7} and {2,3,4}. At this division each of the sets is assigned a bit encoding is will be assigned to the set which was identified from the next states as a set of next states of the required size i.e. less than or equal to half the number of present states. In Table 7 above it can be seen that for the input --1 (where -- indicates “don't care”) all the present states can only transit to the next state set of {1,2,3,5}. Thus for the logically adjacent input is block --1, any encoding of the next two bits of the states will result in the first bit of all states under inputs --1 (and all present states) to be encoded by 1. This implies that half the table for the first bit can be represented logically as --1---1 where the first three bits are the primary inputs, the next three bits are the feedback inputs and the last bit is the output. This represents a significant logic saving. The next division which is carried out on the disjoint sets generates once again a number of disjoint sets for each previously determined disjoint set. Each of the disjoint sets will be assigned a second encoded bit in combination with the first encoded bit. Keeping track of previously encoded bits for sets generated by the division process is achieved by the division history. It can thus be seen from FIG. 4 that a number of possible divisions can result. For a four state machine {1,2,3,4} the only division possible are {{1,2},{3,4}}, {{1,3},{24}}, {{1,4},{2,3}}. The number of possible divisions grows very rapidly with the number of states of the machine. Therefore, it is in general not possible to examine all divisions. Thus the problem faced is to determine how to divide the state set into suitable parts in some way that does not require complete enumeration. This is achieved in this embodiment by looking for logic savings in the next state table by looking for sets of next states for logically adjacent inputs. In addition to determining suitable divisions, there is still the problem that a number of suitable divisions can be determined. Thus in order to estimate how efficient complete state assignment will be if the division is chosen, the suitability of each candidate division needs to be evaluated. In this embodiment of the present invention this evaluation of each division i.e. suitability of the encoding, is achieved by evaluating a cost of the outputs of the machine taking into account the previously selected encodings. This will be described in more detail hereinafter. The principles behind the division of the state set will now be considered in more detail. Given a state machine with n states, let m=[log A limited number of divisions are therefore derived from the next state table which are likely to lead to large savings in the implementation of the circuit. It is known in the theory of logic minimisation that larger logical groupings (powers of 2 of 1's) always lead to larger savings in the implementation of the circuit. For the finite state machine of this embodiment of the present invention, the inputs and outputs are already given in binary form and the states are mnemonics (see Table 3 above). Thus all adjacency relationships between the inputs are known. The only adjacency relationship known about states is that the set of all states form an adjacent block for any state assignment. This fact can be harnessed to ensure savings in the feedback outputs by identifying columns in the next state table. Once an encoding for a bit for a state has been defined some further adjacency information about the states has become available (because of their feedback output encoding). It now becomes known that all states in the set indexed by 1 satisfy an adjacency relationship as to the ones in the set indexed by 0. After the first bit encoding has been chosen, this relationship is exploited as well as the one due to columns. In general, as more bit encodings are chosen, more information becomes available and this is iteratively exploited. the first proposed way of grouping is to consider whole columns in the next state table. Suppose that a column contains at most 2 For example, it can be seen that the column with input 000 contains the states 1 and 3. If 1 is assigned as the first bit encoding to states 1 and 3, the logic implementation of the part of the machine receiving the input 000 given by Table 8 below.
Thus for feedback output 1, the logic implementation is as shown in Table 9 below:
It should be noted from Table 9 that the encoding of the present states is irrelevant. An input of 000 will always result in a feedback output of 1 since the next state always lies in the set {1,3}. A further proposed way of grouping is to consider logically adjacent columns. Suppose there are four vertically adjacent columns and a collection of states appearing in those columns is at most 2
Thus for the assigned feedback output (i.e. first encoded bit) of 1, the part of the machine takes the form as given in Table 11 below:
Thus based on the above principles, logical groupings of columns can be arrived at which result in a state assignment leading to large savings in the implementation of the first bit encoding of the next state function. It is required in this minimal length encoding embodiment that at most 2 If blocks exist which contain less than the required number of states, i.e. number of states in the complementary set is greater than 2 Since it is known in the theory of logic minimisation that larger logically adjacent blocks of 1's lead to larger savings in the logical implementation, the method attempts to identify maximally logically adjacent groupings i.e. those that cannot be extended without increasing the number of states appearing in the logically adjacent columns to greater than 2 Details of the method of state assignment of the finite state machine in this embodiment will now be described with reference to FIGS. 5 to FIG. 5 is a flow diagram of the method implemented to assign states to the finite state machine This technique performs a “breadth first” search technique on the divisions since all the possible divisions for each bit encoding are determined and are evaluated. In this way, the “tree structure” illustrated in FIG. 4 is traversed in a breadth wise manner. Referring specifically now to FIG. 5, in step S In step S In step S Assuming in the first pass through i >3, in step S In step S When finally the divisions have been processed to a point at which the number of encoded bits left is 3, in step S Although this embodiment uses the evaluation step this is not essential. Ranking can then be carried out by first ranking those divisions not obtained from the union list by their width and then using the divisions obtained from the union list ranked arbitrarily. The process of determining the new divisions (step S In step S In step S In step S Then for each state in the state list a maximally adjacent region not containing the state is determined and added to the maximal block list in step S Any blocks with too few associated states are deleted from the maximal block list and added to the union list. If the maximal block list is empty (in step S Thus this process is a technique for computing all maximally adjacent collections of columns which contain at most 2 This technique will now be described in more detail with reference to the state transition data given for this embodiment in Table 3. As mentioned hereinabove, maximally adjacent columns are sought which contain at most 2 This method will now be described with reference to the example. To each input the set of states is associated which comprise the next states which can be transited to from any state under the above mentioned input. That is, the states appearing in the column indexed by the input. In the above example, the associations are given in Table 12 below:
This association can be viewed on a Karnaugh map as given in Table 13 below:
For each state a logic function is formed which is true if the state is not present in the column set associated to the input. All maximally adjacent blocks which cover the function are computed. Table 14 below indicates maximally adjacent blocks not containing state 1.
Thus the maximally adjacent blocks not containing state 1 are: 01-, 100. The maximally adjacent blocks not containing state 2 are given in Table 15 below:
Thus the maximally adjacent blocks not containing state 2 are: 00-, 11-. The maximally adjacent blocks not containing state 3 are given in Table 16 below:
Thus the maximally adjacent blocks not containing state 3 are: 10-, -01, -10, 1-0. The maximally adjacent blocks not containing state 4 are given in Table 17 below:
Thus the maximally adjacent states not containing state 4 are; 0--, --1. The maximally adjacent blocks not containing state 5 are given in Table 18 below:
Thus the maximally adjacent blocks not containing state 5 are: -00, -11, 01-, 0-0. The maximally adjacent blocks not containing state 6 are given in Table 19 below:
Thus the maximally adjacent blocks not containing, state 6 are; 1--, -0-, --1. The maximally adjacent blocks not containing state 7 are given in Table 20 below:
Thus the maximally adjacent blocks not containing state 7 are: 1--, -0-, --1. Each maximally adjacent block not containing a different state is now considered. All the other states which are also not present in the collection of columns comprising the given maximally adjacent blocks need to be computed. Consider the maximally adjacent region, subject to the condition that it does not contain state 1, 01-, it is known that this does not contain state 1. It is clear that some other state is not present in this block if and only if 01- is contained in or equal to some maximal block due to some other state. It can be seen that 01- is contained in or equal to 0-- and 01-. The first is a maximal block not containing state 4 and the second is a maximal block not containing state 5. Thus 01- is a maximal block not containing states 1,4 and 5. That is 01- is a maximally adjacent region containing the states 2,3,6 and 7. Repeating this procedure for each of the maximal regions defined by each state results in the list of maximally adjacent regions not containing at least one state and the states that they do contain which is given in Table 21 below:
By choosing maximal blocks i.e. by throwing away adjacent blocks which contain other adjacent blocks, the maximally adjacent blocks can be obtained as given in Table 22 below:
Of the above blocks, Table 23 below gives the blocks which are of the correct size to form a candidate division.
Table 24 below shows all maximally adjacent blocks which do not contain at least one state, but which are too large to form a candidate division.
It is thus necessary to compute all maximally adjacent blocks from which a candidate division can be formed. By restricting processing to the columns in the block 1-- and repeating the process as before, but only for the states 1,2,3,4, and 5, all maximally adjacent blocks in the adjacent block 1-- can be computed. It should be noted that this process will either result in no blocks containing at most 4 states, or will lead to maximally adjacent blocks with at most 4 states. The restricted column Karnaugh map given in Table 25 is formed.
The process then proceeds as before to determine maximally adjacent blocks not containing a state. Tables 26 to 30 are Karnaugh maps identifying maximally adjacent blocks that do not contain states 1, 2, 3, 4 and 5 respectively.
It can be seen from Table 26 that the maximally adjacent block within 1-- which does not contain state 1 is: 00. It can be seen from Table 27 that the maximally adjacent block within 1-- which does not contain state 2 is: 1-. It can be seen from Table 26 that the maximally adjacent blocks within 1-- which do not contain state 3 are: 0-, -0. It can be seen from Table 29 that the maximally adjacent block within 1-- which does not contain state 4 is: -1. It can be seen from table 30 that the maximally adjacent blocks within 1-- which do not contain state 5 are: 00, 11. By proceeding in this manner for all maximal blocks which are too large, it can be seen that all maximally adjacent blocks with at most 2 As mentioned hereinabove, once a candidate division has been chosen, further information about adjacent states become available. The method for exploiting this information will now be described. For any candidate division determined as described hereinabove, a second division of the n states into two disjoint subsets each containing at most 2 For any first bit encoding determined, a new machine is formed (a modified finite state machine) which has one extra input and one extra output, the input being 0 if the present state of the machine belongs to one of the chosen sets and 1 if it belongs to the complementary set. The output is 0 if the next state of the machine belongs to one of the chosen sets and 1 if it belongs to the complementary set. For the set 1, 2, 3, 5 encoded by 1 the set 4, 6, 7 encoded by 0 (as shown on the left hand side of FIG. 4) Table 31 below illustrates the modified machine.
The process of finding maximal adjacent blocks with at most 2
As before, maximal adjacent blocks with most 2 1. A collection of columns from the original machine and so the logic implementation will be independent of the present state of the block; or 2. A collection of columns from the modified machine. It should be noted that any such collection has all its present states encoded either by 1 or 0 and not both This implies that the logic implementation of the block must be independent of the present states comprising one of the disjoint sets determined by the first bit encoding. The second saving will now be demonstrated. By examining the table it can be seen that the block 10-0 (a collection of columns from the modified machine) contains the states 2, 4, 5. If 1 is assigned to the states and 0 is assigned to the complementary states 1, 3, 6, 7, then the four resulting sets and their encodings axe given in Table 33 below:
It can be seen that each of the four sets has at most 8/4=2 states. For feedback output 2, the part of the machine is given in Table 34 below:
If the second bit encoding i.e. the second feedback output is encoded as 1 for the set of states 2,4,5, Table 35 below illustrates the result.
It should be noted that the last two bits of the encoding of the present state are “don't cares” due to independence from the present states encoded by 0, by the first bit encoding. Table 36 below shows all maximally adjacent blocks in the modified machine which do not contain at least one of the states. Any block ending with a “don't care”, e.g. 01--, is a maximally adjacent block of columns from the original machine and so has its constraints automatically satisfied. Any block ending in 0, e.g. ---0, lies entirely in the bottom left hand corner of the modified machine and any block ending in 1, e.g. 10-1, lies entirely in the top left hand corner. As already demonstrated, in both of the later cases the constraints are also already satisfied.
If 01-- is chosen (a collection of columns from the original machine) with associated states 2,3,6 and 7, and 1 is assigned to these states and 0 is assigned to the states 1,4, and 5 (the complementary set), then the four resulting sets and their encodings are given in Table 37 below:
For feedback output 2, the following part of the machine is given in Table 38 below:
With the encoding of states 2,3,6 and 7 as 1, Table 38 can be expressed as given in Table 39 below:
As before, the maximally adjacent blocks which do not contain at least one state, but which are too large to form a division, can be explored further. For example, ---0 contains the states 1,2,3,4,5 and 7. Thus by restricting the column Karnaugh map to ---0 results in Table 40 below:
This can be searched as before to arrive at further maximally adjacent blocks and associated sets which may lead to divisions. The method of evaluating the encoding of new divisions (step S In step S FIG. 7 is a flow diagram illustrating the method of evaluating new divisions for the minimal length encoding technique of this embodiment. In step S Thus this technique establishes approximate minimum cost of the primary outputs and feedback outputs taking into account the partial state encoding due to the candidate division and previously picked divisions. This allows an informed decision on which partial assignment to pursue further for complete state assignment. This technique will now be described in more detail with reference to the example and the second bit encoding. If the complete encoding of states is known, the exact cost of any output function is completely determined by all the powers of two adjacency relationships between the states when all adjacency relationships are considered simultaneously. However, if only a partial encoding is known, then some of the adjacency relationships are still to be defined while others have been completely defined. The method of this embodiment of the present invention calculates an approximate minimum cost taking into account all powers of two adjacency relationships already defined and the method attempts to do so in a simultaneous fashion. This is achieved for all primary outputs and the feedback outputs defined by the partial encoding. Consider the example in which the two encodings which result in the disjoint sets and the encodings illustrated in Table 41 have been chosen.
On a Karnaugh map, this can be presented as given in Table 42 below:
Since 00 and 11 do not lie in an adjacent block on a Karnaugh map, the fact that no state from the set {4,8} can ever be adjacent to a state from the set {2,3} and vice-versa is arrived at Likewise, since 01 and 10 do not lie in an adjacent block, no state from the set {6,7} can be adjacent to a state from {1,5} and vice-versa. It should be noted however, that 00, 11, 01 and 10 together do lie in the adjacent block -- on a Karnaugh map, and so the set of all the states {1,2,3,4,5,6,7,8} is an adjacent set. The aim is to calculate the minimum cost for each primary and feedback output, taking into account these constraints. The minimum cost is calculated by constructing a logic function for each output that will be minimised by a logic minimiser. This constructed logic function will express both the output function and the adjacency constraints imposed on the states by the partial encoding. Table 43 below illustrates the logic function for feedback output 2:
Logic functions which express the fact that the set {1,2,3,4,5,6,7,8} lies in an adjacent block is first-constructed. This can be viewed on a Karnaugh map as illustrated in Table 44 below:
The indexing row and the column both contain the partial encoding of all disjoint sets, which allows the adjacency constraints between them to be expressed. Each T is a table of all inputs against all states. The tables on the diagonal represent the output function and the off-diagonal tables represent the adjacency constraints. Table 45 below is the T(4,8) table.
Table 46 below is the T(6,7) table:
Table 47 below is the T(2,3) table:
Table 48 below is the T(1,5) table.
Table 49 below is T(-) table:
Each table is encoded in the logic function by 11 input variables: 3 for the inputs of the machine and 8 for a one-hot encoding of each state. Combined with the 4 variables of the Karnaugh map, which consist of two partial codes, this results in a 15 variable function which has to be minimised. It should be noted that by setting all off-diagonal tables to T(-), i.e. a table filled with only “don't cares”, no adjacency constraints are imposed at all, so any states can occur with any other state in a single term of the minimised function. Table 50 below shows some terms of the logic function:
When Table 50 is minimised, Table 51 below is arrived at:
This minimised function can be expressed as Table 52 below:
This means that it requires at least 6 terms to implement this feedback output, taking into account the imposed adjacency constraints. Since no such constraints were imposed, it is known that the actual number of terms needed in the implementation of the circuit for this feedback output must be at least 6. It should be noted that the set 1,2,3,4,8 intersects the sets 2,3 and 4,8 non-trivially and it is known that no state from the set 2,3 can ever be adjacent to any state from the set 4,8 no matter how the last co-ordinate is chosen Thus -11 {1,2,3,4,8} can never be represented by a single term in the final solution. (It should be noted that 8 is a “don't care” state and so in columns -11 the output for state 8 could be set to zero, resulting in -11 {1,2,3,4}. However, the set 1,2,3,4 still intersects the sets 2,3 and 4,8 non-trivially, so this term still can not be represented by a single term in the final solution.) To arrive at a more accurate estimate of the cost for this output, which takes this adjacency constraint into account, the constructed function can be used with more restrictive adjacency constraints by changing the off-diagonal tables. In the four positions 00111 0110, 1100 and 1001 the off-diagonal tables are set to 0. This completely captures the constraints that no state from the set {4,8} can ever be adjacent to a state from the set {2,3} and that no state from the set {6,7} can be adjacent to a state from the set {1,5}. The constructed function then takes the form as given in Table 53 below:
Minimisation of the resulting logic function yields Table 54 below:
This minimised function can be interpreted as Table 55 below:
This contains 9 terms. It should be noted that no set: now violates the constraints that no state from the set {4,8} can ever be adjacent to a state from the set {2,3} and that no state from the set {6,7} can be adjacent to a state from the set {1,5}. It should be noted however, that the constraints imposed by the constructed function can be considered too strict. It has already been noted that 00, 11, 01 and 10 together do lie in the adjacent block -- on a Karnaugh map, and so the set of all the states {1,2,3,4,5,6,7,8} is an adjacent set. However, introducing the non-adjacency constraints, that no state from the set {4,8} can ever be adjacent to a state from the set {2,3} and that no state from the set {6,7} can be adjacent to a state from {1,5}, by this method prevents the adjacency block {1,2,3,4,5,6,7,8} from appearing in one term of the minimised function. This implies that the method as described above can result in an estimate which is worse than the true value. In the example the division which assigns 1 to 1, 2, 4, 6 and 0 to 3, 5, 7, 8 and it can be seen from the above minimised function that this results in at most 8 terms. Every adjacency constraint on sets in the above function is then satisfied and we can gather the terms 01-{1,4,5,8} and 01-{2,3,6,7} to form the term 01-1{,2,3,4,5,6,7,8}. The adjacency on the latter set is automatically satisfied. It can now be noted that 01-{1,2,3,4,5,6,7,8} did not appear as a term when no adjacency constraints were imposed. To improve the estimate of the minimum costs the following strategy can therefore be applied. First, the function with no constraints can be constructed. From the minimised representation all terms are picked that contain all states. It is known that the adjacency constraints for this set of states are always satisfied. It is also known that because this term has appeared in the minimum representation, it is very likely to appear in the minimum representation for the complete assignment. To preserve this term in the estimate of the minimum cost, it is now accepted as a term in the estimated minimum representation. This block is replaced in the output function by “don't cares”. The adjacency constraints are introduced and the resulting function is minimised. This term will then not show up again but the term has to be added to the obtained minimal representation to cover the original output function. It should be noted that in this way the block is covered by one term instead of two. If this is applied to the example, having identified the term 01-{1,2,3,4,5,6,7,8} in the minimised function without any constraints, a modified output function is constructed with a block 01-{1,2,3,4,5,6,7,8} replaced with “-don't cares”. This results in Table 56 below:
When the constrained function is constructed and minimising as before Table 57 below is arrived at:
If the removed term is added onto this Table 57, Table 58 below results:
Thus the current estimated minimum is 8 terms. If there were 3 binary encodings and there were any terms with four associated states, any terms with 8 states and with 4 states would be kept once the adjacency constraints due to the first two binary encodings have been introduced. Next the output function would be modified by replacing the kept blocks with “don't cares” and introducing the constraints due to the 3 binary encodings. Finally, this resulting function will be minimised and the kept terms added back in to arrive at the estimate. The method of processing the union list (step S In step S If the union list is empty all of the processing time has run out, in step S Thus in this process sets which are not of the required size can be unioned with other sets which are not of the required size in order to try to obtain sets of the required size to be used as divisions. When a anion of sets results in a set which is too large, this is deleted from the union list (step S The process for ordering virtual finite state machines (step S In step S Thus the result of this process is an ordered list of virtual finite state machines with partially encoded states and having 3 binary encodings left to be determined. An alternative method of ranking is to order the virtual machines by their partial code in the order given by gray encoding. The step of encoding the 3 final bits will now be described (step S In step S Thus this technique results in the exact encoding of the virtual finite state machines sequentially in accordance with the order and in dependence upon the previously encoded virtual finite state machines. In the first embodiment of the, present invention described hereinabove, logic saving is looked for by looking for next states which transit from all present states i.e. by inspecting columns. The present invention is however applicable to the use of partial columns i.e. looking for a set of present states which is less than all of the present states which transit to a set of next states of reduced size (for minimal length encoding of half size) for an input. Thus, in Table 3, it is possible to restrict the search to, for example, the top half of the table i.e. for present states 1 to 4. This can allow the identification of useful divisions which can result in logic saving since logical adjacency can be provided by a combination of logical adjacency of the inputs and a logical adjacency for a number (but not all) of the present states. A second embodiment of the present invention will now be described with reference to FIG. The first embodiment of the present invention, as described with reference to FIG. 5, utilises a breadth first search technique for minimal length encoding. The second embodiment of the present invention utilises a depth first or “greedy” search. In this technique, a single branch of the tree (see FIG. 4) is followed in order to determine an optimum encoding. This process will now be described in more detail with reference to the flow diagram of FIG. In step S If in step S If in step S Although the first and second embodiments of the present invention have been described as processes for minimal length encoding, the present invention is not limited to minimal length encoding. Minimal length encoding will minimise the number of flip-flops. This may not necessarily result in the fastest and/or smallest circuit. For some circuit implementations, non minimal length encoding is preferred. For example, in field programmable gate arrays, there are usually spare flip-flops available. Thus there is nothing to be gained by minimal length encoding and in fact by using more of the available logic a degree of parallism is obtained thus resulting in a faster logic circuit design. For non minimal length encoding, it is only necessary to identify a set of next states which is of reduced size compared to the set of present states. Thus it is possible for an eight state machine to require 8 bits to encode it, since the division used to determine the encoding of the bit can result in the division of the present state set of size one less than previous divisions with a compliment set of just 1. Although non-minimal length encoding will require more flip flops, for certain circuit implementations, this can result in faster circuits which may be preferable for certain applications. It is clear from this that the encoding of logic circuits would depend upon the target of the designer. The present invention can take into account such requirements by a designer. For example, where a designer wishes to ensure that minimal flip flops are used, minimal length encoding can be used, whereas where a designer wishes to ensure that optimal speed is achieved and the restriction on the amount of logic is relaxed, non minimal length encoding can be used in order to find useful divisions which will provide optimum encoding to suit the designers requirements. A third embodiment of the present invention will now be described with reference to FIGS. 12 and 13 which utilizes a breadth first search technique for non-minimal length encoding. In this technique once a series of divisions have generated disjoint sets which are sufficiently small to be exhaustively evaluated, the disjoint sets are stored in a list (LF) and are not further processed. The list (LF) contains a list of all of the disjoint sets resulting from divisions. These can then be exhaustively evaluated. Since in non-minimal length encoding there is no requirement to exactly split the sets in half, there is no need for the process of unioning sets. All that is required of the division is that it reduces the set size. Referring now specifically to FIG. 12, in step S In step S In step S In step S Once all of the tree structure has been evaluated, i.e. all divisions have been evaluated, or processing time has been exhausted, in step S The process of determining the new divisions (step S In step S In step S In step S Then for each state in the state list a maximally adjacent region not containing the state is determined and added to the maximal block list in step S The first criterion for ordering gives importance to divisions which are likely to lead to a large logic saving, as identified by their block size. The second criteria for ordering is an attempt to identify divisions which lead to even splitting of the sets i.e. produces disjoint sets more evenly in size. This causes the ordering to give higher preference to divisions which are closest to minimal length encoding divisions. The third criterion for ordering is to identify maximal blocks which contain the least number of states. This minimises the chances of these states occurring in the complement of the block and is therefore likely to lead to a logic saving. In the first embodiment of the present invention, this was the criteria used to identify blocks with the correct number of states suited for minimal length encoding. This ordering process tends to place divisions which are likely to be good divisions at the top of the list thus ensuring preferential processing. In step S In this breadth first search technique for non-minimal length encoding, the process for evaluating the new divisions (step S The step of ordering the virtual FSM's (step S A fourth embodiment of the present invention will now be described which utilizes a depth first or ‘greedy’ search technique for non-minimal length encoding. As for the technique of the second embodiment for minimal length encoding, a single branch of the tree is followed in order to determine an optimum encoding. The depth first non-minimal length encoding technique is identical to the technique disclosed with reference to FIG. A fifth embodiment of the present invention will now be described with reference to FIGS. 14 In the technique of the fifth embodiment of the present invention, if, during the repeated determinations to form a cluster, no solution is found i.e. the search reaches a point at which no more division can be found, divisions can be forced in one of two ways. The first technique used to try to force a divisions is to use non-maximal blocks. If this still does not result in any new divisions, a division can be generated that splits all of the largest disjoint sets. The process can then carry on with this forced division. This technique of forcing the division avoids the search terminating with an incomplete encoding. The forcing of a division can allow the search to continue to provide a full encoding. The use of forcing is essential for example when a permutation machine is to be encoded since right at the start for the first bit encoding no divisions can be found. Following the generation of a forced division, it is often the case that the search technique can complete the encoding. This embodiment of the present invention will now be described in more detail with reference to FIGS. 14 In step S In step S In step S If the number of clusters found is not yet the number of clusters required in step S If in step S It in step S New divisions due to the current division are then determined in step S For each new division, the size of the maximum disjoint set is then determined in step S The remaining new divisions are then added and ranked in the current list. The ranking is carried out with regard to the number of bits already encoded for this division (i.e. the size of its history or the depth in the tree), the width of the last block, the size of the largest disjoint set, and the number of associated states. The first criterion is therefore the depth in the tree, which is ordered in descending order (deepest first). Apart from this added first criterion, the ranking process corresponds to the lexicographical ranking used in the previous embodiments and described hereinabove. If a node corresponding to a division is determined as being a better node, the identification of this node is used to update the Best_Node_Sofar variable in step S In step S If in step S The first level of forcing to determine a division is carried out by step S In step S Once the working list is EMPTY, the number of clusters found has reached the desired level, or the number of iterations has reached the predetermined maximum and there are solutions found, the process of encoding the complete circuit is then carried out in step S In step S It can thus be seen from FIGS. 14 (a) normally using maximal blocks, (b) by the first forcing step using non-maximal blocks if (a) does not provide divisions, and (c) by the second forcing step of simply generating a division that splits all of the largest disjoint sets if neither (a) or (b) provide divisions. The process of determining the new divisions (step S In step S The process of determining new divisions using non maximal blocks (step S In step S A sixth embodiment of the present invention will now be-described with reference to FIG. This embodiment of the present invention utilises the technique as described hereinabove for the first to fifth embodiments to optimise the encoding already assigned to a logic circuit. Using this technique of this embodiment of the present invention, one or more symbolic representations can be assigned to any number of binary encoded bits of a binary encoded state representation. The assigned symbolic representation or representations, can then be binary encoded using the techniques of any of the first to fifth embodiments described hereinabove. For example, the 3 bit encoded state representation can be symbolically encoded as illustrated below:
In this example the symbolic representations a,b,c, and d can then be encoded using the techniques described hereinabove for using any conventional exact evaluation technique. The binary encoded state representation can be symbolically encoded with more than one symbolic code as illustrated below:
In this example the symbolic representations a The specific technique utilising the technique of embodiment 1 or embodiment 2 will now be described with reference to FIG. In step S If in step S For the next part in step S This embodiment of the present invention thus allows for a previously state assigned circuit to be tested to determine an optimum binary encoding by only symbolically encoding part of the binary code and optimising that part. This aspect of the present invention is applicable not just to the determination of binary encodings for finite state machines but is applicable to the determination of binary encodings for any form of circuits including combinational circuits and cascaded circuits. The concept lies in the breaking down of the circuit into virtual circuits which are separately state assigned. The present invention can be implemented on a special purpose machine or more conveniently in a programmed general purpose computer. In the latter case, the present invention can thus also be embodied as a computer program for controlling the general purpose computer to implement the method. The computer program can be provided to the general purpose computer on any carrier medium e.g. a storage medium such as a floppy disk, CDROM, programmable read only memory device, or programmable tape, or a signal carrying the computer program over a network e.g. the Internet. The result of the binary encoding technique described hereinabove with reference to the embodiments, can then be applied in the construction of a logic circuit using well known techniques of circuit fabrication. In the present invention, if a division cannot be found which splits the next state set, in order to avoid the technique failing to encode a circuit, a division can be arbitrarily chosen to enable the repeated dividing to be carried on. This technique is particularly useful when applying the invention to permutation machines for example. The aspects of the present invention described hereinabove can be used either separately or in any combination. Although the present invention has been described hereinabove with reference to specific embodiments, the present invention is not limited to these embodiments and it will be apparent to a skilled person in the art that modifications lie within the spirit and scope of the present invention. Patent Citations
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