|Publication number||US6665265 B1|
|Application number||US 09/435,749|
|Publication date||Dec 16, 2003|
|Filing date||Nov 8, 1999|
|Priority date||Nov 23, 1998|
|Publication number||09435749, 435749, US 6665265 B1, US 6665265B1, US-B1-6665265, US6665265 B1, US6665265B1|
|Inventors||S. Babar Raza|
|Original Assignee||Cypress Semiconductor Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (18), Non-Patent Citations (1), Referenced by (4), Classifications (14), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present application claims the benefit of provisional application Serial No. 60/109,505, filed Nov. 23, 1998 and is hereby incorporated by reference in its entirety.
The present application may be related to Ser. No. 09/436,314, now U.S. Pat. No. 6,502,197, filed concurrently and is hereby incorporated by reference in its entirety.
The present invention relates to circuits for validation of overhead bytes generally and, more particularly, to a method and an architecture for serial communication between an overhead generator and an overhead processor for such validation.
Referring to FIG. 1, a conventional circuit 10 is shown comprising an overhead processor 12, an overhead generator 14 and an overhead interface 16. The overhead processor 12 may receive or generate a number of signals TOH (transport overhead), TOHEN (transmit overhead enable), TOHCLK (transmit overhead clock), TPOHFP (transmit path overhead frame pulse) and TTOHFP (transmit transport overhead frame pulse) for transferring overhead bytes from the overhead generator 14 to the overhead processor 12. Generally, the signal TOH is the data for transmit, the signal TOHCLK is the clock for the overhead interface 16, the signal TTOHFP is the start of the frame from the overhead processor 12, and the signal TPOHFP is the payload indicator from the overhead processor 12. The signal TOHEN is an indicator received from the path overhead generator 14 indicating whether the current path overhead bytes should be used or not.
FIG. 2 shows the waveform for communication typical of the approach described above with respect to FIG. 1. As seen in FIG. 2, when the signal TOHEN is asserted on the first bit of the incoming overhead byte (i.e., TOH1, TOHEN), the overhead processor 12 recognizes the signal TOHEN as indicating that a valid overhead byte is to be used as the frame of a SONET device. When the signal TOHEN pin is de-asserted (i.e., TOH2) during the first bit of the overhead byte, the overhead processor 12 recognizes the overhead byte as not valid and uses the default value stored inside the overhead processor 12.
As shown in the description above, this previous approach uses a separate pin to communicate the validation of the overhead byte.
The present invention concerns a method of validating data between a path generator and a path processor, comprising the steps of (A) transmitting validation data from said path generator to said path processor on a data path, (B) sequentially transmitting data on said data path, (C) determining if the transmitted data is valid in response to the validation data and (D) using the overhead data by the processor when the overhead data is validated by the validation data.
Another aspect of the present invention concerns a circuit for validating overhead bytes comprising a data pin and a processor. The data pin may be configured to sequentially transmit one or more validation bits and an overhead data. The processor may be configured to determine if the transmitted overhead data is valid with respect to a previously sequentially transmitted validation data.
The objects, features and advantages of the present invention include a method and architecture that may provide (i) in-band signaling to communicate validation of overhead bytes, (ii) in-band communication in a serial communication scheme, and/or (iii) in-band communication without implementing a separate pin for such validation.
These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
FIG. 1 is a block diagram of an approach using a TOHEN pin for the validation signal received from a path overhead generator;
FIG. 2 is a timing diagram of the signal waveforms characteristic of the approach illustrated in FIG. 1;
FIG. 3 is a block diagram of the present invention for serial communication for validation of overhead bytes; and
FIG. 4 is a timing diagram illustrating signal waveforms characteristic of the present invention.
The present invention concerns a method and architecture for validation of overhead bytes using a serial communication scheme between an overhead generator and an overhead processor. A particular pattern received at a pin (e.g., TPOH—transmit path overhead) as the interface between the overhead generator and the overhead processor may frame and/or validate a data package transferred at the interface and may eliminate any need for another pin dedicated to such framing and/or validation. Validation bits may be transmitted on the pin, which may be followed by sequential serial transmission of the overhead data bytes. For each row of a SONET frame, payload data may be transmitted after several (e.g., three) overhead data bytes have been transmitted. The processor may be configured to determine if the overhead bytes are valid for the previously sequentially transmitted validation bits and may complete or accept their transfer of the overhead bytes if valid or ignore the overhead bytes if not valid.
Referring to FIG. 3, a circuit 100 is shown in accordance with a preferred embodiment of the present invention. The circuit 100 generally comprises an overhead interface 102, a path generator (e.g., a path overhead generator) 104, and a processor (e.g., a path overhead processor) 106. The circuit 100 may use a pin (e.g., TOHCLK) as a clock for the overhead interface 102, a pin (e.g., TTOHFP) as the start of the frame from an overhead processor 106 and a pin (e.g., TPOHFP) as the payload indicator from the overhead processor 104. The circuit 100 may eliminate implementing a separate pin for indicating the usability of the current path overhead bytes (e.g., TOHEN). Instead, the circuit 100 may use a data pin (e.g., TOH) to communicate validation information in addition to the transfer of data.
FIG. 4 illustrates the waveform characteristic of the interface 102 of the circuit 100. As shown in FIG. 4, the validation bits for each overhead byte may be sent first and then the overhead bytes may be sent sequentially. If the transmitted validation bits match a predetermined pattern, and thus are appropriate (e.g., valid) for the particular sequentially (or alternately, subsequently) transmitted overhead byte(s), the processor 106 generally uses (e.g., accepts) the particular valid overhead byte. If the transmitted validation bits are inappropriate (e.g., not valid) for the next bit, the processor 106 generally ignores the next byte. The processor 106 may contain suitable logic circuitry and/or memory to perform such a matching function. The number of validation bits may be a number n, where n is an integer.
The method and architecture of the present invention may use of in-band signaling to communicate validation of overhead bytes. The present invention may allow the elimination of one additional pin in the overhead interface 102, with appropriate savings of chip real estate and related expense.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3763758||Sep 25, 1972||Oct 9, 1973||Logetronics Inc||Control unit for minimizing water and power consumption in automatic film processors|
|US4534025 *||Feb 24, 1983||Aug 6, 1985||United Technologies Automotive, Inc.||Vehicle multiplex system having protocol/format for secure communication transactions|
|US4980887 *||Oct 27, 1988||Dec 25, 1990||Seiscor Technologies||Digital communication apparatus and method|
|US5029183 *||Jun 29, 1989||Jul 2, 1991||Symbol Technologies, Inc.||Packet data communication network|
|US5103461 *||Dec 19, 1990||Apr 7, 1992||Symbol Technologies, Inc.||Signal quality measure in packet data communication|
|US5157687 *||Dec 19, 1990||Oct 20, 1992||Symbol Technologies, Inc.||Packet data communication network|
|US5189671 *||Dec 20, 1991||Feb 23, 1993||Raynet Corporation||Apparatus and method for formatting variable length data packets for a transmission network|
|US5349588 *||Jun 23, 1992||Sep 20, 1994||Motorola, Inc.||Error detecting method and apparatus for data communications|
|US5432775 *||Dec 3, 1993||Jul 11, 1995||Advanced Micro Devices, Inc.||Auto negotiation system for a communications network|
|US5461622||Jun 14, 1994||Oct 24, 1995||Bell Communications Research, Inc.||Method and apparatus for using SONET overheat to align multiple inverse multiplexed data streams|
|US5668803 *||Nov 23, 1994||Sep 16, 1997||Symbol Technologies, Inc.||Protocol for packet data communication system|
|US5740189 *||Oct 3, 1996||Apr 14, 1998||Ford Motor Company||Integrity check method and system for serial-based communication|
|US5898674 *||Jul 7, 1997||Apr 27, 1999||Paradyne Corporation||System and method for performing non-disruptive diagnostics through a frame relay circuit|
|US6061365 *||Nov 16, 1995||May 9, 2000||Airspan Communications Corporation||Control message transmission in telecommunications systems|
|US6161198 *||Dec 23, 1997||Dec 12, 2000||Unisys Corporation||System for providing transaction indivisibility in a transaction processing system upon recovery from a host processor failure by monitoring source message sequencing|
|US6263443||Oct 11, 1997||Jul 17, 2001||Agere Systems Guardian Corp.||Simplified data link protocol processor|
|US6298038||Apr 24, 1997||Oct 2, 2001||Nortel Networks Limited||Transparent transport|
|US6502197||Nov 8, 1999||Dec 31, 2002||Cypress Semiconductor Corp.||Method and architecture for synchronizing a transport and path overhead generator and/or extractor to an path overhead transport and path processor|
|1||Practical Data Communications, by Roger L. Freeman, 1995, pp. 433-448.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7114106 *||Jul 22, 2002||Sep 26, 2006||Finisar Corporation||Scalable network attached storage (NAS) testing tool|
|US7139286 *||Mar 27, 2002||Nov 21, 2006||Nec Electronics Corporation||Method and system for insertion and extraction of overhead in SONET/SDH|
|US20020141455 *||Mar 27, 2002||Oct 3, 2002||Nec Corporation||Method and system for insertion and extraction of overhead in SONET/SDH|
|US20040015722 *||Jul 22, 2002||Jan 22, 2004||Finisar Corporation||Scalable network attached storage (NAS) testing tool|
|U.S. Classification||370/231, 710/55|
|International Classification||H04J3/14, H04L1/00, H04J3/04, H04Q11/04|
|Cooperative Classification||H04J3/14, H04J3/04, H04L1/00, H04J2203/006, H04J2203/0025|
|European Classification||H04J3/14, H04J3/04, H04L1/00|
|Nov 8, 1999||AS||Assignment|
Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RAZA, S. BABAR;REEL/FRAME:010378/0230
Effective date: 19991105
|Jun 18, 2007||FPAY||Fee payment|
Year of fee payment: 4
|Jun 16, 2011||FPAY||Fee payment|
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|Jan 9, 2014||AS||Assignment|
Owner name: RPX CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CYPRESS SEMICONDUCTOR CORPORATION;REEL/FRAME:031950/0752
Effective date: 20131218
|Jun 16, 2015||FPAY||Fee payment|
Year of fee payment: 12